24 #ifdef SECONDARY_RELOAD_CLASS
25 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
26 SECONDARY_RELOAD_CLASS (CLASS, MODE, X)
27 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
28 SECONDARY_RELOAD_CLASS (CLASS, MODE, X)
36 #define MAX_RELOADS (2 * MAX_RECOG_OPERANDS * (MAX_REGS_PER_ADDRESS + 1))
71 #ifdef GCC_INSN_CODES_H
82 enum reg_class rclass;
85 enum machine_mode inmode;
87 enum machine_mode outmode;
90 enum machine_mode mode;
121 int secondary_in_reload;
124 int secondary_out_reload;
128 enum insn_code secondary_in_icode;
130 enum insn_code secondary_out_icode;
139 unsigned int optional:1;
141 unsigned int nocombine:1;
143 unsigned int secondary_p:1;
146 unsigned int nongroup:1;
179 [FIRST_PSEUDO_REGISTER]
192 #if SWITCHABLE_TARGET
195 #define this_target_reload (&default_target_reload)
198 #define indirect_symref_ok \
199 (this_target_reload->x_indirect_symref_ok)
200 #define double_reg_address_ok \
201 (this_target_reload->x_double_reg_address_ok)
202 #define caller_save_initialized_p \
203 (this_target_reload->x_caller_save_initialized_p)
243 #define reg_equiv_constant(ELT) \
244 (*reg_equivs)[(ELT)].constant
245 #define reg_equiv_invariant(ELT) \
246 (*reg_equivs)[(ELT)].invariant
247 #define reg_equiv_memory_loc(ELT) \
248 (*reg_equivs)[(ELT)].memory_loc
249 #define reg_equiv_address(ELT) \
250 (*reg_equivs)[(ELT)].address
251 #define reg_equiv_mem(ELT) \
252 (*reg_equivs)[(ELT)].mem
253 #define reg_equiv_alt_mem_list(ELT) \
254 (*reg_equivs)[(ELT)].alt_mem_list
255 #define reg_equiv_init(ELT) \
256 (*reg_equivs)[(ELT)].init
274 #if defined SET_HARD_REG_BIT && defined CLEAR_REG_SET
281 struct insn_chain *next, *prev;
285 struct insn_chain *next_need_reload;
294 unsigned int need_reload:1;
297 unsigned int need_operand_change:1;
299 unsigned int need_elim:1;
301 unsigned int is_caller_save_insn:1;
325 #if defined SET_HARD_REG_BIT
332 enum machine_mode,
rtx);
334 #ifdef GCC_INSN_CODES_H
397 int,
enum machine_mode);
407 enum machine_mode,
enum machine_mode,