; start of dump from pass_ud_rtl_dce (../../src/gcc/dce.c:805) ;; Function ravif2 (ravif2, funcdef_no=0, decl_uid=364, cgraph_uid=0, symbol_order=0) starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) ravif2 Dataflow summary: ;; invalidated by call 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; hardware regs used 7 [sp] 16 [argp] 20 [frame] ;; regular block artificial uses 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; eh block artificial uses 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; entry block defs 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] ;; exit block uses 0 [ax] 6 [bp] 7 [sp] 20 [frame] ;; regs ever live 0 [ax] 1 [dx] 4 [si] 5 [di] 7 [sp] 17 [flags] ;; ref usage r0={7d,3u} r1={7d,2u} r2={5d} r4={9d,4u} r5={9d,5u} r6={1d,4u} r7={1d,8u} r8={4d} r9={4d} r10={4d} r11={4d} r12={4d} r13={4d} r14={4d} r15={4d} r16={1d,3u} r17={7d,1u} r18={4d} r19={4d} r20={1d,4u} r21={5d} r22={5d} r23={5d} r24={5d} r25={5d} r26={5d} r27={5d} r28={5d} r29={4d} r30={4d} r31={4d} r32={4d} r33={4d} r34={4d} r35={4d} r36={4d} r37={5d} r38={5d} r39={4d} r40={4d} r45={4d} r46={4d} r47={4d} r48={4d} r49={4d} r50={4d} r51={4d} r52={4d} r53={4d} r54={4d} r55={4d} r56={4d} r57={4d} r58={4d} r59={4d} r60={4d} r61={4d} r62={4d} r63={4d} r64={4d} r65={4d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={4d} r79={4d} r80={4d} r87={1d,2u} r89={1d,2u} r91={1d,3u} r93={1d,2u} r94={1d,1u} r95={1d,1u} r97={1d,3u} r103={1d,6u} r104={1d,1u} r105={1d,1u} r106={1d,1u} r107={1d,1u} r108={1d,1u} r109={1d,1u} r110={1d,1u} ;; total ref usage 398{337d,61u,0e} in 38{34 regular + 4 call} insns. ;; Reaching defs: ;; sparse invalidated ;; dense invalidated 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321 ;; reg->defs[] map: 0[0,6] 1[7,13] 2[14,18] 4[19,27] 5[28,36] 6[37,37] 7[38,38] 8[39,42] 9[43,46] 10[47,50] 11[51,54] 12[55,58] 13[59,62] 14[63,66] 15[67,70] 16[71,71] 17[72,78] 18[79,82] 19[83,86] 20[87,87] 21[88,92] 22[93,97] 23[98,102] 24[103,107] 25[108,112] 26[113,117] 27[118,122] 28[123,127] 29[128,131] 30[132,135] 31[136,139] 32[140,143] 33[144,147] 34[148,151] 35[152,155] 36[156,159] 37[160,164] 38[165,169] 39[170,173] 40[174,177] 45[178,181] 46[182,185] 47[186,189] 48[190,193] 49[194,197] 50[198,201] 51[202,205] 52[206,209] 53[210,213] 54[214,217] 55[218,221] 56[222,225] 57[226,229] 58[230,233] 59[234,237] 60[238,241] 61[242,245] 62[246,249] 63[250,253] 64[254,257] 65[258,261] 66[262,265] 67[266,269] 68[270,273] 69[274,277] 70[278,281] 71[282,285] 72[286,289] 73[290,293] 74[294,297] 75[298,301] 76[302,305] 77[306,309] 78[310,313] 79[314,317] 80[318,321] 87[322,322] 89[323,323] 91[324,324] 93[325,325] 94[326,326] 95[327,327] 97[328,328] 103[329,329] 104[330,330] 105[331,331] 106[332,332] 107[333,333] 108[334,334] 109[335,335] 110[336,336] ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d6(0){ }d13(1){ }d18(2){ }d27(4){ }d36(5){ }d37(6){ }d38(7){ }d71(16){ }d87(20){ }d92(21){ }d97(22){ }d102(23){ }d107(24){ }d112(25){ }d117(26){ }d122(27){ }d127(28){ }d164(37){ }d169(38){ }} ;; bb 0 artificial_uses: { } ;; lr in ;; lr use ;; lr def 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] ;; live in ;; live gen 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] ;; live kill ;; rd in (0) ;; rd gen (19) 0[6],1[13],2[18],4[27],5[36],6[37],7[38],16[71],20[87],21[92],22[97],23[102],24[107],25[112],26[117],27[122],28[127],37[164],38[169] ;; rd kill (91) 0[0,1,2,3,4,5,6],1[7,8,9,10,11,12,13],2[14,15,16,17,18],4[19,20,21,22,23,24,25,26,27],5[28,29,30,31,32,33,34,35,36],6[37],7[38],16[71],20[87],21[88,89,90,91,92],22[93,94,95,96,97],23[98,99,100,101,102],24[103,104,105,106,107],25[108,109,110,111,112],26[113,114,115,116,117],27[118,119,120,121,122],28[123,124,125,126,127],37[160,161,162,163,164],38[165,166,167,168,169] ;; UD chains for artificial uses at top ;; lr out 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; live out 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; rd out (5) 5[36],6[37],7[38],16[71],20[87] ;; UD chains for artificial uses at bottom ( 0 )->[2]->( 3 4 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u0(6){ d37(bb 0 insn -1) }u1(7){ d38(bb 0 insn -1) }u2(16){ d71(bb 0 insn -1) }u3(20){ d87(bb 0 insn -1) }} ;; lr in 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; lr use 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; lr def 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] 87 89 91 93 94 95 97 103 104 105 106 107 108 109 ;; live in 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; live gen 0 [ax] 1 [dx] 4 [si] 5 [di] 17 [flags] 87 89 91 93 94 95 97 103 104 105 106 107 108 109 ;; live kill 17 [flags] ;; rd in (5) 5[36],6[37],7[38],16[71],20[87] ;; rd gen (16) 0[3],17[75],87[322],89[323],91[324],93[325],94[326],95[327],97[328],103[329],104[330],105[331],106[332],107[333],108[334],109[335] ;; rd kill (28) 0[0,1,2,3,4,5,6],17[72,73,74,75,76,77,78],87[322],89[323],91[324],93[325],94[326],95[327],97[328],103[329],104[330],105[331],106[332],107[333],108[334],109[335] ;; UD chains for artificial uses at top ;; lr out 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; live out 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; rd out (6) 6[37],7[38],16[71],20[87],97[328],103[329] ;; UD chains for artificial uses at bottom ;; reg 6 { d37(bb 0 insn -1) } ;; reg 7 { d38(bb 0 insn -1) } ;; reg 16 { d71(bb 0 insn -1) } ;; reg 20 { d87(bb 0 insn -1) } ( 2 )->[3]->( 4 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u37(6){ d37(bb 0 insn -1) }u38(7){ d38(bb 0 insn -1) }u39(16){ d71(bb 0 insn -1) }u40(20){ d87(bb 0 insn -1) }} ;; lr in 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; lr use 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; lr def 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; live in 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; live gen 4 [si] 5 [di] ;; live kill ;; rd in (6) 6[37],7[38],16[71],20[87],97[328],103[329] ;; rd gen (0) ;; rd kill (0) ;; UD chains for artificial uses at top ;; lr out 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; live out 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; rd out (6) 6[37],7[38],16[71],20[87],97[328],103[329] ;; UD chains for artificial uses at bottom ;; reg 6 { d37(bb 0 insn -1) } ;; reg 7 { d38(bb 0 insn -1) } ;; reg 16 { d71(bb 0 insn -1) } ;; reg 20 { d87(bb 0 insn -1) } ( 2 3 )->[4]->( 1 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u46(6){ d37(bb 0 insn -1) }u47(7){ d38(bb 0 insn -1) }u48(16){ d71(bb 0 insn -1) }u49(20){ d87(bb 0 insn -1) }} ;; lr in 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; lr use 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; lr def 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] 110 ;; live in 6 [bp] 7 [sp] 16 [argp] 20 [frame] 97 103 ;; live gen 0 [ax] 4 [si] 5 [di] 110 ;; live kill 17 [flags] ;; rd in (6) 6[37],7[38],16[71],20[87],97[328],103[329] ;; rd gen (2) 0[0],110[336] ;; rd kill (8) 0[0,1,2,3,4,5,6],110[336] ;; UD chains for artificial uses at top ;; lr out 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; live out 0 [ax] 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; rd out (5) 0[0],6[37],7[38],16[71],20[87] ;; UD chains for artificial uses at bottom ;; reg 6 { d37(bb 0 insn -1) } ;; reg 7 { d38(bb 0 insn -1) } ;; reg 16 { d71(bb 0 insn -1) } ;; reg 20 { d87(bb 0 insn -1) } ( 4 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u57(0){ d0(bb 4 insn 50) }u58(6){ d37(bb 0 insn -1) }u59(7){ d38(bb 0 insn -1) }u60(20){ d87(bb 0 insn -1) }} ;; lr in 0 [ax] 6 [bp] 7 [sp] 20 [frame] ;; lr use 0 [ax] 6 [bp] 7 [sp] 20 [frame] ;; lr def ;; live in 0 [ax] 6 [bp] 7 [sp] 20 [frame] ;; live gen ;; live kill ;; rd in (5) 0[0],6[37],7[38],16[71],20[87] ;; rd gen (0) ;; rd kill (0) ;; UD chains for artificial uses at top ;; lr out ;; live out ;; rd out (0) ;; UD chains for artificial uses at bottom ;; reg 0 { d0(bb 4 insn 50) } ;; reg 6 { d37(bb 0 insn -1) } ;; reg 7 { d38(bb 0 insn -1) } ;; reg 20 { d87(bb 0 insn -1) } Finding needed instructions: Adding insn 34 to worklist Adding insn 31 to worklist Adding insn 27 to worklist Adding insn 22 to worklist Adding insn 20 to worklist Adding insn 19 to worklist Adding insn 13 to worklist Adding insn 39 to worklist Adding insn 51 to worklist Adding insn 45 to worklist Finished finding needed instructions: Adding insn 50 to worklist Processing use of (reg 7 sp) in insn 45: Processing use of (reg 4 si) in insn 45: Adding insn 43 to worklist Processing use of (reg 5 di) in insn 45: Adding insn 44 to worklist Processing use of (reg 103 [ L ]) in insn 44: Adding insn 2 to worklist Processing use of (reg 5 di) in insn 2: Processing use of (reg 110 [ D.452 ]) in insn 43: Adding insn 42 to worklist Processing use of (reg 97 [ base ]) in insn 42: Adding insn 29 to worklist Processing use of (reg 107 [ L_3(D)->ci ]) in insn 29: Adding insn 28 to worklist Processing use of (reg 103 [ L ]) in insn 28: Processing use of (reg 0 ax) in insn 51: Processing use of (reg 7 sp) in insn 39: Processing use of (reg 4 si) in insn 39: Adding insn 37 to worklist Processing use of (reg 5 di) in insn 39: Adding insn 38 to worklist Processing use of (reg 103 [ L ]) in insn 38: Processing use of (reg 97 [ base ]) in insn 37: Processing use of (reg 7 sp) in insn 13: Processing use of (reg 1 dx) in insn 13: Adding insn 10 to worklist Processing use of (reg 4 si) in insn 13: Adding insn 11 to worklist Processing use of (reg 5 di) in insn 13: Adding insn 12 to worklist Processing use of (reg 87 [ D.451 ]) in insn 12: Adding insn 7 to worklist Processing use of (reg 103 [ L ]) in insn 7: Processing use of (reg 91 [ base ]) in insn 19: Adding insn 15 to worklist Processing use of (reg 94 [ D.454 ]) in insn 19: Adding insn 18 to worklist Processing use of (reg 93 [ D.452 ]) in insn 18: Adding insn 17 to worklist Processing use of (reg 106 [ cl_6->p ]) in insn 17: Adding insn 16 to worklist Processing use of (reg 89 [ cl ]) in insn 16: Adding insn 9 to worklist Processing use of (reg 104 [ _4->func ]) in insn 9: Adding insn 8 to worklist Processing use of (reg 87 [ D.451 ]) in insn 8: Processing use of (reg 105 [ L_3(D)->ci ]) in insn 15: Adding insn 14 to worklist Processing use of (reg 103 [ L ]) in insn 14: Processing use of (reg 91 [ base ]) in insn 20: Processing use of (reg 91 [ base ]) in insn 22: Processing use of (reg 95 [ D.454 ]) in insn 22: Adding insn 21 to worklist Processing use of (reg 93 [ D.452 ]) in insn 21: Processing use of (reg 7 sp) in insn 27: Processing use of (reg 0 ax) in insn 27: Adding insn 26 to worklist Processing use of (reg 1 dx) in insn 27: Adding insn 23 to worklist Processing use of (reg 4 si) in insn 27: Adding insn 24 to worklist Processing use of (reg 5 di) in insn 27: Adding insn 25 to worklist Processing use of (reg 103 [ L ]) in insn 31: Processing use of (reg 108) in insn 31: Adding insn 30 to worklist Processing use of (reg 97 [ base ]) in insn 30: Processing use of (reg 17 flags) in insn 34: Adding insn 33 to worklist Processing use of (reg 109 [ cl_6->p ]) in insn 33: Adding insn 32 to worklist Processing use of (reg 89 [ cl ]) in insn 32: starting the processing of deferred insns ending the processing of deferred insns ravif2 Dataflow summary: ;; invalidated by call 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; hardware regs used 7 [sp] 16 [argp] 20 [frame] ;; regular block artificial uses 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; eh block artificial uses 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; entry block defs 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] ;; exit block uses 0 [ax] 6 [bp] 7 [sp] 20 [frame] ;; regs ever live 0 [ax] 1 [dx] 4 [si] 5 [di] 7 [sp] 17 [flags] ;; ref usage r0={7d,3u} r1={7d,2u} r2={5d} r4={9d,4u} r5={9d,5u} r6={1d,4u} r7={1d,8u} r8={4d} r9={4d} r10={4d} r11={4d} r12={4d} r13={4d} r14={4d} r15={4d} r16={1d,3u} r17={7d,1u} r18={4d} r19={4d} r20={1d,4u} r21={5d} r22={5d} r23={5d} r24={5d} r25={5d} r26={5d} r27={5d} r28={5d} r29={4d} r30={4d} r31={4d} r32={4d} r33={4d} r34={4d} r35={4d} r36={4d} r37={5d} r38={5d} r39={4d} r40={4d} r45={4d} r46={4d} r47={4d} r48={4d} r49={4d} r50={4d} r51={4d} r52={4d} r53={4d} r54={4d} r55={4d} r56={4d} r57={4d} r58={4d} r59={4d} r60={4d} r61={4d} r62={4d} r63={4d} r64={4d} r65={4d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={4d} r79={4d} r80={4d} r87={1d,2u} r89={1d,2u} r91={1d,3u} r93={1d,2u} r94={1d,1u} r95={1d,1u} r97={1d,3u} r103={1d,6u} r104={1d,1u} r105={1d,1u} r106={1d,1u} r107={1d,1u} r108={1d,1u} r109={1d,1u} r110={1d,1u} ;; total ref usage 398{337d,61u,0e} in 38{34 regular + 4 call} insns. (note 4 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (insn 2 4 3 2 (set (reg/v/f:DI 103 [ L ]) (reg:DI 5 di [ L ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 5 di [ L ]) (nil))) (note 3 2 5 2 NOTE_INSN_FUNCTION_BEG) (note 5 3 7 2 ("entry") NOTE_INSN_DELETED_LABEL 2) (insn 7 5 8 2 (set (reg/f:DI 87 [ D.451 ]) (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 8 7 9 2 (set (reg/f:DI 104 [ _4->func ]) (mem/f:DI (reg/f:DI 87 [ D.451 ]) [11 _4->func+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 9 8 10 2 (set (reg/v/f:DI 89 [ cl ]) (mem/f:DI (reg/f:DI 104 [ _4->func ]) [3 _5->value_.gc+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 104 [ _4->func ]) (nil))) (insn 10 9 11 2 (set (reg:SI 1 dx) (const_int 0 [0])) 86 {*movsi_internal} (nil)) (insn 11 10 12 2 (set (reg:SI 4 si) (const_int 0 [0])) 86 {*movsi_internal} (nil)) (insn 12 11 13 2 (set (reg:DI 5 di) (reg/f:DI 87 [ D.451 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 87 [ D.451 ]) (nil))) (call_insn 13 12 14 2 (call (mem:QI (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) [0 raviV_op_loadnil S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:SI 4 si) (expr_list:REG_DEAD (reg:SI 1 dx) (expr_list:REG_CALL_DECL (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil))))) (insn 14 13 15 2 (set (reg/f:DI 105 [ L_3(D)->ci ]) (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 15 14 16 2 (set (reg/v/f:DI 91 [ base ]) (mem/f:DI (plus:DI (reg/f:DI 105 [ L_3(D)->ci ]) (const_int 32 [0x20])) [11 _8->u.l.base+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 105 [ L_3(D)->ci ]) (nil))) (insn 16 15 17 2 (set (reg/f:DI 106 [ cl_6->p ]) (mem/f:DI (plus:DI (reg/v/f:DI 89 [ cl ]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 17 16 18 2 (set (reg/f:DI 93 [ D.452 ]) (mem/f:DI (plus:DI (reg/f:DI 106 [ cl_6->p ]) (const_int 48 [0x30])) [11 _10->k+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 106 [ cl_6->p ]) (nil))) (insn 18 17 19 2 (set (reg:DI 94 [ D.454 ]) (mem:DI (reg/f:DI 93 [ D.452 ]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 19 18 20 2 (set (mem:DI (plus:DI (reg/v/f:DI 91 [ base ]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 94 [ D.454 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 94 [ D.454 ]) (nil))) (insn 20 19 21 2 (set (mem:SI (plus:DI (reg/v/f:DI 91 [ base ]) (const_int 24 [0x18])) [5 MEM[(struct ravi_TValue *)base_9 + 16B].tt_+0 S4 A64]) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 21 20 22 2 (set (reg:DI 95 [ D.454 ]) (mem:DI (reg/f:DI 93 [ D.452 ]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 93 [ D.452 ]) (nil))) (insn 22 21 23 2 (set (mem:DI (plus:DI (reg/v/f:DI 91 [ base ]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 95 [ D.454 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 95 [ D.454 ]) (expr_list:REG_DEAD (reg/v/f:DI 91 [ base ]) (nil)))) (insn 23 22 24 2 (set (reg:SI 1 dx) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 24 23 25 2 (set (reg:SI 4 si) (const_int 13 [0xd])) 86 {*movsi_internal} (nil)) (insn 25 24 26 2 (set (reg:DI 5 di) (symbol_ref/f:DI ("*.LC0") [flags 0x2] )) 85 {*movdi_internal} (nil)) (insn 26 25 27 2 (set (reg:QI 0 ax) (const_int 0 [0])) 89 {*movqi_internal} (nil)) (call_insn 27 26 28 2 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("printf") [flags 0x41] ) [0 printf S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:SI 4 si) (expr_list:REG_DEAD (reg:SI 1 dx) (expr_list:REG_UNUSED (reg:SI 0 ax) (expr_list:REG_CALL_DECL (symbol_ref:DI ("printf") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))))))) (expr_list (use (reg:QI 0 ax)) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil)))))) (insn 28 27 29 2 (set (reg/f:DI 107 [ L_3(D)->ci ]) (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 29 28 30 2 (set (reg/v/f:DI 97 [ base ]) (mem/f:DI (plus:DI (reg/f:DI 107 [ L_3(D)->ci ]) (const_int 32 [0x20])) [11 _19->u.l.base+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 107 [ L_3(D)->ci ]) (nil))) (insn 30 29 31 2 (parallel [ (set (reg/f:DI 108) (plus:DI (reg/v/f:DI 97 [ base ]) (const_int 32 [0x20]))) (clobber (reg:CC 17 flags)) ]) 215 {*adddi_1} (expr_list:REG_UNUSED (reg:CC 17 flags) (nil))) (insn 31 30 32 2 (set (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 16 [0x10])) [11 L_3(D)->top+0 S8 A64]) (reg/f:DI 108)) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 108) (nil))) (insn 32 31 33 2 (set (reg/f:DI 109 [ cl_6->p ]) (mem/f:DI (plus:DI (reg/v/f:DI 89 [ cl ]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/v/f:DI 89 [ cl ]) (nil))) (insn 33 32 34 2 (set (reg:CCNO 17 flags) (compare:CCNO (mem:SI (plus:DI (reg/f:DI 109 [ cl_6->p ]) (const_int 32 [0x20])) [5 _23->sizep+0 S4 A64]) (const_int 0 [0]))) 3 {*cmpsi_ccno_1} (expr_list:REG_DEAD (reg/f:DI 109 [ cl_6->p ]) (nil))) (jump_insn 34 33 36 2 (set (pc) (if_then_else (le (reg:CCNO 17 flags) (const_int 0 [0])) (label_ref 40) (pc))) 601 {*jcc_1} (expr_list:REG_DEAD (reg:CCNO 17 flags) (int_list:REG_BR_PROB 3666 (nil))) -> 40) (note 36 34 35 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (note 35 36 37 3 ("OP_RETURN_if_sizep_gt_0_12_23") NOTE_INSN_DELETED_LABEL 4) (insn 37 35 38 3 (set (reg:DI 4 si) (reg/v/f:DI 97 [ base ])) 85 {*movdi_internal} (nil)) (insn 38 37 39 3 (set (reg:DI 5 di) (reg/v/f:DI 103 [ L ])) 85 {*movdi_internal} (nil)) (call_insn 39 38 40 3 (call (mem:QI (symbol_ref:DI ("luaF_close") [flags 0x41] ) [0 luaF_close S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:DI 4 si) (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaF_close") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (code_label 40 39 41 4 3 ("OP_RETURN_else_sizep_gt_0_12_24") [1 uses]) (note 41 40 42 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 42 41 43 4 (parallel [ (set (reg/f:DI 110 [ D.452 ]) (plus:DI (reg/v/f:DI 97 [ base ]) (const_int 16 [0x10]))) (clobber (reg:CC 17 flags)) ]) 215 {*adddi_1} (expr_list:REG_DEAD (reg/v/f:DI 97 [ base ]) (expr_list:REG_UNUSED (reg:CC 17 flags) (nil)))) (insn 43 42 44 4 (set (reg:DI 4 si) (reg/f:DI 110 [ D.452 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 110 [ D.452 ]) (nil))) (insn 44 43 45 4 (set (reg:DI 5 di) (reg/v/f:DI 103 [ L ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/v/f:DI 103 [ L ]) (nil))) (call_insn 45 44 50 4 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) [0 luaD_poscall S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:DI 4 si) (expr_list:REG_UNUSED (reg:SI 0 ax) (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (insn 50 45 51 4 (set (reg/i:SI 0 ax) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 51 50 0 4 (use (reg/i:SI 0 ax)) -1 (nil)) ; end of dump from pass_ud_rtl_dce (../../src/gcc/dce.c:805)