; start of dump from pass_ira (../../src/gcc/ira.c:5512) ;; Function ravif2 (ravif2, funcdef_no=0, decl_uid=364, cgraph_uid=0, symbol_order=0) Starting decreasing number of live ranges... starting the processing of deferred insns ending the processing of deferred insns df_analyze called starting the processing of deferred insns ending the processing of deferred insns df_analyze called Ignoring reg 104, has equiv memory Ignoring reg 105, has equiv memory Ignoring reg 106, has equiv memory Ignoring reg 94, has equiv memory Ignoring reg 95, has equiv memory Ignoring reg 107, has equiv memory Reg 97 uninteresting (no unique first use) Reg 109 uninteresting ;; 1 loops found ;; ;; Loop 0 ;; header 0, latch 1 ;; depth 0, outer -1 ;; nodes: 0 1 2 3 4 ;; 2 succs { 3 4 } ;; 3 succs { 4 } ;; 4 succs { 1 } Building IRA IR starting the processing of deferred insns ending the processing of deferred insns df_analyze called init_insns for 87: (insn_list:REG_DEP_TRUE 7 (nil)) init_insns for 94: (insn_list:REG_DEP_TRUE 18 (nil)) init_insns for 95: (insn_list:REG_DEP_TRUE 22 (nil)) init_insns for 104: (insn_list:REG_DEP_TRUE 8 (nil)) init_insns for 105: (insn_list:REG_DEP_TRUE 14 (nil)) init_insns for 106: (insn_list:REG_DEP_TRUE 16 (nil)) init_insns for 107: (insn_list:REG_DEP_TRUE 28 (nil)) init_insns for 108: (insn_list:REG_DEP_TRUE 31 (nil)) Pass 0 for finding pseudo/allocno costs a1 (r110,l0) best SIREG, allocno SIREG a3 (r109,l0) best GENERAL_REGS, allocno GENERAL_REGS a5 (r108,l0) best GENERAL_REGS, allocno GENERAL_REGS a6 (r107,l0) best GENERAL_REGS, allocno GENERAL_REGS a11 (r106,l0) best GENERAL_REGS, allocno GENERAL_REGS a12 (r105,l0) best GENERAL_REGS, allocno GENERAL_REGS a14 (r104,l0) best GENERAL_REGS, allocno GENERAL_REGS a0 (r103,l0) best DIREG, allocno DIREG a2 (r97,l0) best GENERAL_REGS, allocno GENERAL_REGS a8 (r95,l0) best GENERAL_REGS, allocno GENERAL_REGS a10 (r94,l0) best GENERAL_REGS, allocno GENERAL_REGS a9 (r93,l0) best GENERAL_REGS, allocno GENERAL_REGS a7 (r91,l0) best GENERAL_REGS, allocno GENERAL_REGS a4 (r89,l0) best GENERAL_REGS, allocno GENERAL_REGS a13 (r87,l0) best DIREG, allocno DIREG a0(r103,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:-2000,-2000 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:73064,73064 NO_REX_SSE_REGS:73064,73064 SSE_REGS:73064,73064 MMX_REGS:81697,81697 INT_SSE_REGS:81697,81697 ALL_REGS:1895664,1895664 MEM:33899,33899 a1(r110,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:-1000,-1000 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:416000,416000 MEM:6000,6000 a2(r97,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:29064,29064 NO_REX_SSE_REGS:29064,29064 SSE_REGS:29064,29064 MMX_REGS:31697,31697 INT_SSE_REGS:31697,31697 ALL_REGS:651664,651664 MEM:12899,12899 a3(r109,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:16000,16000 NO_REX_SSE_REGS:16000,16000 SSE_REGS:16000,16000 MMX_REGS:17000,17000 INT_SSE_REGS:17000,17000 ALL_REGS:312000,312000 MEM:8000,8000 a4(r89,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:32000,32000 NO_REX_SSE_REGS:32000,32000 SSE_REGS:32000,32000 MMX_REGS:35000,35000 INT_SSE_REGS:35000,35000 ALL_REGS:728000,728000 MEM:16000,16000 a5(r108,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:416000,416000 MEM:8000,8000 a6(r107,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:16000,16000 NO_REX_SSE_REGS:16000,16000 SSE_REGS:16000,16000 MMX_REGS:17000,17000 INT_SSE_REGS:17000,17000 ALL_REGS:312000,312000 MEM:0,0 a7(r91,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:32000,32000 NO_REX_SSE_REGS:32000,32000 SSE_REGS:32000,32000 MMX_REGS:35000,35000 INT_SSE_REGS:35000,35000 ALL_REGS:728000,728000 MEM:16000,16000 a8(r95,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:16000,16000 NO_REX_SSE_REGS:16000,16000 SSE_REGS:16000,16000 MMX_REGS:17000,17000 INT_SSE_REGS:17000,17000 ALL_REGS:312000,312000 MEM:0,0 a9(r93,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:40000,40000 NO_REX_SSE_REGS:40000,40000 SSE_REGS:40000,40000 MMX_REGS:44000,44000 INT_SSE_REGS:44000,44000 ALL_REGS:936000,936000 MEM:20000,20000 a10(r94,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:16000,16000 NO_REX_SSE_REGS:16000,16000 SSE_REGS:16000,16000 MMX_REGS:17000,17000 INT_SSE_REGS:17000,17000 ALL_REGS:312000,312000 MEM:0,0 a11(r106,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:16000,16000 NO_REX_SSE_REGS:16000,16000 SSE_REGS:16000,16000 MMX_REGS:17000,17000 INT_SSE_REGS:17000,17000 ALL_REGS:312000,312000 MEM:0,0 a12(r105,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:16000,16000 NO_REX_SSE_REGS:16000,16000 SSE_REGS:16000,16000 MMX_REGS:17000,17000 INT_SSE_REGS:17000,17000 ALL_REGS:312000,312000 MEM:0,0 a13(r87,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:-1000,-1000 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:32000,32000 NO_REX_SSE_REGS:32000,32000 SSE_REGS:32000,32000 MMX_REGS:35000,35000 INT_SSE_REGS:35000,35000 ALL_REGS:728000,728000 MEM:7000,7000 a14(r104,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:16000,16000 NO_REX_SSE_REGS:16000,16000 SSE_REGS:16000,16000 MMX_REGS:17000,17000 INT_SSE_REGS:17000,17000 ALL_REGS:312000,312000 MEM:0,0 Pass 1 for finding pseudo/allocno costs r110: preferred SIREG, alternative GENERAL_REGS, allocno GENERAL_REGS r109: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r108: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r107: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r106: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r105: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r104: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r103: preferred DIREG, alternative GENERAL_REGS, allocno GENERAL_REGS r97: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r95: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r94: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r93: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r91: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r89: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS r87: preferred DIREG, alternative GENERAL_REGS, allocno GENERAL_REGS a0(r103,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,-2000 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:77064,77064 NO_REX_SSE_REGS:77064,77064 SSE_REGS:77064,77064 MMX_REGS:85697,85697 INT_SSE_REGS:85697,85697 ALL_REGS:1899664,1899664 MEM:36899,36899 a1(r110,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,-1000 DIREG:0,0 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:416000,416000 MEM:6000,6000 a2(r97,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:30064,30064 NO_REX_SSE_REGS:30064,30064 SSE_REGS:30064,30064 MMX_REGS:32697,32697 INT_SSE_REGS:32697,32697 ALL_REGS:655664,655664 MEM:12899,12899 a3(r109,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:316000,316000 MEM:8000,8000 a4(r89,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:33000,33000 NO_REX_SSE_REGS:33000,33000 SSE_REGS:33000,33000 MMX_REGS:36000,36000 INT_SSE_REGS:36000,36000 ALL_REGS:732000,732000 MEM:16000,16000 a5(r108,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:416000,416000 MEM:8000,8000 a6(r107,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:316000,316000 MEM:0,0 a7(r91,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:33000,33000 NO_REX_SSE_REGS:33000,33000 SSE_REGS:33000,33000 MMX_REGS:36000,36000 INT_SSE_REGS:36000,36000 ALL_REGS:732000,732000 MEM:16000,16000 a8(r95,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:316000,316000 MEM:0,0 a9(r93,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:41000,41000 NO_REX_SSE_REGS:41000,41000 SSE_REGS:41000,41000 MMX_REGS:45000,45000 INT_SSE_REGS:45000,45000 ALL_REGS:940000,940000 MEM:20000,20000 a10(r94,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:316000,316000 MEM:0,0 a11(r106,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:316000,316000 MEM:0,0 a12(r105,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:316000,316000 MEM:0,0 a13(r87,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,-1000 AD_REGS:0,0 CLOBBERED_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:33000,33000 NO_REX_SSE_REGS:33000,33000 SSE_REGS:33000,33000 MMX_REGS:36000,36000 INT_SSE_REGS:36000,36000 ALL_REGS:732000,732000 MEM:7000,7000 a14(r104,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:17000,17000 NO_REX_SSE_REGS:17000,17000 SSE_REGS:17000,17000 MMX_REGS:18000,18000 INT_SSE_REGS:18000,18000 ALL_REGS:316000,316000 MEM:0,0 Insn 51(l0): point = 0 Insn 50(l0): point = 2 Insn 45(l0): point = 4 Insn 44(l0): point = 6 Insn 43(l0): point = 8 Insn 42(l0): point = 10 Insn 39(l0): point = 13 Insn 38(l0): point = 15 Insn 37(l0): point = 17 Insn 34(l0): point = 20 Insn 33(l0): point = 22 Insn 32(l0): point = 24 Insn 31(l0): point = 26 Insn 30(l0): point = 28 Insn 29(l0): point = 30 Insn 28(l0): point = 32 Insn 27(l0): point = 34 Insn 26(l0): point = 36 Insn 25(l0): point = 38 Insn 24(l0): point = 40 Insn 23(l0): point = 42 Insn 22(l0): point = 44 Insn 21(l0): point = 46 Insn 20(l0): point = 48 Insn 19(l0): point = 50 Insn 18(l0): point = 52 Insn 17(l0): point = 54 Insn 16(l0): point = 56 Insn 15(l0): point = 58 Insn 14(l0): point = 60 Insn 13(l0): point = 62 Insn 12(l0): point = 64 Insn 11(l0): point = 66 Insn 10(l0): point = 68 Insn 9(l0): point = 70 Insn 8(l0): point = 72 Insn 7(l0): point = 74 Insn 2(l0): point = 76 a0(r103): [7..76] a1(r110): [9..10] a2(r97): [11..30] a3(r109): [23..24] a4(r89): [25..70] a5(r108): [27..28] a6(r107): [31..32] a7(r91): [45..58] a8(r95): [45..46] a9(r93): [47..54] a10(r94): [51..52] a11(r106): [55..56] a12(r105): [59..60] a13(r87): [65..74] a14(r104): [71..72] Compressing live ranges: from 79 to 20 - 25% Ranges after the compression: a0(r103): [0..19] a1(r110): [0..1] a2(r97): [2..5] a3(r109): [2..3] a4(r89): [4..17] a5(r108): [4..5] a6(r107): [6..7] a7(r91): [8..13] a8(r95): [8..9] a9(r93): [10..11] a10(r94): [10..11] a11(r106): [12..13] a12(r105): [14..15] a13(r87): [16..19] a14(r104): [18..19] +++Allocating 120 bytes for conflict table (uncompressed size 120) ;; a0(r103,l0) conflicts: a1(r110,l0) a3(r109,l0) a2(r97,l0) a5(r108,l0) a4(r89,l0) a6(r107,l0) a8(r95,l0) a7(r91,l0) a9(r93,l0) a10(r94,l0) a11(r106,l0) a12(r105,l0) a13(r87,l0) a14(r104,l0) ;; total conflict hard regs: 0 1 4 5 ;; conflict hard regs: 0 1 4 5 ;; a1(r110,l0) conflicts: a0(r103,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a2(r97,l0) conflicts: a0(r103,l0) a3(r109,l0) a5(r108,l0) a4(r89,l0) ;; total conflict hard regs: 4 5 ;; conflict hard regs: 4 5 ;; a3(r109,l0) conflicts: a0(r103,l0) a2(r97,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a4(r89,l0) conflicts: a0(r103,l0) a2(r97,l0) a5(r108,l0) a6(r107,l0) a8(r95,l0) a7(r91,l0) a9(r93,l0) a10(r94,l0) a11(r106,l0) a12(r105,l0) a13(r87,l0) ;; total conflict hard regs: 0 1 4 5 ;; conflict hard regs: 0 1 4 5 ;; a5(r108,l0) conflicts: a0(r103,l0) a2(r97,l0) a4(r89,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a6(r107,l0) conflicts: a0(r103,l0) a4(r89,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a7(r91,l0) conflicts: a0(r103,l0) a4(r89,l0) a8(r95,l0) a9(r93,l0) a10(r94,l0) a11(r106,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a8(r95,l0) conflicts: a0(r103,l0) a4(r89,l0) a7(r91,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a9(r93,l0) conflicts: a0(r103,l0) a4(r89,l0) a7(r91,l0) a10(r94,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a10(r94,l0) conflicts: a0(r103,l0) a4(r89,l0) a7(r91,l0) a9(r93,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a11(r106,l0) conflicts: a0(r103,l0) a4(r89,l0) a7(r91,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a12(r105,l0) conflicts: a0(r103,l0) a4(r89,l0) ;; total conflict hard regs: ;; conflict hard regs: ;; a13(r87,l0) conflicts: a0(r103,l0) a4(r89,l0) a14(r104,l0) ;; total conflict hard regs: 1 4 ;; conflict hard regs: 1 4 ;; a14(r104,l0) conflicts: a0(r103,l0) a13(r87,l0) ;; total conflict hard regs: ;; conflict hard regs: cp0:a1(r110)<->a2(r97)@125:shuffle pref0:a1(r110)<-hr4@1500 pref1:a0(r103)<-hr5@3633 pref2:a13(r87)<-hr5@1500 pref3:a2(r97)<-hr4@633 regions=1, blocks=5, points=20 allocnos=15 (big 0), copies=1, conflicts=0, ranges=15 **** Allocnos coloring: Loop 0 (parent -1, header bb2, depth 0) bbs: 4 3 2 all: 0r103 1r110 2r97 3r109 4r89 5r108 6r107 7r91 8r95 9r93 10r94 11r106 12r105 13r87 14r104 modified regnos: 87 89 91 93 94 95 97 103 104 105 106 107 108 109 110 border: Pressure: GENERAL_REGS=6 Removing pref1:hr5@3633 Removing pref3:hr4@633 Hard reg set forest: 0:( 0-6 8-15 21-52)@0 1:( 0-6 37-44)@122000 2:( 0-3 6 37-44)@25798 3:( 2 3 6 37-44)@105798 Allocno a0r103 of GENERAL_REGS(15) has 11 avail. regs 2 3 6 37-44, node: 2 3 6 37-44 (confl regs = 0 1 4 5 7-36 45-79) Allocno a1r110 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a2r97 of GENERAL_REGS(15) has 13 avail. regs 0-3 6 37-44, node: 0-3 6 37-44 (confl regs = 4 5 7-36 45-79) Allocno a3r109 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a4r89 of GENERAL_REGS(15) has 11 avail. regs 2 3 6 37-44, node: 2 3 6 37-44 (confl regs = 0 1 4 5 7-36 45-79) Allocno a5r108 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a6r107 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a7r91 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a8r95 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a9r93 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a10r94 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a11r106 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a12r105 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Allocno a13r87 of GENERAL_REGS(15) has 13 avail. regs 0 2 3 5 6 37-44, ^node: 0-6 37-44 (confl regs = 1 4 7-36 45-79) Allocno a14r104 of GENERAL_REGS(15) has 15 avail. regs 0-6 37-44, node: 0-6 37-44 (confl regs = 7-36 45-79) Forming thread by copy 0:a1r110-a2r97 (freq=125): Result (freq=5633): a1r110(2000) a2r97(3633) Pushing a14(r104,l0)(cost 0) Pushing a12(r105,l0)(cost 0) Making a4(r89,l0) colorable Pushing a11(r106,l0)(cost 0) Pushing a10(r94,l0)(cost 0) Making a0(r103,l0) colorable Pushing a8(r95,l0)(cost 0) Pushing a6(r107,l0)(cost 0) Pushing a5(r108,l0)(cost 0) Pushing a3(r109,l0)(cost 0) Pushing a13(r87,l0)(cost 0) Pushing a9(r93,l0)(cost 0) Pushing a4(r89,l0)(cost 16000) Pushing a7(r91,l0)(cost 0) Pushing a1(r110,l0)(cost 0) Pushing a2(r97,l0)(cost 0) Pushing a0(r103,l0)(cost 36899) Popping a0(r103,l0) -- assign reg 3 Popping a2(r97,l0) -- assign reg 6 Popping a1(r110,l0) -- assign reg 4 Popping a7(r91,l0) -- assign reg 0 Popping a4(r89,l0) -- assign reg 41 Popping a9(r93,l0) -- assign reg 1 Popping a13(r87,l0) -- assign reg 5 Popping a3(r109,l0) -- assign reg 0 Popping a5(r108,l0) -- assign reg 0 Popping a6(r107,l0) -- assign reg 0 Popping a8(r95,l0) -- assign reg 1 Popping a10(r94,l0) -- assign reg 2 Popping a11(r106,l0) -- assign reg 1 Popping a12(r105,l0) -- assign reg 0 Popping a14(r104,l0) -- assign reg 0 Disposition: 13:r87 l0 5 4:r89 l0 41 7:r91 l0 0 9:r93 l0 1 10:r94 l0 2 8:r95 l0 1 2:r97 l0 6 0:r103 l0 3 14:r104 l0 0 12:r105 l0 0 11:r106 l0 1 6:r107 l0 0 5:r108 l0 0 3:r109 l0 0 1:r110 l0 4 New iteration of spill/restore move +++Costs: overall -6000, reg -6000, mem 0, ld 0, st 0, move 0 +++ move loops 0, new jumps 0 ravif2 Dataflow summary: ;; invalidated by call 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; hardware regs used 7 [sp] 16 [argp] 20 [frame] ;; regular block artificial uses 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; eh block artificial uses 6 [bp] 7 [sp] 16 [argp] 20 [frame] ;; entry block defs 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] ;; exit block uses 0 [ax] 6 [bp] 7 [sp] 20 [frame] ;; regs ever live 0 [ax] 1 [dx] 4 [si] 5 [di] 7 [sp] 17 [flags] ;; ref usage r0={7d,3u} r1={7d,2u} r2={5d} r4={9d,4u} r5={9d,5u} r6={1d,4u} r7={1d,8u} r8={4d} r9={4d} r10={4d} r11={4d} r12={4d} r13={4d} r14={4d} r15={4d} r16={1d,3u} r17={7d,1u} r18={4d} r19={4d} r20={1d,4u} r21={5d} r22={5d} r23={5d} r24={5d} r25={5d} r26={5d} r27={5d} r28={5d} r29={4d} r30={4d} r31={4d} r32={4d} r33={4d} r34={4d} r35={4d} r36={4d} r37={5d} r38={5d} r39={4d} r40={4d} r45={4d} r46={4d} r47={4d} r48={4d} r49={4d} r50={4d} r51={4d} r52={4d} r53={4d} r54={4d} r55={4d} r56={4d} r57={4d} r58={4d} r59={4d} r60={4d} r61={4d} r62={4d} r63={4d} r64={4d} r65={4d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={4d} r79={4d} r80={4d} r87={1d,2u,1e} r89={1d,2u,1e} r91={1d,3u,1e} r93={1d,2u,1e} r94={1d,1u} r95={1d,1u} r97={1d,3u} r103={1d,6u,4e} r104={1d,1u} r105={1d,1u} r106={1d,1u} r107={1d,1u} r108={1d,1u} r109={1d,1u} r110={1d,1u} ;; total ref usage 406{337d,61u,8e} in 38{34 regular + 4 call} insns. (note 1 0 4 NOTE_INSN_DELETED) (note 4 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (insn 2 4 3 2 (set (reg/v/f:DI 103 [ L ]) (reg:DI 5 di [ L ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 5 di [ L ]) (nil))) (note 3 2 5 2 NOTE_INSN_FUNCTION_BEG) (note 5 3 7 2 ("entry") NOTE_INSN_DELETED_LABEL 2) (insn 7 5 8 2 (set (reg/f:DI 87 [ D.451 ]) (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn 8 7 9 2 (set (reg/f:DI 104 [ _4->func ]) (mem/f:DI (reg/f:DI 87 [ D.451 ]) [11 _4->func+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (reg/f:DI 87 [ D.451 ]) [11 _4->func+0 S8 A64]) (nil))) (insn 9 8 10 2 (set (reg/v/f:DI 89 [ cl ]) (mem/f:DI (reg/f:DI 104 [ _4->func ]) [3 _5->value_.gc+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 104 [ _4->func ]) (nil))) (insn 10 9 11 2 (set (reg:SI 1 dx) (const_int 0 [0])) 86 {*movsi_internal} (nil)) (insn 11 10 12 2 (set (reg:SI 4 si) (const_int 0 [0])) 86 {*movsi_internal} (nil)) (insn 12 11 13 2 (set (reg:DI 5 di) (reg/f:DI 87 [ D.451 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 87 [ D.451 ]) (nil))) (call_insn 13 12 14 2 (call (mem:QI (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) [0 raviV_op_loadnil S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:SI 4 si) (expr_list:REG_DEAD (reg:SI 1 dx) (expr_list:REG_CALL_DECL (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil))))) (insn 14 13 15 2 (set (reg/f:DI 105 [ L_3(D)->ci ]) (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn 15 14 16 2 (set (reg/v/f:DI 91 [ base ]) (mem/f:DI (plus:DI (reg/f:DI 105 [ L_3(D)->ci ]) (const_int 32 [0x20])) [11 _8->u.l.base+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 105 [ L_3(D)->ci ]) (nil))) (insn 16 15 17 2 (set (reg/f:DI 106 [ cl_6->p ]) (mem/f:DI (plus:DI (reg/v/f:DI 89 [ cl ]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 89 [ cl ]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64]) (nil))) (insn 17 16 18 2 (set (reg/f:DI 93 [ D.452 ]) (mem/f:DI (plus:DI (reg/f:DI 106 [ cl_6->p ]) (const_int 48 [0x30])) [11 _10->k+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 106 [ cl_6->p ]) (nil))) (insn 18 17 19 2 (set (reg:DI 94 [ D.454 ]) (mem:DI (reg/f:DI 93 [ D.452 ]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem:DI (reg/f:DI 93 [ D.452 ]) [7 _11->value_.i+0 S8 A64]) (nil))) (insn 19 18 20 2 (set (mem:DI (plus:DI (reg/v/f:DI 91 [ base ]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 94 [ D.454 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 94 [ D.454 ]) (nil))) (insn 20 19 21 2 (set (mem:SI (plus:DI (reg/v/f:DI 91 [ base ]) (const_int 24 [0x18])) [5 MEM[(struct ravi_TValue *)base_9 + 16B].tt_+0 S4 A64]) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 21 20 22 2 (set (reg:DI 95 [ D.454 ]) (mem:DI (reg/f:DI 93 [ D.452 ]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 93 [ D.452 ]) (expr_list:REG_EQUIV (mem:DI (plus:DI (reg/v/f:DI 91 [ base ]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (nil)))) (insn 22 21 23 2 (set (mem:DI (plus:DI (reg/v/f:DI 91 [ base ]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 95 [ D.454 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 95 [ D.454 ]) (expr_list:REG_DEAD (reg/v/f:DI 91 [ base ]) (nil)))) (insn 23 22 24 2 (set (reg:SI 1 dx) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 24 23 25 2 (set (reg:SI 4 si) (const_int 13 [0xd])) 86 {*movsi_internal} (nil)) (insn 25 24 26 2 (set (reg:DI 5 di) (symbol_ref/f:DI ("*.LC0") [flags 0x2] )) 85 {*movdi_internal} (nil)) (insn 26 25 27 2 (set (reg:QI 0 ax) (const_int 0 [0])) 89 {*movqi_internal} (nil)) (call_insn 27 26 28 2 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("printf") [flags 0x41] ) [0 printf S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:SI 4 si) (expr_list:REG_DEAD (reg:SI 1 dx) (expr_list:REG_UNUSED (reg:SI 0 ax) (expr_list:REG_CALL_DECL (symbol_ref:DI ("printf") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))))))) (expr_list (use (reg:QI 0 ax)) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil)))))) (insn 28 27 29 2 (set (reg/f:DI 107 [ L_3(D)->ci ]) (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn 29 28 30 2 (set (reg/v/f:DI 97 [ base ]) (mem/f:DI (plus:DI (reg/f:DI 107 [ L_3(D)->ci ]) (const_int 32 [0x20])) [11 _19->u.l.base+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 107 [ L_3(D)->ci ]) (nil))) (insn 30 29 31 2 (parallel [ (set (reg/f:DI 108) (plus:DI (reg/v/f:DI 97 [ base ]) (const_int 32 [0x20]))) (clobber (reg:CC 17 flags)) ]) 215 {*adddi_1} (expr_list:REG_UNUSED (reg:CC 17 flags) (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 16 [0x10])) [11 L_3(D)->top+0 S8 A64]) (nil)))) (insn 31 30 32 2 (set (mem/f:DI (plus:DI (reg/v/f:DI 103 [ L ]) (const_int 16 [0x10])) [11 L_3(D)->top+0 S8 A64]) (reg/f:DI 108)) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 108) (nil))) (insn 32 31 33 2 (set (reg/f:DI 109 [ cl_6->p ]) (mem/f:DI (plus:DI (reg/v/f:DI 89 [ cl ]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/v/f:DI 89 [ cl ]) (nil))) (insn 33 32 34 2 (set (reg:CCNO 17 flags) (compare:CCNO (mem:SI (plus:DI (reg/f:DI 109 [ cl_6->p ]) (const_int 32 [0x20])) [5 _23->sizep+0 S4 A64]) (const_int 0 [0]))) 3 {*cmpsi_ccno_1} (expr_list:REG_DEAD (reg/f:DI 109 [ cl_6->p ]) (nil))) (jump_insn 34 33 36 2 (set (pc) (if_then_else (le (reg:CCNO 17 flags) (const_int 0 [0])) (label_ref 40) (pc))) 601 {*jcc_1} (expr_list:REG_DEAD (reg:CCNO 17 flags) (int_list:REG_BR_PROB 3666 (nil))) -> 40) (note 36 34 35 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (note 35 36 37 3 ("OP_RETURN_if_sizep_gt_0_12_23") NOTE_INSN_DELETED_LABEL 4) (insn 37 35 38 3 (set (reg:DI 4 si) (reg/v/f:DI 97 [ base ])) 85 {*movdi_internal} (nil)) (insn 38 37 39 3 (set (reg:DI 5 di) (reg/v/f:DI 103 [ L ])) 85 {*movdi_internal} (nil)) (call_insn 39 38 40 3 (call (mem:QI (symbol_ref:DI ("luaF_close") [flags 0x41] ) [0 luaF_close S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:DI 4 si) (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaF_close") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (code_label 40 39 41 4 3 ("OP_RETURN_else_sizep_gt_0_12_24") [1 uses]) (note 41 40 42 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 42 41 43 4 (parallel [ (set (reg/f:DI 110 [ D.452 ]) (plus:DI (reg/v/f:DI 97 [ base ]) (const_int 16 [0x10]))) (clobber (reg:CC 17 flags)) ]) 215 {*adddi_1} (expr_list:REG_DEAD (reg/v/f:DI 97 [ base ]) (expr_list:REG_UNUSED (reg:CC 17 flags) (nil)))) (insn 43 42 44 4 (set (reg:DI 4 si) (reg/f:DI 110 [ D.452 ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 110 [ D.452 ]) (nil))) (insn 44 43 45 4 (set (reg:DI 5 di) (reg/v/f:DI 103 [ L ])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/v/f:DI 103 [ L ]) (nil))) (call_insn 45 44 50 4 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) [0 luaD_poscall S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:DI 4 si) (expr_list:REG_UNUSED (reg:SI 0 ax) (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (insn 50 45 51 4 (set (reg/i:SI 0 ax) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 51 50 0 4 (use (reg/i:SI 0 ax)) -1 (nil)) ; end of dump from pass_ira (../../src/gcc/ira.c:5512)