; start of dump from pass_reload (../../src/gcc/ira.c:5555) ;; Function ravif2 (ravif2, funcdef_no=0, decl_uid=364, cgraph_uid=0, symbol_order=0) ********** Local #1: ********** Spilling non-eliminable hard regs: 7 New elimination table: Can eliminate 16 to 7 (offset=32, prev_offset=0) Can eliminate 16 to 6 (offset=8, prev_offset=0) Can eliminate 20 to 7 (offset=0, prev_offset=0) Can eliminate 20 to 6 (offset=-24, prev_offset=0) alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 7: (0) r (1) rem {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 8: (0) r (1) rem {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 9: (0) r (1) rem {*movdi_internal} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 10: (0) =r (1) g {*movsi_internal} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 11: (0) =r (1) g {*movsi_internal} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 13: (0) rBwBz {*call} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 14: (0) r (1) rem {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 15: (0) r (1) rem {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 16: (0) r (1) rem {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 17: (0) r (1) rem {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 18: (0) r (1) rem {*movdi_internal} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3,overall=609,losers=1,rld_nregs=1 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=4: Bad operand -- refuse alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 19: (0) m (1) re {*movdi_internal} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0,overall=9,losers=1,rld_nregs=1 alt=1,overall=0,losers=0,rld_nregs=0 Choosing alt 1 in insn 20: (0) m (1) re {*movsi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 21: (0) r (1) rem {*movdi_internal} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3,overall=609,losers=1,rld_nregs=1 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=4: Bad operand -- refuse alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 22: (0) m (1) re {*movdi_internal} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 23: (0) =r (1) g {*movsi_internal} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 24: (0) =r (1) g {*movsi_internal} alt=2: Bad operand -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=3,overall=609,losers=1,rld_nregs=1 alt=4,overall=0,losers=0,rld_nregs=0 Choosing alt 4 in insn 25: (0) r (1) i {*movdi_internal} 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=609,losers=1,rld_nregs=1 alt=1,overall=0,losers=0,rld_nregs=0 Choosing alt 1 in insn 26: (0) q (1) qn {*movqi_internal} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 27: (1) rBwBz {*call_value} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 28: (0) r (1) rem {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 29: (0) r (1) rem {*movdi_internal} 1 Matching alt: reject+=2 alt=0,overall=8,losers=1,rld_nregs=1 1 Matching alt: reject+=2 alt=1,overall=8,losers=1,rld_nregs=1 2 Matching alt: reject+=2 2 Non-pseudo reload: reject+=2 2 Non input pseudo reload: reject++ alt=2,overall=11,losers=1 -- refuse alt=3,overall=0,losers=0,rld_nregs=0 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=11,losers=1 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=1,overall=11,losers=1 -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=2,overall=9,losers=1 -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=3,overall=9,losers=1 -- refuse Choosing alt 3 in insn 30: (0) r (1) r (2) le {*adddi_1} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=2: Bad operand -- refuse 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=3,overall=609,losers=1,rld_nregs=1 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=4: Bad operand -- refuse alt=5,overall=0,losers=0,rld_nregs=0 Choosing alt 5 in insn 31: (0) m (1) re {*movdi_internal} alt=2: Bad operand -- refuse alt=3,overall=0,losers=0,rld_nregs=0 Choosing alt 3 in insn 32: (0) r (1) rem {*movdi_internal} 0 Non-pseudo reload: reject+=2 0 Non input pseudo reload: reject++ alt=0,overall=9,losers=1,rld_nregs=1 Staticly defined alt reject+=6 alt=1,overall=6,losers=0,rld_nregs=0 Choosing alt 1 in insn 33: (0) ?mr {*cmpsi_ccno_1} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 39: (0) rBwBz {*call} alt=0,overall=6,losers=1,rld_nregs=1 alt=1,overall=6,losers=1,rld_nregs=1 2 Matching alt: reject+=2 2 Non-pseudo reload: reject+=2 2 Non input pseudo reload: reject++ alt=2,overall=11,losers=1 -- refuse alt=3,overall=0,losers=0,rld_nregs=0 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=0,overall=11,losers=1 -- refuse 1 Matching alt: reject+=2 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=1,overall=11,losers=1 -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=2,overall=9,losers=1 -- refuse 1 Non-pseudo reload: reject+=2 1 Non input pseudo reload: reject++ alt=3,overall=9,losers=1 -- refuse Choosing alt 3 in insn 42: (0) r (1) r (2) le {*adddi_1} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 45: (1) rBwBz {*call_value} alt=0,overall=0,losers=0,rld_nregs=0 Choosing alt 0 in insn 50: (0) =r (1) g {*movsi_internal} ********** Pseudo live ranges #1: ********** BB 4 Insn 51: point = 0 Insn 50: point = 0 Insn 45: point = 0 Insn 44: point = 0 Insn 43: point = 1 Insn 42: point = 2 BB 3 Insn 39: point = 5 Insn 38: point = 5 Insn 37: point = 5 BB 2 Insn 34: point = 6 Insn 33: point = 6 Insn 32: point = 7 Insn 31: point = 9 Insn 30: point = 10 Insn 29: point = 11 Insn 28: point = 13 Insn 27: point = 14 Insn 26: point = 14 Insn 25: point = 14 Insn 24: point = 14 Insn 23: point = 14 Insn 22: point = 14 Insn 21: point = 15 Insn 20: point = 17 Insn 19: point = 17 Insn 18: point = 18 Insn 17: point = 19 Insn 16: point = 21 Insn 15: point = 22 Insn 14: point = 24 Insn 13: point = 25 Insn 12: point = 25 Insn 11: point = 26 Insn 10: point = 26 Insn 9: point = 26 Insn 8: point = 28 Insn 7: point = 29 Insn 2: point = 30 Compressing live ranges: from 31 to 0 - 0% Ranges after the compression: Spilling non-eliminable hard regs: 7 New elimination table: Can eliminate 16 to 7 (offset=32, prev_offset=32) Can eliminate 16 to 6 (offset=8, prev_offset=0) Can eliminate 20 to 7 (offset=0, prev_offset=0) Can eliminate 20 to 6 (offset=-24, prev_offset=0) changing reg in insn 7 changing reg in insn 12 changing reg in insn 8 changing reg in insn 8 changing reg in insn 9 changing reg in insn 32 changing reg in insn 16 changing reg in insn 16 changing reg in insn 15 changing reg in insn 22 changing reg in insn 20 changing reg in insn 19 changing reg in insn 21 changing reg in insn 17 changing reg in insn 21 changing reg in insn 18 changing reg in insn 18 changing reg in insn 18 changing reg in insn 19 changing reg in insn 21 changing reg in insn 22 changing reg in insn 29 changing reg in insn 42 changing reg in insn 37 changing reg in insn 30 changing reg in insn 2 changing reg in insn 44 changing reg in insn 38 changing reg in insn 31 changing reg in insn 28 changing reg in insn 14 changing reg in insn 7 changing reg in insn 30 changing reg in insn 28 changing reg in insn 14 changing reg in insn 7 changing reg in insn 8 changing reg in insn 9 changing reg in insn 14 changing reg in insn 15 changing reg in insn 16 changing reg in insn 17 changing reg in insn 28 changing reg in insn 29 changing reg in insn 30 changing reg in insn 31 changing reg in insn 32 changing reg in insn 33 changing reg in insn 42 changing reg in insn 43 deleting insn with uid = 12. deleting insn with uid = 43. try_optimize_cfg iteration 1 starting the processing of deferred insns ending the processing of deferred insns verify found no changes in insn with uid = 13. verify found no changes in insn with uid = 27. verify found no changes in insn with uid = 39. verify found no changes in insn with uid = 45. starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) ravif2 Dataflow summary: ;; invalidated by call 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; hardware regs used 7 [sp] ;; regular block artificial uses 7 [sp] ;; eh block artificial uses 7 [sp] 16 [argp] ;; entry block defs 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 7 [sp] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] ;; exit block uses 0 [ax] 7 [sp] ;; regs ever live 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 17 [flags] 41 [r12] ;; ref usage r0={13d,11u,1e} r1={10d,6u,1e} r2={6d,1u} r3={1d,6u,4e} r4={9d,4u} r5={9d,6u,1e} r6={1d,3u} r7={1d,8u} r8={4d} r9={4d} r10={4d} r11={4d} r12={4d} r13={4d} r14={4d} r15={4d} r17={7d,1u} r18={4d} r19={4d} r21={5d} r22={5d} r23={5d} r24={5d} r25={5d} r26={5d} r27={5d} r28={5d} r29={4d} r30={4d} r31={4d} r32={4d} r33={4d} r34={4d} r35={4d} r36={4d} r37={5d} r38={5d} r39={4d} r40={4d} r41={1d,2u,1e} r45={4d} r46={4d} r47={4d} r48={4d} r49={4d} r50={4d} r51={4d} r52={4d} r53={4d} r54={4d} r55={4d} r56={4d} r57={4d} r58={4d} r59={4d} r60={4d} r61={4d} r62={4d} r63={4d} r64={4d} r65={4d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={4d} r79={4d} r80={4d} ;; total ref usage 388{332d,48u,8e} in 36{32 regular + 4 call} insns. (note 1 0 4 NOTE_INSN_DELETED) (note 4 1 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (insn 2 4 3 2 (set (reg/v/f:DI 3 bx [orig:103 L ] [103]) (reg:DI 5 di [ L ])) 85 {*movdi_internal} (nil)) (note 3 2 5 2 NOTE_INSN_FUNCTION_BEG) (note 5 3 7 2 ("entry") NOTE_INSN_DELETED_LABEL 2) (insn 7 5 8 2 (set (reg/f:DI 5 di [orig:87 D.451 ] [87]) (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn 8 7 9 2 (set (reg/f:DI 0 ax [orig:104 _4->func ] [104]) (mem/f:DI (reg/f:DI 5 di [orig:87 D.451 ] [87]) [11 _4->func+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (reg/f:DI 5 di [orig:87 D.451 ] [87]) [11 _4->func+0 S8 A64]) (nil))) (insn 9 8 10 2 (set (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (mem/f:DI (reg/f:DI 0 ax [orig:104 _4->func ] [104]) [3 _5->value_.gc+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 10 9 11 2 (set (reg:SI 1 dx) (const_int 0 [0])) 86 {*movsi_internal} (nil)) (insn 11 10 13 2 (set (reg:SI 4 si) (const_int 0 [0])) 86 {*movsi_internal} (nil)) (call_insn 13 11 14 2 (call (mem:QI (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) [0 raviV_op_loadnil S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_CALL_DECL (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil))))) (insn 14 13 15 2 (set (reg/f:DI 0 ax [orig:105 L_3(D)->ci ] [105]) (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn 15 14 16 2 (set (reg/v/f:DI 0 ax [orig:91 base ] [91]) (mem/f:DI (plus:DI (reg/f:DI 0 ax [orig:105 L_3(D)->ci ] [105]) (const_int 32 [0x20])) [11 _8->u.l.base+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 16 15 17 2 (set (reg/f:DI 1 dx [orig:106 cl_6->p ] [106]) (mem/f:DI (plus:DI (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64]) (nil))) (insn 17 16 18 2 (set (reg/f:DI 1 dx [orig:93 D.452 ] [93]) (mem/f:DI (plus:DI (reg/f:DI 1 dx [orig:106 cl_6->p ] [106]) (const_int 48 [0x30])) [11 _10->k+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 18 17 19 2 (set (reg:DI 2 cx [orig:94 D.454 ] [94]) (mem:DI (reg/f:DI 1 dx [orig:93 D.452 ] [93]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem:DI (reg/f:DI 1 dx [orig:93 D.452 ] [93]) [7 _11->value_.i+0 S8 A64]) (nil))) (insn 19 18 20 2 (set (mem:DI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 2 cx [orig:94 D.454 ] [94])) 85 {*movdi_internal} (nil)) (insn 20 19 21 2 (set (mem:SI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 24 [0x18])) [5 MEM[(struct ravi_TValue *)base_9 + 16B].tt_+0 S4 A64]) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 21 20 22 2 (set (reg:DI 1 dx [orig:95 D.454 ] [95]) (mem:DI (reg/f:DI 1 dx [orig:93 D.452 ] [93]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem:DI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (nil))) (insn 22 21 23 2 (set (mem:DI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 1 dx [orig:95 D.454 ] [95])) 85 {*movdi_internal} (nil)) (insn 23 22 24 2 (set (reg:SI 1 dx) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 24 23 25 2 (set (reg:SI 4 si) (const_int 13 [0xd])) 86 {*movsi_internal} (nil)) (insn 25 24 26 2 (set (reg:DI 5 di) (symbol_ref/f:DI ("*.LC0") [flags 0x2] )) 85 {*movdi_internal} (nil)) (insn 26 25 27 2 (set (reg:QI 0 ax) (const_int 0 [0])) 89 {*movqi_internal} (nil)) (call_insn 27 26 28 2 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("printf") [flags 0x41] ) [0 printf S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_CALL_DECL (symbol_ref:DI ("printf") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))) (expr_list (use (reg:QI 0 ax)) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil)))))) (insn 28 27 29 2 (set (reg/f:DI 0 ax [orig:107 L_3(D)->ci ] [107]) (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn 29 28 30 2 (set (reg/v/f:DI 6 bp [orig:97 base ] [97]) (mem/f:DI (plus:DI (reg/f:DI 0 ax [orig:107 L_3(D)->ci ] [107]) (const_int 32 [0x20])) [11 _19->u.l.base+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 30 29 31 2 (parallel [ (set (reg/f:DI 0 ax [108]) (plus:DI (reg/v/f:DI 6 bp [orig:97 base ] [97]) (const_int 32 [0x20]))) (clobber (reg:CC 17 flags)) ]) 215 {*adddi_1} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 16 [0x10])) [11 L_3(D)->top+0 S8 A64]) (nil))) (insn 31 30 32 2 (set (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 16 [0x10])) [11 L_3(D)->top+0 S8 A64]) (reg/f:DI 0 ax [108])) 85 {*movdi_internal} (nil)) (insn 32 31 33 2 (set (reg/f:DI 0 ax [orig:109 cl_6->p ] [109]) (mem/f:DI (plus:DI (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn 33 32 34 2 (set (reg:CCNO 17 flags) (compare:CCNO (mem:SI (plus:DI (reg/f:DI 0 ax [orig:109 cl_6->p ] [109]) (const_int 32 [0x20])) [5 _23->sizep+0 S4 A64]) (const_int 0 [0]))) 3 {*cmpsi_ccno_1} (nil)) (jump_insn 34 33 36 2 (set (pc) (if_then_else (le (reg:CCNO 17 flags) (const_int 0 [0])) (label_ref 40) (pc))) 601 {*jcc_1} (int_list:REG_BR_PROB 3666 (nil)) -> 40) (note 36 34 35 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (note 35 36 37 3 ("OP_RETURN_if_sizep_gt_0_12_23") NOTE_INSN_DELETED_LABEL 4) (insn 37 35 38 3 (set (reg:DI 4 si) (reg/v/f:DI 6 bp [orig:97 base ] [97])) 85 {*movdi_internal} (nil)) (insn 38 37 39 3 (set (reg:DI 5 di) (reg/v/f:DI 3 bx [orig:103 L ] [103])) 85 {*movdi_internal} (nil)) (call_insn 39 38 40 3 (call (mem:QI (symbol_ref:DI ("luaF_close") [flags 0x41] ) [0 luaF_close S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaF_close") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (code_label 40 39 41 4 3 ("OP_RETURN_else_sizep_gt_0_12_24") [1 uses]) (note 41 40 42 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (insn 42 41 44 4 (parallel [ (set (reg/f:DI 4 si [orig:110 D.452 ] [110]) (plus:DI (reg/v/f:DI 6 bp [orig:97 base ] [97]) (const_int 16 [0x10]))) (clobber (reg:CC 17 flags)) ]) 215 {*adddi_1} (nil)) (insn 44 42 45 4 (set (reg:DI 5 di) (reg/v/f:DI 3 bx [orig:103 L ] [103])) 85 {*movdi_internal} (nil)) (call_insn 45 44 50 4 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) [0 luaD_poscall S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (insn 50 45 51 4 (set (reg/i:SI 0 ax) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 51 50 54 4 (use (reg/i:SI 0 ax)) -1 (nil)) (note 54 51 0 NOTE_INSN_DELETED) ; end of dump from pass_reload (../../src/gcc/ira.c:5555)