; start of dump from pass_sched2 (../../src/gcc/sched-rgn.c:3767) ;; Function ravif2 (ravif2, funcdef_no=0, decl_uid=364, cgraph_uid=0, symbol_order=0) starting the processing of deferred insns ending the processing of deferred insns df_analyze called df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) ravif2 Dataflow summary: def_info->table_size = 330, use_info->table_size = 0 ;; invalidated by call 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; hardware regs used 7 [sp] ;; regular block artificial uses 7 [sp] ;; eh block artificial uses 7 [sp] 16 [argp] ;; entry block defs 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] 41 [r12] ;; exit block uses 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] ;; regs ever live 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 17 [flags] 41 [r12] ;; ref usage r0={14d,12u,1e} r1={10d,6u,1e} r2={6d,1u} r3={3d,7u,3e} r4={9d,4u} r5={9d,7u,1e} r6={3d,5u} r7={7d,14u} r8={4d} r9={4d} r10={4d} r11={4d} r12={4d} r13={4d} r14={4d} r15={4d} r17={8d,1u} r18={4d} r19={4d} r21={5d} r22={5d} r23={5d} r24={5d} r25={5d} r26={5d} r27={5d} r28={5d} r29={4d} r30={4d} r31={4d} r32={4d} r33={4d} r34={4d} r35={4d} r36={4d} r37={5d} r38={5d} r39={4d} r40={4d} r41={3d,4u,1e} r45={4d} r46={4d} r47={4d} r48={4d} r49={4d} r50={4d} r51={4d} r52={4d} r53={4d} r54={4d} r55={4d} r56={4d} r57={4d} r58={4d} r59={4d} r60={4d} r61={4d} r62={4d} r63={4d} r64={4d} r65={4d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={4d} r79={4d} r80={4d} ;; total ref usage 414{346d,61u,7e} in 44{40 regular + 4 call} insns. ( )->[0]->( 2 ) ;; bb 0 artificial_defs: { d-1(0){ }d-1(1){ }d-1(2){ }d-1(3){ }d-1(4){ }d-1(5){ }d-1(6){ }d-1(7){ }d-1(21){ }d-1(22){ }d-1(23){ }d-1(24){ }d-1(25){ }d-1(26){ }d-1(27){ }d-1(28){ }d-1(37){ }d-1(38){ }d-1(41){ }} ;; bb 0 artificial_uses: { } ;; lr in ;; lr use ;; lr def 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] 41 [r12] ;; live in ;; live gen 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] 41 [r12] ;; live kill ;; lr out 3 [bx] 5 [di] 6 [bp] 7 [sp] 41 [r12] ;; live out 3 [bx] 5 [di] 6 [bp] 7 [sp] 41 [r12] ( 0 )->[2]->( 3 4 ) ;; bb 2 artificial_defs: { } ;; bb 2 artificial_uses: { u-1(7){ }} ;; lr in 3 [bx] 5 [di] 6 [bp] 7 [sp] 41 [r12] ;; lr use 3 [bx] 5 [di] 6 [bp] 7 [sp] 41 [r12] ;; lr def 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 41 [r12] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; live in 3 [bx] 5 [di] 6 [bp] 7 [sp] 41 [r12] ;; live gen 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 17 [flags] 41 [r12] ;; live kill 17 [flags] ;; lr out 3 [bx] 6 [bp] 7 [sp] ;; live out 3 [bx] 6 [bp] 7 [sp] ( 2 )->[3]->( 4 ) ;; bb 3 artificial_defs: { } ;; bb 3 artificial_uses: { u-1(7){ }} ;; lr in 3 [bx] 6 [bp] 7 [sp] ;; lr use 3 [bx] 6 [bp] 7 [sp] ;; lr def 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; live in 3 [bx] 6 [bp] 7 [sp] ;; live gen 4 [si] 5 [di] ;; live kill ;; lr out 3 [bx] 6 [bp] 7 [sp] ;; live out 3 [bx] 6 [bp] 7 [sp] ( 2 3 )->[4]->( 1 ) ;; bb 4 artificial_defs: { } ;; bb 4 artificial_uses: { u-1(7){ }} ;; lr in 3 [bx] 6 [bp] 7 [sp] ;; lr use 3 [bx] 6 [bp] 7 [sp] ;; lr def 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 41 [r12] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; live in 3 [bx] 6 [bp] 7 [sp] ;; live gen 0 [ax] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 41 [r12] ;; live kill ;; lr out 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] ;; live out 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] ( 4 )->[1]->( ) ;; bb 1 artificial_defs: { } ;; bb 1 artificial_uses: { u-1(0){ }u-1(3){ }u-1(6){ }u-1(7){ }u-1(41){ }} ;; lr in 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] ;; lr use 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] ;; lr def ;; live in 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] ;; live gen ;; live kill ;; lr out ;; live out Finding needed instructions: Adding insn 34 to worklist Adding insn 31 to worklist Adding insn 27 to worklist Adding insn 22 to worklist Adding insn 20 to worklist Adding insn 19 to worklist Adding insn 13 to worklist Adding insn 63 to worklist Adding insn 62 to worklist Adding insn 61 to worklist Adding insn 39 to worklist Adding insn 71 to worklist Adding insn 51 to worklist Adding insn 45 to worklist Finished finding needed instructions: processing block 4 lr out = 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] Adding insn 70 to worklist Adding insn 69 to worklist Adding insn 68 to worklist Adding insn 50 to worklist Adding insn 44 to worklist Adding insn 59 to worklist processing block 3 lr out = 3 [bx] 6 [bp] 7 [sp] Adding insn 38 to worklist Adding insn 37 to worklist processing block 2 lr out = 3 [bx] 6 [bp] 7 [sp] Adding insn 79 to worklist Adding insn 78 to worklist Adding insn 32 to worklist Adding insn 60 to worklist Adding insn 29 to worklist Adding insn 28 to worklist Adding insn 77 to worklist Adding insn 25 to worklist Adding insn 24 to worklist Adding insn 23 to worklist Adding insn 21 to worklist Adding insn 18 to worklist Adding insn 17 to worklist Adding insn 16 to worklist Adding insn 15 to worklist Adding insn 14 to worklist Adding insn 76 to worklist Adding insn 75 to worklist Adding insn 9 to worklist Adding insn 8 to worklist Adding insn 7 to worklist Adding insn 2 to worklist df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 5 count 5 ( 1) ;; ====================================================== ;; -- basic block 2 from 61 to 34 -- after reload ;; ====================================================== ;; 0--> b 0: i 61 [--sp]=r12 :bdver1-direct,bdver1-agu,bdver1-store ;; 0--> b 0: i 62 [--sp]=bp :bdver1-direct,bdver1-agu,bdver1-store ;; 0--> b 0: i 75 {dx=0;clobber flags;} :bdver1-direct,bdver1-ieu ;; 1--> b 0: i 63 [--sp]=bx :bdver1-direct,bdver1-agu,bdver1-store ;; 1--> b 0: i 2 bx=di :bdver1-direct,bdver1-ieu ;; 1--> b 0: i 7 di=[di+0x20] :bdver1-direct,bdver1-load ;; 2--> b 0: i 76 {si=0;clobber flags;} :bdver1-direct,bdver1-ieu ;; 5--> b 0: i 8 ax=[di] :bdver1-direct,bdver1-load ;; 9--> b 0: i 9 r12=[ax] :bdver1-direct,bdver1-load ;; 9--> b 0: i 13 call [`raviV_op_loadnil'] :bdver1-double,bdver1-agu ;; 10--> b 0: i 14 ax=[bx+0x20] :bdver1-direct,bdver1-load ;; 10--> b 0: i 24 si=0xd :bdver1-direct,bdver1-ieu ;; 10--> b 0: i 25 di=`*.LC0' :bdver1-direct,bdver1-agu ;; 13--> b 0: i 16 dx=[r12+0x18] :bdver1-direct,bdver1-load ;; 14--> b 0: i 15 ax=[ax+0x20] :bdver1-direct,bdver1-load ;; 17--> b 0: i 17 dx=[dx+0x30] :bdver1-direct,bdver1-load ;; 21--> b 0: i 18 cx=[dx] :bdver1-direct,bdver1-load ;; 21--> b 0: i 20 [ax+0x18]=0x1 :bdver1-direct,bdver1-agu,bdver1-store ;; 25--> b 0: i 19 [ax+0x10]=cx :bdver1-direct,bdver1-agu,bdver1-store ;; 26--> b 0: i 21 dx=[dx] :bdver1-direct,bdver1-load ;; 30--> b 0: i 22 [ax+0x10]=dx :bdver1-direct,bdver1-agu,bdver1-store ;; 30--> b 0: i 23 dx=0x1 :bdver1-direct,bdver1-ieu ;; 30--> b 0: i 77 {ax=0;clobber flags;} :bdver1-direct,bdver1-ieu ;; 34--> b 0: i 27 ax=call [`printf'] :bdver1-double,bdver1-agu ;; 34--> b 0: i 28 ax=[bx+0x20] :bdver1-direct,bdver1-load ;; 38--> b 0: i 29 bp=[ax+0x20] :bdver1-direct,bdver1-load ;; 42--> b 0: i 60 ax=bp+0x20 :bdver1-direct,bdver1-agu ;; 43--> b 0: i 31 [bx+0x10]=ax :bdver1-direct,bdver1-agu,bdver1-store ;; 43--> b 0: i 32 ax=[r12+0x18] :bdver1-direct,bdver1-load ;; 47--> b 0: i 78 ax=[ax+0x20] :bdver1-direct,bdver1-load ;; 51--> b 0: i 79 flags=cmp(ax,0) :bdver1-direct,bdver1-ieu ;; 51--> b 0: i 34 pc={(flags<=0)?L40:pc} :bdver1-direct,bdver1-ieu ;; Ready list (final): ;; total time = 51 ;; new head = 61 ;; new tail = 34 ;; ====================================================== ;; -- basic block 3 from 37 to 39 -- after reload ;; ====================================================== ;; 0--> b 0: i 37 si=bp :bdver1-direct,bdver1-ieu ;; 0--> b 0: i 38 di=bx :bdver1-direct,bdver1-ieu ;; 1--> b 0: i 39 call [`luaF_close'] :bdver1-double,bdver1-agu ;; Ready list (final): ;; total time = 1 ;; new head = 37 ;; new tail = 39 ;; ====================================================== ;; -- basic block 4 from 59 to 71 -- after reload ;; ====================================================== ;; 0--> b 0: i 59 si=bp+0x10 :bdver1-direct,bdver1-agu ;; 0--> b 0: i 44 di=bx :bdver1-direct,bdver1-ieu ;; 1--> b 0: i 45 ax=call [`luaD_poscall'] :bdver1-double,bdver1-agu ;; 1--> b 0: i 50 ax=0x1 :bdver1-direct,bdver1-ieu ;; 1--> b 0: i 51 use ax :nothing ;; 2--> b 0: i 68 bx=[sp++] :bdver1-direct,bdver1-ivector ;; 3--> b 0: i 69 bp=[sp++] :bdver1-direct,bdver1-ivector ;; 4--> b 0: i 70 r12=[sp++] :bdver1-direct,bdver1-ivector ;; 5--> b 0: i 71 simple_return :bdver1-direct,bdver1-ieu ;; Ready list (final): ;; total time = 5 ;; new head = 59 ;; new tail = 71 starting the processing of deferred insns ending the processing of deferred insns ravif2 Dataflow summary: ;; invalidated by call 0 [ax] 1 [dx] 2 [cx] 4 [si] 5 [di] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [r8] 38 [r9] 39 [r10] 40 [r11] 45 [xmm8] 46 [xmm9] 47 [xmm10] 48 [xmm11] 49 [xmm12] 50 [xmm13] 51 [xmm14] 52 [xmm15] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] ;; hardware regs used 7 [sp] ;; regular block artificial uses 7 [sp] ;; eh block artificial uses 7 [sp] 16 [argp] ;; entry block defs 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 37 [r8] 38 [r9] 41 [r12] ;; exit block uses 0 [ax] 3 [bx] 6 [bp] 7 [sp] 41 [r12] ;; regs ever live 0 [ax] 1 [dx] 2 [cx] 3 [bx] 4 [si] 5 [di] 6 [bp] 7 [sp] 17 [flags] 41 [r12] ;; ref usage r0={14d,12u,1e} r1={10d,6u,1e} r2={6d,1u} r3={3d,7u,3e} r4={9d,4u} r5={9d,7u,1e} r6={3d,5u} r7={7d,14u} r8={4d} r9={4d} r10={4d} r11={4d} r12={4d} r13={4d} r14={4d} r15={4d} r17={8d,1u} r18={4d} r19={4d} r21={5d} r22={5d} r23={5d} r24={5d} r25={5d} r26={5d} r27={5d} r28={5d} r29={4d} r30={4d} r31={4d} r32={4d} r33={4d} r34={4d} r35={4d} r36={4d} r37={5d} r38={5d} r39={4d} r40={4d} r41={3d,4u,1e} r45={4d} r46={4d} r47={4d} r48={4d} r49={4d} r50={4d} r51={4d} r52={4d} r53={4d} r54={4d} r55={4d} r56={4d} r57={4d} r58={4d} r59={4d} r60={4d} r61={4d} r62={4d} r63={4d} r64={4d} r65={4d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={4d} r79={4d} r80={4d} ;; total ref usage 414{346d,61u,7e} in 44{40 regular + 4 call} insns. (note 1 0 55 NOTE_INSN_DELETED) (note 55 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK) (note 3 55 5 2 NOTE_INSN_FUNCTION_BEG) (note 5 3 61 2 ("entry") NOTE_INSN_DELETED_LABEL 2) (insn/f:TI 61 5 62 2 (set (mem:DI (pre_dec:DI (reg/f:DI 7 sp)) [0 S8 A8]) (reg:DI 41 r12)) 61 {*pushdi2_rex64} (expr_list:REG_DEAD (reg:DI 41 r12) (nil))) (insn/f 62 61 75 2 (set (mem:DI (pre_dec:DI (reg/f:DI 7 sp)) [0 S8 A8]) (reg:DI 6 bp)) 61 {*pushdi2_rex64} (expr_list:REG_DEAD (reg:DI 6 bp) (nil))) (insn 75 62 63 2 (parallel [ (set (reg:DI 1 dx) (const_int 0 [0])) (clobber (reg:CC 17 flags)) ]) 79 {*movdi_xor} (expr_list:REG_UNUSED (reg:CC 17 flags) (nil))) (insn/f:TI 63 75 64 2 (set (mem:DI (pre_dec:DI (reg/f:DI 7 sp)) [0 S8 A8]) (reg:DI 3 bx)) 61 {*pushdi2_rex64} (expr_list:REG_DEAD (reg:DI 3 bx) (nil))) (note 64 63 2 2 NOTE_INSN_PROLOGUE_END) (insn 2 64 7 2 (set (reg/v/f:DI 3 bx [orig:103 L ] [103]) (reg:DI 5 di [ L ])) 85 {*movdi_internal} (nil)) (insn 7 2 76 2 (set (reg/f:DI 5 di [orig:87 D.451 ] [87]) (mem/f:DI (plus:DI (reg/f:DI 5 di [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn:TI 76 7 8 2 (parallel [ (set (reg:DI 4 si) (const_int 0 [0])) (clobber (reg:CC 17 flags)) ]) 79 {*movdi_xor} (expr_list:REG_UNUSED (reg:CC 17 flags) (nil))) (insn:TI 8 76 9 2 (set (reg/f:DI 0 ax [orig:104 _4->func ] [104]) (mem/f:DI (reg/f:DI 5 di [orig:87 D.451 ] [87]) [11 _4->func+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (reg/f:DI 5 di [orig:87 D.451 ] [87]) [11 _4->func+0 S8 A64]) (nil))) (insn:TI 9 8 13 2 (set (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (mem/f:DI (reg/f:DI 0 ax [orig:104 _4->func ] [104]) [3 _5->value_.gc+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 0 ax [orig:104 _4->func ] [104]) (nil))) (call_insn 13 9 14 2 (call (mem:QI (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) [0 raviV_op_loadnil S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:SI 4 si) (expr_list:REG_DEAD (reg:SI 1 dx) (expr_list:REG_CALL_DECL (symbol_ref:DI ("raviV_op_loadnil") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil))))) (insn:TI 14 13 24 2 (set (reg/f:DI 0 ax [orig:105 L_3(D)->ci ] [105]) (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn 24 14 25 2 (set (reg:SI 4 si) (const_int 13 [0xd])) 86 {*movsi_internal} (nil)) (insn 25 24 16 2 (set (reg:DI 5 di) (symbol_ref/f:DI ("*.LC0") [flags 0x2] )) 85 {*movdi_internal} (nil)) (insn:TI 16 25 15 2 (set (reg/f:DI 1 dx [orig:106 cl_6->p ] [106]) (mem/f:DI (plus:DI (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64]) (nil))) (insn:TI 15 16 17 2 (set (reg/v/f:DI 0 ax [orig:91 base ] [91]) (mem/f:DI (plus:DI (reg/f:DI 0 ax [orig:105 L_3(D)->ci ] [105]) (const_int 32 [0x20])) [11 _8->u.l.base+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn:TI 17 15 18 2 (set (reg/f:DI 1 dx [orig:93 D.452 ] [93]) (mem/f:DI (plus:DI (reg/f:DI 1 dx [orig:106 cl_6->p ] [106]) (const_int 48 [0x30])) [11 _10->k+0 S8 A64])) 85 {*movdi_internal} (nil)) (insn:TI 18 17 20 2 (set (reg:DI 2 cx [orig:94 D.454 ] [94]) (mem:DI (reg/f:DI 1 dx [orig:93 D.452 ] [93]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem:DI (reg/f:DI 1 dx [orig:93 D.452 ] [93]) [7 _11->value_.i+0 S8 A64]) (nil))) (insn 20 18 19 2 (set (mem:SI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 24 [0x18])) [5 MEM[(struct ravi_TValue *)base_9 + 16B].tt_+0 S4 A64]) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn:TI 19 20 21 2 (set (mem:DI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 2 cx [orig:94 D.454 ] [94])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 2 cx [orig:94 D.454 ] [94]) (nil))) (insn:TI 21 19 22 2 (set (reg:DI 1 dx [orig:95 D.454 ] [95]) (mem:DI (reg/f:DI 1 dx [orig:93 D.452 ] [93]) [7 _11->value_.i+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem:DI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (nil))) (insn:TI 22 21 23 2 (set (mem:DI (plus:DI (reg/v/f:DI 0 ax [orig:91 base ] [91]) (const_int 16 [0x10])) [7 MEM[(struct ravi_TValue *)base_9 + 16B].value_.i+0 S8 A64]) (reg:DI 1 dx [orig:95 D.454 ] [95])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg:DI 1 dx [orig:95 D.454 ] [95]) (expr_list:REG_DEAD (reg/v/f:DI 0 ax [orig:91 base ] [91]) (nil)))) (insn 23 22 77 2 (set (reg:SI 1 dx) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 77 23 27 2 (parallel [ (set (reg:DI 0 ax) (const_int 0 [0])) (clobber (reg:CC 17 flags)) ]) 79 {*movdi_xor} (expr_list:REG_UNUSED (reg:CC 17 flags) (nil))) (call_insn:TI 27 77 28 2 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("printf") [flags 0x41] ) [0 printf S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:SI 4 si) (expr_list:REG_DEAD (reg:SI 1 dx) (expr_list:REG_UNUSED (reg:SI 0 ax) (expr_list:REG_CALL_DECL (symbol_ref:DI ("printf") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))))))) (expr_list (use (reg:QI 0 ax)) (expr_list:DI (use (reg:DI 5 di)) (expr_list:SI (use (reg:SI 4 si)) (expr_list:SI (use (reg:SI 1 dx)) (nil)))))) (insn 28 27 29 2 (set (reg/f:DI 0 ax [orig:107 L_3(D)->ci ] [107]) (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_EQUIV (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 32 [0x20])) [13 L_3(D)->ci+0 S8 A64]) (nil))) (insn:TI 29 28 60 2 (set (reg/v/f:DI 6 bp [orig:97 base ] [97]) (mem/f:DI (plus:DI (reg/f:DI 0 ax [orig:107 L_3(D)->ci ] [107]) (const_int 32 [0x20])) [11 _19->u.l.base+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 0 ax [orig:107 L_3(D)->ci ] [107]) (nil))) (insn:TI 60 29 31 2 (set (reg/f:DI 0 ax [108]) (plus:DI (reg/v/f:DI 6 bp [orig:97 base ] [97]) (const_int 32 [0x20]))) 208 {*leadi} (nil)) (insn:TI 31 60 32 2 (set (mem/f:DI (plus:DI (reg/v/f:DI 3 bx [orig:103 L ] [103]) (const_int 16 [0x10])) [11 L_3(D)->top+0 S8 A64]) (reg/f:DI 0 ax [108])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/f:DI 0 ax [108]) (nil))) (insn 32 31 78 2 (set (reg/f:DI 0 ax [orig:109 cl_6->p ] [109]) (mem/f:DI (plus:DI (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (const_int 24 [0x18])) [27 cl_6->p+0 S8 A64])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/v/f:DI 41 r12 [orig:89 cl ] [89]) (nil))) (insn:TI 78 32 79 2 (set (reg:SI 0 ax) (mem:SI (plus:DI (reg/f:DI 0 ax [orig:109 cl_6->p ] [109]) (const_int 32 [0x20])) [5 _23->sizep+0 S4 A64])) 86 {*movsi_internal} (nil)) (insn:TI 79 78 34 2 (set (reg:CCNO 17 flags) (compare:CCNO (reg:SI 0 ax) (const_int 0 [0]))) 3 {*cmpsi_ccno_1} (expr_list:REG_DEAD (reg:SI 0 ax) (nil))) (jump_insn 34 79 36 2 (set (pc) (if_then_else (le (reg:CCNO 17 flags) (const_int 0 [0])) (label_ref 40) (pc))) 601 {*jcc_1} (expr_list:REG_DEAD (reg:CCNO 17 flags) (int_list:REG_BR_PROB 3666 (nil))) -> 40) (note 36 34 35 3 [bb 3] NOTE_INSN_BASIC_BLOCK) (note 35 36 37 3 ("OP_RETURN_if_sizep_gt_0_12_23") NOTE_INSN_DELETED_LABEL 4) (insn:TI 37 35 38 3 (set (reg:DI 4 si) (reg/v/f:DI 6 bp [orig:97 base ] [97])) 85 {*movdi_internal} (nil)) (insn 38 37 39 3 (set (reg:DI 5 di) (reg/v/f:DI 3 bx [orig:103 L ] [103])) 85 {*movdi_internal} (nil)) (call_insn:TI 39 38 40 3 (call (mem:QI (symbol_ref:DI ("luaF_close") [flags 0x41] ) [0 luaF_close S1 A8]) (const_int 0 [0])) 647 {*call} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:DI 4 si) (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaF_close") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (code_label 40 39 41 4 3 ("OP_RETURN_else_sizep_gt_0_12_24") [1 uses]) (note 41 40 56 4 [bb 4] NOTE_INSN_BASIC_BLOCK) (note 56 41 59 4 NOTE_INSN_DELETED) (insn:TI 59 56 44 4 (set (reg/f:DI 4 si [orig:110 D.452 ] [110]) (plus:DI (reg/v/f:DI 6 bp [orig:97 base ] [97]) (const_int 16 [0x10]))) 208 {*leadi} (expr_list:REG_DEAD (reg/v/f:DI 6 bp [orig:97 base ] [97]) (nil))) (insn 44 59 45 4 (set (reg:DI 5 di) (reg/v/f:DI 3 bx [orig:103 L ] [103])) 85 {*movdi_internal} (expr_list:REG_DEAD (reg/v/f:DI 3 bx [orig:103 L ] [103]) (nil))) (call_insn:TI 45 44 50 4 (set (reg:SI 0 ax) (call (mem:QI (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) [0 luaD_poscall S1 A8]) (const_int 0 [0]))) 657 {*call_value} (expr_list:REG_DEAD (reg:DI 5 di) (expr_list:REG_DEAD (reg:DI 4 si) (expr_list:REG_UNUSED (reg:SI 0 ax) (expr_list:REG_CALL_DECL (symbol_ref:DI ("luaD_poscall") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int 0 [0]) (nil)))))) (expr_list:DI (use (reg:DI 5 di)) (expr_list:DI (use (reg:DI 4 si)) (nil)))) (insn 50 45 51 4 (set (reg/i:SI 0 ax) (const_int 1 [0x1])) 86 {*movsi_internal} (nil)) (insn 51 50 80 4 (use (reg/i:SI 0 ax)) -1 (nil)) (note 80 51 68 4 NOTE_INSN_EPILOGUE_BEG) (insn/f:TI 68 80 69 4 (set (reg:DI 3 bx) (mem:DI (post_inc:DI (reg/f:DI 7 sp)) [0 S8 A8])) 71 {*popdi1} (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:DI 7 sp) (plus:DI (reg/f:DI 7 sp) (const_int 8 [0x8]))) (nil))) (insn/f:TI 69 68 70 4 (set (reg:DI 6 bp) (mem:DI (post_inc:DI (reg/f:DI 7 sp)) [0 S8 A8])) 71 {*popdi1} (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:DI 7 sp) (plus:DI (reg/f:DI 7 sp) (const_int 8 [0x8]))) (nil))) (insn/f:TI 70 69 71 4 (set (reg:DI 41 r12) (mem:DI (post_inc:DI (reg/f:DI 7 sp)) [0 S8 A8])) 71 {*popdi1} (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:DI 7 sp) (plus:DI (reg/f:DI 7 sp) (const_int 8 [0x8]))) (nil))) (jump_insn:TI 71 70 72 4 (simple_return) 669 {simple_return_internal} (nil) -> simple_return) (barrier 72 71 54) (note 54 72 0 NOTE_INSN_DELETED) ; end of dump from pass_sched2 (../../src/gcc/sched-rgn.c:3767)