GCC Middle and Back End API Reference
target_ira Struct Reference

#include <ira.h>

Data Fields

enum reg_class x_ira_hard_regno_allocno_class [FIRST_PSEUDO_REGISTER]
int x_ira_allocno_classes_num
enum reg_class x_ira_allocno_classes [N_REG_CLASSES]
enum reg_class x_ira_allocno_class_translate [N_REG_CLASSES]
int x_ira_pressure_classes_num
enum reg_class x_ira_pressure_classes [N_REG_CLASSES]
enum reg_class x_ira_pressure_class_translate [N_REG_CLASSES]
enum reg_class x_ira_stack_reg_pressure_class
unsigned char x_ira_reg_class_max_nregs [N_REG_CLASSES][MAX_MACHINE_MODE]
unsigned char x_ira_reg_class_min_nregs [N_REG_CLASSES][MAX_MACHINE_MODE]
short x_ira_memory_move_cost [MAX_MACHINE_MODE][N_REG_CLASSES][2]
short x_ira_class_hard_regs [N_REG_CLASSES][FIRST_PSEUDO_REGISTER]
int x_ira_class_hard_regs_num [N_REG_CLASSES]
int x_ira_class_subset_p [N_REG_CLASSES][N_REG_CLASSES]
enum reg_class x_ira_reg_class_subset [N_REG_CLASSES][N_REG_CLASSES]
bool x_ira_reg_classes_intersect_p [N_REG_CLASSES][N_REG_CLASSES]
short x_ira_class_singleton [N_REG_CLASSES][MAX_MACHINE_MODE]
HARD_REG_SET x_ira_no_alloc_regs

Field Documentation

enum reg_class target_ira::x_ira_allocno_class_translate[N_REG_CLASSES]
     Map of all register classes to corresponding allocno classes
     containing the given class.  If given class is not a subset of an
     allocno class, we translate it into the cheapest allocno class.  
enum reg_class target_ira::x_ira_allocno_classes[N_REG_CLASSES]
     The array containing allocno classes.  Only first
     IRA_ALLOCNO_CLASSES_NUM elements are used for this.  
int target_ira::x_ira_allocno_classes_num
     Number of allocno classes.  Allocno classes are register classes
     which can be used for allocations of allocnos.  
short target_ira::x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]
     Array of number of hard registers of given class which are
     available for the allocation.  The order is defined by the
     allocation order.  
int target_ira::x_ira_class_hard_regs_num[N_REG_CLASSES]
     The number of elements of the above array for given register
short target_ira::x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE]
     If class CL has a single allocatable register of mode M,
     index [CL][M] gives the number of that register, otherwise it is -1.  
int target_ira::x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES]
     Register class subset relation: TRUE if the first class is a subset
     of the second one considering only hard registers available for the
enum reg_class target_ira::x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER]
     Map: hard register number -> allocno class it belongs to.  If the
     corresponding class is NO_REGS, the hard register is not available
     for allocation.  
short target_ira::x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]
     Array analogous to target hook TARGET_MEMORY_MOVE_COST.  
HARD_REG_SET target_ira::x_ira_no_alloc_regs
     Function specific hard registers can not be used for the register
enum reg_class target_ira::x_ira_pressure_class_translate[N_REG_CLASSES]
     Map of all register classes to corresponding pressure classes
     containing the given class.  If given class is not a subset of an
     pressure class, we translate it into the cheapest pressure
enum reg_class target_ira::x_ira_pressure_classes[N_REG_CLASSES]
     The array containing pressure classes.  Only first
     IRA_PRESSURE_CLASSES_NUM elements are used for this.  
int target_ira::x_ira_pressure_classes_num
     Number of pressure classes.  Pressure classes are register
     classes for which we calculate register pressure.  
unsigned char target_ira::x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]
     Maps: register class x machine mode -> maximal/minimal number of
     hard registers of given class needed to store value of given
unsigned char target_ira::x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]
enum reg_class target_ira::x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES]
     The biggest class inside of intersection of the two classes (that
     is calculated taking only hard registers available for allocation
     into account.  If the both classes contain no hard registers
     available for allocation, the value is calculated with taking all
     hard-registers including fixed ones into account.  
bool target_ira::x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES]
     True if the two classes (that is calculated taking only hard
     registers available for allocation into account; are
enum reg_class target_ira::x_ira_stack_reg_pressure_class
     Bigest pressure register class containing stack registers.
     NO_REGS if there are no stack registers.  

The documentation for this struct was generated from the following file: