GCC Middle and Back End API Reference

#include "diagnosticcore.h"
Variables  
static vect_recog_func_ptr  vect_vect_recog_func_ptrs [NUM_PATTERNS] 

static 
Helper function of vect_recog_bool_pattern. Do the actual transformations, recursively. VAR is an SSA_NAME that should be transformed from bool to a wider integer type, OUT_TYPE is the desired final integer type of the whole pattern, TRUEVAL should be NULL unless optimizing BIT_AND_EXPR into a COND_EXPR with one integer from one of the operands in the then_clause, STMTS is where statements with added pattern stmts should be pushed to.
Try to optimize x = y & (a < b ? 1 : 0); into x = (a < b ? y : 0); E.g. for: bool a_b, b_b, c_b; TYPE d_T; S1 a_b = x1 CMP1 y1; S2 b_b = x2 CMP2 y2; S3 c_b = a_b & b_b; S4 d_T = (TYPE) c_b; we would normally emit: S1' a_T = x1 CMP1 y1 ? 1 : 0; S2' b_T = x2 CMP2 y2 ? 1 : 0; S3' c_T = a_T & b_T; S4' d_T = c_T; but we can save one stmt by using the result of one of the COND_EXPRs in the other COND_EXPR and leave BIT_AND_EXPR stmt out: S1' a_T = x1 CMP1 y1 ? 1 : 0; S3' c_T = x2 CMP2 y2 ? a_T : 0; S4' f_T = c_T; At least when VEC_COND_EXPR is implemented using masks cond ? 1 : 0 is as expensive as cond ? var : 0, in both cases it computes the comparison masks and ands it, in one case with all ones vector, in the other case with a vector register. Don't do this for BIT_IOR_EXPR, because cond ? 1 : var; is often more expensive.
FALLTHRU
Referenced by check_bool_pattern().

static 
Helper function of adjust_bool_pattern. Add a cast to TYPE to a previous stmt (SSA_NAME_DEF_STMT of VAR) by moving the COND_EXPR from RELATED_STMT to PATTERN_DEF_SEQ and adding a cast as RELATED_STMT.

inlinestatic 

static 
Helper function of vect_recog_bool_pattern. Called recursively, return true if bool VAR can be optimized that way.
If the comparison can throw, then is_gimple_condexpr will be false and we can't make a COND_EXPR/VEC_COND_EXPR out of it.
References adjust_bool_pattern(), build_int_cst(), gimple_assign_rhs1(), gimple_assign_rhs2(), gimple_assign_rhs_code(), gimple_build_assign_with_ops(), gimple_location(), tcc_comparison, vect_recog_temp_ssa_var(), and vinfo_for_stmt().

inlinestatic 

static 
Check whether NAME, an ssaname used in USE_STMT, is a result of a type promotion or demotion, such that: DEF_STMT: NAME = NOP (name0) where the type of name0 (ORIG_TYPE) is smaller/bigger than the type of NAME. If CHECK_SIGN is TRUE, check that either both types are signed or both are unsigned.

static 
Handle widening operation by a constant. At the moment we support MULT_EXPR and LSHIFT_EXPR. For MULT_EXPR we check that CONST_OPRND fits HALF_TYPE, and for LSHIFT_EXPR we check that CONST_OPRND is less or equal to the size of HALF_TYPE. Otherwise, if the type of the result (TYPE) is at least 4 times bigger than HALF_TYPE, and there is an intermediate type (2 times smaller than TYPE) that satisfies the above restrictions, we can perform a widening opeartion from the intermediate type to TYPE and replace a_T = (TYPE) a_t; with a_it = (interm_type) a_t;
CONST_OPRND is a constant of HALF_TYPE.
TYPE is 4 times bigger than HALF_TYPE, try widening operation for a type 2 times bigger than HALF_TYPE.
Use NEW_TYPE for widening operation.
Check if the already created pattern stmt is what we need.
Create a_T = (NEW_TYPE) a_t;

inlinestatic 
Mark statements that are involved in a pattern.

static 
Return TRUE if the operation in STMT can be performed on a smaller type. Input: STMT  a statement to check. DEF  we support operations with two operands, one of which is constant. The other operand can be defined by a demotion operation, or by a previous statement in a sequence of overpromoted operations. In the later case DEF is used to replace that operand. (It is defined by a pattern statement we created for the previous statement in the sequence). Input/output: NEW_TYPE  Output: a smaller type that we are trying to use. Input: if not NULL, it's the type of DEF. STMTS  additional pattern statements. If a pattern statement (type conversion) is created in this function, its original statement is added to STMTS. Output: OP0, OP1  if the operation fits a smaller type, OP0 and OP1 are the new operands to use in the new pattern statement for STMT (will be created in vect_recog_over_widening_pattern ()). NEW_DEF_STMT  in case DEF has to be promoted, we create two pattern statements for STMT: the first one is a type promotion and the second one is the operation itself. We return the type promotion statement in NEW_DEF_STMT and further store it in STMT_VINFO_PATTERN_DEF_SEQ of the second pattern statement.
If oprnd has other uses besides that in stmt we cannot mark it as being part of a pattern only.
If we are in the middle of a sequence, we use DEF from a previous statement. Otherwise, OPRND has to be a result of type promotion.
Can we perform the operation on a smaller type?
HALF_TYPE is not enough. Try a bigger type if possible.
Try intermediate type  HALF_TYPE is not enough for sure.
Check that HALF_TYPE size + shift amount <= INTERM_TYPE size. (e.g., if the original value was char, the shift amount is at most 8 if we want to use short).
Try intermediate type  HALF_TYPE is not supported.
There are four possible cases: 1. OPRND is defined by a type promotion (in that case FIRST is TRUE, it's the first statement in the sequence) a. The original, HALF_TYPE, is not enough  we replace the promotion from HALF_TYPE to TYPE with a promotion to INTERM_TYPE. b. HALF_TYPE is sufficient, OPRND is set as the RHS of the original promotion. 2. OPRND is defined by a pattern statement we created. a. Its type is not sufficient for the operation, we create a new stmt: a type conversion for OPRND from HALF_TYPE to INTERM_TYPE. We store this statement in NEW_DEF_STMT, and it is later put in STMT_VINFO_PATTERN_DEF_SEQ of the pattern statement for STMT. b. OPRND is good to use in the new statement.
Replace the original type conversion HALF_TYPE>TYPE with HALF_TYPE>INTERM_TYPE.
Check if the already created pattern stmt is what we need.
Create NEW_OPRND = (INTERM_TYPE) OPRND.
Retrieve the operand before the type promotion.
Create a type conversion HALF_TYPE>INTERM_TYPE.
Otherwise, OPRND is already set.
void vect_pattern_recog  (  ) 
Function vect_pattern_recog Input: LOOP_VINFO  a struct_loop_info of a loop in which we want to look for computation idioms. Output  for each computation idiom that is detected we create a new stmt that provides the same functionality and that can be vectorized. We also record some information in the struct_stmt_info of the relevant stmts, as explained below: At the entry to this function we have the following stmts, with the following initial value in the STMT_VINFO fields: stmt in_pattern_p related_stmt vec_stmt S1: a_i = ....    S2: a_2 = ..use(a_i)..    S3: a_1 = ..use(a_2)..    S4: a_0 = ..use(a_1)..    S5: ... = ..use(a_0)..    Say the sequence {S1,S2,S3,S4} was detected as a pattern that can be represented by a single stmt. We then:  create a new stmt S6 equivalent to the pattern (the stmt is not inserted into the code)  fill in the STMT_VINFO fields as follows: in_pattern_p related_stmt vec_stmt S1: a_i = ....    S2: a_2 = ..use(a_i)..    S3: a_1 = ..use(a_2)..    S4: a_0 = ..use(a_1).. true S6  '> S6: a_new = ....  S4  S5: ... = ..use(a_0)..    (the last stmt in the pattern (S4) and the new pattern stmt (S6) point to each other through the RELATED_STMT field). S6 will be marked as relevant in vect_mark_stmts_to_be_vectorized instead of S4 because it will replace all its uses. Stmts {S1,S2,S3} will remain irrelevant unless used by stmts other than S4. If vectorization succeeds, vect_transform_stmt will skip over {S1,S2,S3} (because they are marked as irrelevant). It will vectorize S6, and record a pointer to the new vector stmt VS6 from S6 (as usual). S4 will be skipped, and S5 will be vectorized as usual: in_pattern_p related_stmt vec_stmt S1: a_i = ....    S2: a_2 = ..use(a_i)..    S3: a_1 = ..use(a_2)..    > VS6: va_new = ....    S4: a_0 = ..use(a_1).. true S6 VS6 '> S6: a_new = ....  S4 VS6 > VS5: ... = ..vuse(va_new)..    S5: ... = ..use(a_0)..    DCE could then get rid of {S1,S2,S3,S4,S5} (if their defs are not used elsewhere), and we'll end up with: VS6: va_new = .... VS5: ... = ..vuse(va_new).. In case of more than one pattern statements, e.g., widenmult with intermediate type: S1 a_t = ; S2 a_T = (TYPE) a_t; '> S3: a_it = (interm_type) a_t; S4 prod_T = a_T * CONST; '> S5: prod_T' = a_it w* CONST; there may be other users of a_T outside the pattern. In that case S2 will be marked as relevant (as well as S3), and both S2 and S3 will be analyzed and vectorized. The vector stmt VS2 will be recorded in S2, and VS3 will be recorded in S3.
Scan through the loop stmts, applying the pattern recognition functions starting at each stmt visited:
Scan over all generic vect_recog_xxx_pattern functions.

static 
Function vect_pattern_recog_1 Input: PATTERN_RECOG_FUNC: A pointer to a function that detects a certain computation pattern. STMT: A stmt from which the pattern search should start. If PATTERN_RECOG_FUNC successfully detected the pattern, it creates an expression that computes the same functionality and can be used to replace the sequence of stmts that are involved in the pattern. Output: This function checks if the expression returned by PATTERN_RECOG_FUNC is supported in vector form by the target. We use 'TYPE_IN' to obtain the relevant vector type. If 'TYPE_IN' is already a vector type, then this indicates that target support had already been checked by PATTERN_RECOG_FUNC. If 'TYPE_OUT' is also returned by PATTERN_RECOG_FUNC, we check that it fits to the available target pattern. This function also does some bookkeeping, as explained in the documentation for vect_recog_pattern.
No need to check target support (already checked by the pattern recognition function).
Check target support
Found a vectorizable pattern.
Mark the stmts that are involved in the pattern.
Patterns cannot be vectorized using SLP, because they change the order of computation.
It is possible that additional pattern stmts are created and inserted in STMTS_TO_REPLACE. We create a stmt_info for each of them, and mark the relevant statements.
References dump_enabled_p(), dump_printf_loc(), gsi_end_p(), gsi_next(), gsi_start_bb(), gsi_stmt(), loop::num_nodes, si, vect_location, vect_vect_recog_func_ptrs, and vinfo_for_stmt().

static 
Function vect_recog_bool_pattern Try to find pattern like following: bool a_b, b_b, c_b, d_b, e_b; TYPE f_T; loop: S1 a_b = x1 CMP1 y1; S2 b_b = x2 CMP2 y2; S3 c_b = a_b & b_b; S4 d_b = x3 CMP3 y3; S5 e_b = c_b  d_b; S6 f_T = (TYPE) e_b; where type 'TYPE' is an integral type. Input: * LAST_STMT: A stmt at the end from which the pattern search begins, i.e. cast of a bool to an integer type. Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the pattern. Assuming size of TYPE is the same as size of all comparisons (otherwise some casts would be added where needed), the above sequence we create related pattern stmts: S1' a_T = x1 CMP1 y1 ? 1 : 0; S3' c_T = x2 CMP2 y2 ? a_T : 0; S4' d_T = x3 CMP3 y3 ? 1 : 0; S5' e_T = c_T  d_T; S6' f_T = e_T; Instead of the above S3' we could emit: S2' b_T = x2 CMP2 y2 ? 1 : 0; S3' c_T = a_T  b_T; but the above is more efficient.

static 
Detect a signed division by a constant that wouldn't be otherwise vectorized: type a_t, b_t; S1 a_t = b_t / N; where type 'type' is an integral type and N is a constant. Similarly handle modulo by a constant: S4 a_t = b_t % N; Input/Output: * STMTS: Contains a stmt from which the pattern search begins, i.e. the division stmt. S1 is replaced by if N is a power of two constant and type is signed: S3 y_t = b_t < 0 ? N  1 : 0; S2 x_t = b_t + y_t; S1' a_t = x_t >> log2 (N); S4 is replaced if N is a power of two constant and type is signed by (where *_T temporaries have unsigned type): S9 y_T = b_t < 0 ? 1U : 0U; S8 z_T = y_T >> (sizeof (type_t) * CHAR_BIT  log2 (N)); S7 z_t = (type) z_T; S6 w_t = b_t + z_t; S5 x_t = w_t & (N  1); S4' a_t = x_t  z_t; Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the division S1 or modulo S4 stmt.
If the target can handle vectorized division or modulo natively, don't attempt to optimize this.
Pattern detected.
FIXME: Can transform this into oprnd0 >= oprnd1 ? 1 : 0.
Find a suitable multiplier and right shift count instead of multiplying with D.
If the suggested multiplier is more than SIZE bits, we can do better for even divisors, using an initial right shift.
t1 = oprnd0 h* ml; t2 = oprnd0  t1; t3 = t2 >> 1; t4 = t1 + t3; q = t4 >> (post_shift  1);
t1 = oprnd0 >> pre_shift; t2 = t1 h* ml; q = t2 >> post_shift;
Give up for 1.
Since d might be INT_MIN, we have to cast to unsigned HOST_WIDE_INT before negating to avoid undefined signed overflow.
n rem d = n rem d
This case is not handled correctly below.
t1 = oprnd0 h* ml;
t2 = t1 + oprnd0;
t3 = t2 >> post_shift;
q = t3;
t4 = oprnd0 >> (prec  1); or if we know from VRP that oprnd0 >= 0 t4 = 0; or if we know from VRP that oprnd0 < 0 t4 = 1;
q = t3  t4; or q = t4  t3;
We divided. Now finish by: t1 = q * oprnd1; r = oprnd0  t1;
Pattern detected.

static 
Function vect_recog_dot_prod_pattern Try to find the following pattern: type x_t, y_t; TYPE1 prod; TYPE2 sum = init; loop: sum_0 = phi <init, sum_1> S1 x_t = ... S2 y_t = ... S3 x_T = (TYPE1) x_t; S4 y_T = (TYPE1) y_t; S5 prod = x_T * y_T; [S6 prod = (TYPE2) prod; #optional] S7 sum_1 = prod + sum_0; where 'TYPE1' is exactly double the size of type 'type', and 'TYPE2' is the same size of 'TYPE1' or bigger. This is a special case of a reduction computation. Input: * STMTS: Contains a stmt from which the pattern search begins. In the example, when this function is called with S7, the pattern {S3,S4,S5,S6,S7} will be detected. Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the sequence of stmts that constitute the pattern. In this case it will be: WIDEN_DOT_PRODUCT <x_t, y_t, sum_0> Note: The dotprod idiom is a widening reduction pattern that is vectorized without preserving all the intermediate results. It produces only N/2 (widened) results (by summing up pairs of intermediate results) rather than all N results. Therefore, we cannot allow this pattern when we want to get all the results and in the correct order (as is the case when this computation is in an innerloop nested in an outerloop that us being vectorized).
Look for the following pattern DX = (TYPE1) X; DY = (TYPE1) Y; DPROD = DX * DY; DDPROD = (TYPE2) DPROD; sum_1 = DDPROD + sum_0; In which  DX is double the size of X  DY is double the size of Y  DX, DY, DPROD all have the same type  sum is the same size of DPROD or bigger  sum has been recognized as a reduction variable. This is equivalent to: DPROD = X w* Y; #widen mult sum_1 = DPROD w+ sum_0; #widen summation or DPROD = X w* Y; #widen mult sum_1 = DPROD + sum_0; #summation
Starting from LAST_STMT, follow the defs of its uses in search of the above pattern.
Has been detected as wideningsummation?
So far so good. Since last_stmt was detected as a (summation) reduction, we know that oprnd1 is the reduction variable (defined by a loopheader phi), and oprnd0 is an ssaname defined by a stmt in the loop body. Left to check that oprnd0 is defined by a (widen_)mult_expr
It could not be the dot_prod pattern if the stmt is outside the loop.
FORNOW. Can continue analyzing the defuse chain when this stmt in a phi inside the loop (in case we are analyzing an outerloop).
Has been detected as a widening multiplication?
Pattern detected. Create a stmt to be used to replace the pattern:
We don't allow changing the order of the computation in the innerloop when doing outerloop vectorization.

static 
Function vect_recog_mixed_size_cond_pattern Try to find the following pattern: type x_t, y_t; TYPE a_T, b_T, c_T; loop: S1 a_T = x_t CMP y_t ? b_T : c_T; where type 'TYPE' is an integral type which has different size from 'type'. b_T and c_T are either constants (and if 'TYPE' is wider than 'type', the constants need to fit into an integer type with the same width as 'type') or results of conversion from 'type'. Input: * LAST_STMT: A stmt from which the pattern search begins. Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the pattern. Additionally a def_stmt is added. a_it = x_t CMP y_t ? b_it : c_it; a_T = (TYPE) a_it;

static 
Try to find a statement or a sequence of statements that can be performed on a smaller type: type x_t; TYPE x_T, res0_T, res1_T; loop: S1 x_t = *p; S2 x_T = (TYPE) x_t; S3 res0_T = op (x_T, C0); S4 res1_T = op (res0_T, C1); S5 ... = () res1_T;  type demotion where type 'TYPE' is at least double the size of type 'type', C0 and C1 are constants. Check if S3 and S4 can be done on a smaller type than 'TYPE', it can either be 'type' or some intermediate type. For now, we expect S5 to be a type demotion operation. We also check that S3 and S4 have only one use.
STMT can be performed on a smaller type. Check its uses.
Create pattern statement for STMT.
We want to collect all the statements for which we create pattern statetments, except for the case when the last statement in the sequence doesn't have a corresponding pattern statement. In such case we associate the last pattern statement with the last statement in the sequence. Therefore, we only add the original statement to the list if we know that it is not the last.
We got a sequence. We expect it to end with a type demotion operation. Otherwise, we quit (for now). There are three possible cases: the conversion is to NEW_TYPE (we don't do anything), the conversion is to a type bigger than NEW_TYPE and/or the signedness of USE_TYPE and NEW_TYPE differs (we create a new conversion statement).
Support only type demotion or signedess change.
Check that NEW_TYPE is not bigger than the conversion result.
Create NEW_TYPE>USE_TYPE conversion.
We created a pattern statement for the last statement in the sequence, so we don't need to associate it with the pattern statement created for PREV_STMT. Therefore, we add PREV_STMT to the list in order to mark it later in vect_pattern_recog_1.
TODO: support general case, create a conversion to the correct type.
Pattern detected.

static 
@verbatim
Function vect_recog_pow_pattern
Try to find the following pattern:
x = POW (y, N);
with POW being one of pow, powf, powi, powif and N being either 2 or 0.5.
Input:
Output:
We now have a pow or powi builtin function call with a constant exponent.
Catch squaring.
Catch square root.
References gimple_build_assign_with_ops(), and vect_recog_temp_ssa_var().

static 
Detect a rotate pattern wouldn't be otherwise vectorized: type a_t, b_t, c_t; S0 a_t = b_t r<< c_t; Input/Output: * STMTS: Contains a stmt from which the pattern search begins, i.e. the shift/rotate stmt. The original stmt (S0) is replaced with a sequence: S1 d_t = c_t; S2 e_t = d_t & (B  1); S3 f_t = b_t << c_t; S4 g_t = b_t >> e_t; S0 a_t = f_t  g_t; where B is element bitsize of type. Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the rotate S0 stmt.
If vector/vector or vector/scalar rotate is supported by the target, don't do anything here.
If vector/vector or vector/scalar shifts aren't supported by the target, don't do anything here either.
Pattern detected.
Pattern supported. Create a stmt to be used to replace the pattern.
References optab_for_tree_code(), optab_handler(), optab_scalar, and vect_internal_def.

static 
Helper to return a new temporary for pattern of TYPE for STMT. If STMT is NULL, the caller must set SSA_NAME_DEF_STMT for the returned SSA var.
References last_stmt(), and vinfo_for_stmt().
Referenced by check_bool_pattern(), and vect_recog_pow_pattern().

static 
Detect a vector by vector shift pattern that wouldn't be otherwise vectorized: type a_t; TYPE b_T, res_T; S1 a_t = ; S2 b_T = ; S3 res_T = b_T op a_t; where type 'TYPE' is a type with different size than 'type', and op is <<, >> or rotate. Also detect cases: type a_t; TYPE b_T, c_T, res_T; S0 c_T = ; S1 a_t = (type) c_T; S2 b_T = ; S3 res_T = b_T op a_t; Input/Output: * STMTS: Contains a stmt from which the pattern search begins, i.e. the shift/rotate stmt. The original stmt (S3) is replaced with a shift/rotate which has same type on both operands, in the second case just b_T op c_T, in the first case with added cast from a_t to c_T in STMT_VINFO_PATTERN_DEF_SEQ. Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the shift/rotate S3 stmt.
Pattern detected.
Pattern supported. Create a stmt to be used to replace the pattern.

static 
@verbatim
Function vect_recog_widen_mult_pattern
Try to find the following pattern:
type a_t, b_t; TYPE a_T, b_T, prod_T;
S1 a_t = ; S2 b_t = ; S3 a_T = (TYPE) a_t; S4 b_T = (TYPE) b_t; S5 prod_T = a_T * b_T;
where type 'TYPE' is at least double the size of type 'type'.
Also detect unsigned cases:
unsigned type a_t, b_t; unsigned TYPE u_prod_T; TYPE a_T, b_T, prod_T;
S1 a_t = ; S2 b_t = ; S3 a_T = (TYPE) a_t; S4 b_T = (TYPE) b_t; S5 prod_T = a_T * b_T; S6 u_prod_T = (unsigned TYPE) prod_T;
and multiplication by constants:
type a_t; TYPE a_T, prod_T;
S1 a_t = ; S3 a_T = (TYPE) a_t; S5 prod_T = a_T * CONST;
A special case of multiplication by constants is when 'TYPE' is 4 times bigger than 'type', but CONST fits an intermediate type 2 times smaller than 'TYPE'. In that case we create an additional pattern stmt for S3 to create a variable of the intermediate type, and perform widenmult on the intermediate type as well:
type a_t; interm_type a_it; TYPE a_T, prod_T, prod_T';
S1 a_t = ; S3 a_T = (TYPE) a_t; '> a_it = (interm_type) a_t; S5 prod_T = a_T * CONST; '> prod_T' = a_it w* CONST;
Input/Output:
Output:
Starting from LAST_STMT, follow the defs of its uses in search of the above pattern.
Check argument 0.
Check argument 1.
Handle unsigned case. Look for S6 u_prod_T = (unsigned TYPE) prod_T; Use unsigned TYPE as the type for WIDEN_MULT_EXPR.
Pattern detected.
Check target support
Pattern supported. Create a stmt to be used to replace the pattern:

static 
Detect widening shift pattern: type a_t; TYPE a_T, res_T; S1 a_t = ; S2 a_T = (TYPE) a_t; S3 res_T = a_T << CONST; where type 'TYPE' is at least double the size of type 'type'. Also detect cases where the shift result is immediately converted to another type 'result_type' that is no larger in size than 'TYPE'. In those cases we perform a widenshift that directly results in 'result_type', to avoid a possible overwidening situation: type a_t; TYPE a_T, res_T; result_type res_result; S1 a_t = ; S2 a_T = (TYPE) a_t; S3 res_T = a_T << CONST; S4 res_result = (result_type) res_T; '> res_result' = a_t w<< CONST; And a case when 'TYPE' is 4 times bigger than 'type'. In that case we create an additional pattern stmt for S2 to create a variable of an intermediate type, and perform widenshift on the intermediate type: type a_t; interm_type a_it; TYPE a_T, res_T, res_T'; S1 a_t = ; S2 a_T = (TYPE) a_t; '> a_it = (interm_type) a_t; S3 res_T = a_T << CONST; '> res_T' = a_it <<* CONST; Input/Output: * STMTS: Contains a stmt from which the pattern search begins. In case of unsigned widenshift, the original stmt (S3) is replaced with S4 in STMTS. When an intermediate type is used and a pattern statement is created for S2, we also put S2 here (before S3). Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the sequence of stmts that constitute the pattern. In this case it will be: WIDEN_LSHIFT_EXPR <a_t, CONST>.
Check operand 0: it has to be defined by a type promotion.
Check operand 1: has to be positive. We check that it fits the type in vect_handle_widen_op_by_const ().
Check for subsequent conversion to another type.
Check if this a widening operation.
Pattern detected.
Check target support.
Pattern supported. Create a stmt to be used to replace the pattern.

static 
@verbatim
Analysis Utilities for Loop Vectorization. Copyright (C) 20062013 Free Software Foundation, Inc. Contributed by Dorit Nuzman dorit @il. ibm.c om
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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Pattern recognition functions
Function vect_recog_widen_sum_pattern Try to find the following pattern: type x_t; TYPE x_T, sum = init; loop: sum_0 = phi <init, sum_1> S1 x_t = *p; S2 x_T = (TYPE) x_t; S3 sum_1 = x_T + sum_0; where type 'TYPE' is at least double the size of type 'type', i.e  we're summing elements of type 'type' into an accumulator of type 'TYPE'. This is a special case of a reduction computation. Input: * LAST_STMT: A stmt from which the pattern search begins. In the example, when this function is called with S3, the pattern {S2,S3} will be detected. Output: * TYPE_IN: The type of the input arguments to the pattern. * TYPE_OUT: The type of the output of this pattern. * Return value: A new stmt that will be used to replace the sequence of stmts that constitute the pattern. In this case it will be: WIDEN_SUM <x_t, sum_0> Note: The wideningsum idiom is a widening reduction pattern that is vectorized without preserving all the intermediate results. It produces only N/2 (widened) results (by summing up pairs of intermediate results) rather than all N results. Therefore, we cannot allow this pattern when we want to get all the results and in the correct order (as is the case when this computation is in an innerloop nested in an outerloop that us being vectorized).
Look for the following pattern DX = (TYPE) X; sum_1 = DX + sum_0; In which DX is at least double the size of X, and sum_1 has been recognized as a reduction variable.
Starting from LAST_STMT, follow the defs of its uses in search of the above pattern.
So far so good. Since last_stmt was detected as a (summation) reduction, we know that oprnd1 is the reduction variable (defined by a loopheader phi), and oprnd0 is an ssaname defined by a stmt in the loop body. Left to check that oprnd0 is defined by a cast from type 'type' to type 'TYPE'.
Pattern detected. Create a stmt to be used to replace the pattern:
We don't allow changing the order of the computation in the innerloop when doing outerloop vectorization.

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Check whether STMT2 is in the same loop or basic block as STMT1. Which of the two applies depends on whether we're currently doing loopbased or basicblockbased vectorization, as determined by the vinfo_for_stmt for STMT1 (which must be defined). If this returns true, vinfo_for_stmt for STMT2 is guaranteed to be defined as well.

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If the LHS of DEF_STMT has a single use, and that statement is in the same loop or basic block, return it.

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Referenced by vect_pattern_recog_1().