Each target machine types can have its own special options, starting with -m, to choose among various hardware models or configurations-for example, 68010 vs 68020, floating coprocessor or none. A single installed version of the compiler can compile for any model or configuration, according to the options specified.
Some configurations of the compiler also support additional special options, usually for compatibility with other compilers on the same platform.
These options are defined for AArch64 implementations:
Generate code for the specified data model. Permissible values are ilp32 for SysV-like data model where int, long int and pointer are 32-bit, and lp64 for SysV-like data model where int is 32-bit, but long int and pointer are 64-bit.
The default depends on the specific target configuration. Note that the LP64 and ILP32 ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.
Generate big-endian code. This is the default when GCC is configured for an aarch64_be-*-* target.
Generate code which uses only the general registers.
Generate little-endian code. This is the default when GCC is configured for an aarch64-*-* but not an aarch64_be-*-* target.
Generate code for the tiny code model. The program and its statically defined symbols must be within 1GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This model is not fully implemented and mostly treated as small.
Generate code for the small code model. The program and its statically defined symbols must be within 4GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This is the default code model.
Generate code for the large code model. This makes no assumptions about addresses and sizes of sections. Pointers are 64 bits. Programs can be statically linked only.
Do not assume that unaligned memory references are handled by the system.
Omit or keep the frame pointer in leaf functions. The former behaviour is the default.
Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is the default.
Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables.
Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This involves inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions.
Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. This erratum workaround is made at link time and this will only pass the corresponding flag to the linker.
Specify the name of the target architecture, optionally suffixed by one or more feature modifiers. This option has the form -march=``arch``{+[no]``feature`}*`, where the only permissible value for arch is armv8-a. The permissible values for feature are documented in the sub-section below. Additionally on native AArch64 GNU/Linux systems the value native is available. This option causes the compiler to pick the architecture of the host system. If the compiler is unable to recognize the architecture of the host system this option has no effect.
Where conflicting feature modifiers are specified, the right-most feature is used.
GCC uses this name to determine what kind of instructions it can emit when generating assembly code.
Where -march is specified without either of -mtune or -mcpu also being specified, the code is tuned to perform well across a range of target processors implementing the target architecture.
Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: generic, cortex-a53, cortex-a57, cortex-a72, exynos-m1, thunderx, xgene1.
Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible values for this option are: cortex-a57.cortex-a53, cortex-a72.cortex-a53.
Additionally on native AArch64 GNU/Linux systems the value native is available. This option causes the compiler to pick the architecture of and tune the performance of the code for the processor of the host system. If the compiler is unable to recognize the processor of the host system this option has no effect.
Where none of -mtune=, -mcpu= or -march= are specified, the code is tuned to perform well across a range of target processors.
This option cannot be suffixed by feature modifiers.
Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This option has the form -mcpu=``cpu``{+[no]``feature`}*`, where the permissible values for cpu are the same as those available for -mtune. Additionally on native AArch64 GNU/Linux systems the value native is available. This option causes the compiler to tune the performance of the code for the processor of the host system. If the compiler is unable to recognize the processor of the host system this option has no effect.
The permissible values for feature are documented in the sub-section below.
Where conflicting feature modifiers are specified, the right-most feature is used.
GCC uses this name to determine what kind of instructions it can emit when generating assembly code (as if by -march) and to determine the target processor for which to tune for performance (as if by -mtune). Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option.
-march and -mcpu Feature Modifiers .. index:: -march feature modifiers
Feature modifiers used with -march and -mcpu can be one the following:
These -m options are defined for Adapteva Epiphany:
Don’t allocate any register in the range r32...``r63``. That allows code to run on hardware variants that lack these registers.
Preferrentially allocate registers that allow short instruction generation. This can result in increased instruction count, so this may either reduce or increase overall code size.
Set the cost of branches to roughly num ‘simple’ instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases.
Enable the generation of conditional moves.
Emit num NOPs before every other generated instruction.
For single-precision floating-point comparisons, emit an fsub instruction and test the flags. This is faster than a software comparison, but can get incorrect results in the presence of NaNs, or when two different small numbers are compared such that their difference is calculated as zero. The default is -msoft-cmpsf, which uses slower, but IEEE-compliant, software comparisons.
Set the offset between the top of the stack and the stack pointer. E.g., a value of 8 means that the eight bytes in the range sp+0...sp+7 can be used by leaf functions without stack allocation. Values other than 8 or 16 are untested and unlikely to work. Note also that this option changes the ABI; compiling a program with a different stack offset than the libraries have been compiled with generally does not work. This option can be useful if you want to evaluate if a different stack offset would give you better code, but to actually use a different stack offset to build working programs, it is recommended to configure the toolchain with the appropriate --with-stack-offset=``num`` option.
Make the scheduler assume that the rounding mode has been set to truncating. The default is -mround-nearest.
If not otherwise specified by an attribute, assume all calls might be beyond the offset range of the b / bl instructions, and therefore load the function address into a register before performing a (otherwise direct) call. This is the default.
If not otherwise specified by an attribute, assume all direct calls are in the range of the b / bl instructions, so use these instructions for direct calls. The default is -mlong-calls.
Assume addresses can be loaded as 16-bit unsigned values. This does not apply to function addresses for which -mlong-calls semantics are in effect.
Set the prevailing mode of the floating-point unit. This determines the floating-point mode that is provided and expected at function call and return time. Making this mode match the mode you predominantly need at function start can make your programs smaller and faster by avoiding unnecessary mode switches.
mode can be set to one the following values:
This is the mode used to perform integer calculations in the FPU, e.g. integer multiply, or integer multiply-and-accumulate.
The default is -mfp-mode=caller
Code generation tweaks that disable, respectively, splitting of 32-bit loads, generation of post-increment addresses, and generation of post-modify addresses. The defaults are msplit-lohi, -mpost-inc, and -mpost-modify.
Change the preferred SIMD mode to SImode. The default is -mvect-double, which uses DImode as preferred SIMD mode.
The maximum alignment for SIMD vector mode types. num may be 4 or 8. The default is 8. Note that this is an ABI change, even though many library function interfaces are unaffected if they don’t use SIMD vector modes in places that affect size and/or alignment of relevant types.
Split vector moves into single word moves before reload. In theory this can give better register allocation, but so far the reverse seems to be generally the case.
Specify a register to hold the constant -1, which makes loading small negative constants and certain bitmasks faster. Allowable values for reg are r43 and r63, which specify use of that register as a fixed register, and none, which means that no register is used for this purpose. The default is -m1reg-none.
The following options control the architecture variant for which code is being compiled:
Generate instructions supported by barrel shifter. This is the default unless -mcpu=ARC601 is in effect.
Set architecture type, register usage, and instruction scheduling parameters for cpu. There are also shortcut alias options available for backward compatibility and convenience. Supported values for cpu are
FPX: Generate Double Precision FPX instructions, tuned for the compact implementation.
FPX: Generate Double Precision FPX instructions, tuned for the fast implementation.
Disable LR and SR instructions from using FPX extension aux registers.
Generate Extended arithmetic instructions. Currently only divaw, adds, subs, and sat16 are supported. This is always enabled for -mcpu=ARC700.
Do not generate mpy instructions for ARC700.
Generate 32x16 bit multiply and mac instructions.
Generate mul64 and mulu64 instructions. Only valid for -mcpu=ARC600.
Generate norm instruction. This is the default if -mcpu=ARC700 is in effect.
FPX: Generate Single Precision FPX instructions, tuned for the compact implementation.
FPX: Generate Single Precision FPX instructions, tuned for the fast implementation.
Enable generation of ARC SIMD instructions via target-specific builtins. Only valid for -mcpu=ARC700.
This option ignored; it is provided for compatibility purposes only. Software floating point code is emitted by default, and this default can overridden by FPX options; mspfp, mspfp-compact, or mspfp-fast for single precision, and mdpfp, mdpfp-compact, or mdpfp-fast for double precision.
Generate swap instructions.
The following options are passed through to the assembler, and also define preprocessor macro symbols.
Passed down to the assembler to enable the DSP Pack A extensions. Also sets the preprocessor symbol __Xdsp_packa.
Passed down to the assembler to enable the dual viterbi butterfly extension. Also sets the preprocessor symbol __Xdvbf.
Passed down to the assembler to enable the Locked Load/Store Conditional extension. Also sets the preprocessor symbol __Xlock.
Passed down to the assembler. Also sets the preprocessor symbol __Xxmac_d16.
Passed down to the assembler. Also sets the preprocessor symbol __Xxmac_24.
Passed down to the assembler to enable the 64-bit Time-Stamp Counter extension instruction. Also sets the preprocessor symbol __Xrtsc.
Passed down to the assembler to enable the swap byte ordering extension instruction. Also sets the preprocessor symbol __Xswape.
Passed down to the assembler to enable dual and single operand instructions for telephony. Also sets the preprocessor symbol __Xtelephony.
Passed down to the assembler to enable the XY Memory extension. Also sets the preprocessor symbol __Xxy.
The following options control how the assembly code is annotated:
Annotate assembler instructions with estimated addresses.
Explain what alignment considerations lead to the decision to make an instruction short or long.
The following options are passed through to the linker:
Passed through to the linker, to specify use of the arclinux emulation. This option is enabled by default in tool chains built for arc-linux-uclibc and arceb-linux-uclibc targets when profiling is not requested.
Passed through to the linker, to specify use of the arclinux_prof emulation. This option is enabled by default in tool chains built for arc-linux-uclibc and arceb-linux-uclibc targets when profiling is requested.
The following options control the semantics of generated code:
Enable generation of call frame information for epilogues.
Disable generation of call frame information for epilogues.
Generate call insns as register indirect calls, thus providing access to the full 32-bit address range.
Don’t use less than 25 bit addressing range for calls, which is the offset available for an unconditional branch-and-link instruction. Conditional execution of function calls is suppressed, to allow use of the 25-bit range, rather than the 21-bit range with conditional branch-and-link. This is the default for tool chains built for arc-linux-uclibc and arceb-linux-uclibc targets.
Do not generate sdata references. This is the default for tool chains built for arc-linux-uclibc and arceb-linux-uclibc targets.
Instrument with mcount calls as used in UCB code. I.e. do the counting in the callee, not the caller. By default ARC instrumentation counts in the caller.
Use ordinarily cached memory accesses for volatile references. This is the default.
Enable cache bypass for volatile references.
The following options fine tune code generation:
Do alignment optimizations for call instructions.
Enable the use of pre/post modify with register displacement.
Enable bbit peephole2.
This option disables a target-specific pass in arc_reorg to generate BRcc instructions. It has no effect on BRcc generation driven by the combiner pass.
Use pc-relative switch case tables - this enables case table shortening. This is the default for -Os.
Disable ARCompact specific pass to generate conditional execution instructions. Due to delay slot scheduling and interactions between operand numbers, literal sizes, instruction lengths, and the support for conditional execution, the target-independent pass to generate conditional execution is often lacking, so the ARC port has kept a special pass around that tries to find more conditional execution generating opportunities after register allocation, branch shortening, and delay slot scheduling have been done. This pass generally, but not always, improves performance and code size, at the cost of extra compilation time, which is why there is an option to switch it off. If you have a problem with call instructions exceeding their allowable offset range because they are conditionalized, you should consider using -mmedium-calls instead.
Enable pre-reload use of the cbranchsi pattern.
Expand adddi3 and subdi3 at rtl generation time into add.f, adc etc.
Enable the use of indexed loads. This can be problematic because some optimizers then assume that indexed stores exist, which is not the case.
Enable Local Register Allocation. This is still experimental for ARC, so by default the compiler uses standard reload (i.e. -mno-lra).
Don’t indicate any priority for target registers.
Indicate target register priority for r0..r3 / r12..r15.
Reduce target regsiter priority for r0..r3 / r12..r15.
When optimizing for size (using -Os), prologues and epilogues that have to save or restore a large number of registers are often shortened by using call to a special function in libgcc; this is referred to as a millicode call. As these calls can pose performance issues, and/or cause linking issues when linking in a nonstandard way, this option is provided to turn off millicode call generation.
Tweak register allocation to help 16-bit instruction generation. This generally has the effect of decreasing the average instruction size while increasing the instruction count.
Enable Rcq constraint handling - most short code generation depends on this. This is the default.
Enable Rcw constraint handling - ccfsm condexec mostly depends on this. This is the default.
Fine-tune size optimization with regards to instruction lengths and alignment. The recognized values for level are:
In addition, optional data alignment is dropped, and the option Os is enabled.
This defaults to 3 when -Os is in effect. Otherwise,
the behavior when this is not set is equivalent to level 1.
Set instruction scheduling parameters for cpu, overriding any implied by -mcpu=.
Supported values for cpu are
Cost to assume for a multiply instruction, with 4 being equal to a normal instruction.
Set probability threshold for unaligning branches. When tuning for ARC700 and optimizing for speed, branches without filled delay slot are preferably emitted unaligned and long, unless profiling indicates that the probability for the branch to be taken is below probability. See Data File Relocation to Support Cross-Profiling. The default is (REG_BR_PROB_BASE/2), i.e. 5000.
The following options are maintained for backward compatibility, but are now deprecated and will be removed in a future release:
Obsolete FPX.
Compile code for big endian targets. Use of these options is now deprecated. Users wanting big-endian code, should use the arceb-elf32 and arceb-linux-uclibc targets when building the tool chain, for which big-endian is the default.
Compile code for little endian targets. Use of these options is now deprecated. Users wanting little-endian code should use the arc-elf32 and arc-linux-uclibc targets when building the tool chain, for which little-endian is the default.
Replaced by -mbarrel-shifter.
Replaced by -mdpfp-compact.
Replaced by -mdpfp-fast.
Replaced by -mdsp-packa.
Replaced by -mspfp-compact.
Replaced by -mspfp-fast.
Values arc600, arc601, arc700 and arc700-xmac for cpu are replaced by ARC600, ARC601, ARC700 and ARC700-xmac respectively
Replaced by -mmultcost.
These -m options are defined for the ARM port:
Generate code for the specified ABI. Permissible values are: apcs-gnu, atpcs, aapcs, aapcs-linux and iwmmxt.
Generate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if this is not strictly necessary for correct execution of the code. Specifying -fomit-frame-pointer with this option causes the stack frames not to be generated for leaf functions. The default is -mno-apcs-frame. This option is deprecated.
This is a synonym for -mapcs-frame and is deprecated.
@c not currently implemented @item -mapcs-stack-check @opindex mapcs-stack-check Generate code to check the amount of stack space available upon entry to every function (that actually uses some stack space). If there is insufficient space available then either the function @code{__rt_stkovf_split_small} or @code{__rt_stkovf_split_big} is called, depending upon the amount of stack space required. The runtime system is required to provide these functions. The default is @option{-mno-apcs-stack-check}, since this produces smaller code.
@c not currently implemented @item -mapcs-float @opindex mapcs-float Pass floating-point arguments using the floating-point registers. This is one of the variants of the APCS@. This option is recommended if the target hardware has a floating-point unit or if a lot of floating-point arithmetic is going to be performed by the code. The default is @option{-mno-apcs-float}, since the size of integer-only code is slightly increased if @option{-mapcs-float} is used.
@c not currently implemented @item -mapcs-reentrant @opindex mapcs-reentrant Generate reentrant, position-independent code. The default is @option{-mno-apcs-reentrant}.
Generate code that supports calling between the ARM and Thumb instruction sets. Without this option, on pre-v5 architectures, the two instruction sets cannot be reliably used inside one program. The default is -mno-thumb-interwork, since slightly larger code is generated when -mthumb-interwork is specified. In AAPCS configurations this option is meaningless.
Prevent the reordering of instructions in the function prologue, or the merging of those instruction with the instructions in the function’s body. This means that all functions start with a recognizable set of instructions (or in fact one of a choice from a small set of different function prologues), and this information can be used to locate the start of functions inside an executable piece of code. The default is -msched-prolog.
Specifies which floating-point ABI to use. Permissible values are: soft, softfp and hard.
Specifying soft causes GCC to generate output containing library calls for floating-point operations. softfp allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions. hard allows generation of floating-point instructions and uses FPU-specific calling conventions.
The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.
Generate code for a processor running in little-endian mode. This is the default for all standard configurations.
Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor.
This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the -mcpu= option. Permissible names are: armv2, armv2a, armv3, armv3m, armv4, armv4t, armv5, armv5t, armv5e, armv5te, armv6, armv6j, armv6t2, armv6z, armv6zk, armv6-m, armv7, armv7-a, armv7-r, armv7-m, armv7e-m, armv7ve, armv8-a, armv8-a+crc, iwmmxt, iwmmxt2, ep9312.
-march=armv7ve is the armv7-a architecture with virtualization extensions.
-march=armv8-a+crc enables code generation for the ARMv8-A architecture together with the optional CRC32 extensions.
-march=native causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
This option specifies the name of the target ARM processor for which GCC should tune the performance of the code. For some ARM implementations better performance can be obtained by using this option. Permissible names are: arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, arm700i, arm710, arm710c, arm7100, arm720, arm7500, arm7500fe, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm740t, strongarm, strongarm110, strongarm1100, strongarm1110, arm8, arm810, arm9, arm9e, arm920, arm920t, arm922t, arm946e-s, arm966e-s, arm968e-s, arm926ej-s, arm940t, arm9tdmi, arm10tdmi, arm1020t, arm1026ej-s, arm10e, arm1020e, arm1022e, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1156t2-s, arm1156t2f-s, arm1176jz-s, arm1176jzf-s, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a53, cortex-a57, cortex-a72, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-m7, cortex-m4, cortex-m3, cortex-m1, cortex-m0, cortex-m0plus, cortex-m1.small-multiply, cortex-m0.small-multiply, cortex-m0plus.small-multiply, exynos-m1, marvell-pj4, xscale, iwmmxt, iwmmxt2, ep9312, fa526, fa626, fa606te, fa626te, fmp626, fa726te, xgene1.
Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: cortex-a15.cortex-a7, cortex-a57.cortex-a53, cortex-a72.cortex-a53.
-mtune=generic-``arch`` specifies that GCC should tune the performance for a blend of processors within architecture arch. The aim is to generate code that run well on the current most popular processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go.
-mtune=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified by -march) and the ARM processor type for which to tune for performance (as if specified by -mtune). Where this option is used in conjunction with -march or -mtune, those options take precedence over the appropriate part of this option.
Permissible names for this option are the same as those for -mtune.
-mcpu=generic-``arch`` is also permissible, and is equivalent to -march=``arch` -mtune=generic-arch`. See -mtune for more information.
-mcpu=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
This specifies what floating-point hardware (or hardware emulation) is available on the target. Permissible names are: vfp, vfpv3, vfpv3-fp16, vfpv3-d16, vfpv3-d16-fp16, vfpv3xd, vfpv3xd-fp16, neon, neon-fp16, vfpv4, vfpv4-d16, fpv4-sp-d16, neon-vfpv4, fpv5-d16, fpv5-sp-d16, fp-armv8, neon-fp-armv8, and crypto-neon-fp-armv8.
If -msoft-float is specified this specifies the format of floating-point values.
If the selected floating-point hardware includes the NEON extension (e.g. -mfpu`=:samp:`neon), note that floating-point operations are not generated by GCC’s auto-vectorization pass unless -funsafe-math-optimizations is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision.
Specify the format of the __fp16 half-precision floating-point type. Permissible names are none, ieee, and alternative; the default is none, in which case the __fp16 type is not defined. See Half-Precision Floating Point, for more information.
The sizes of all structures and unions are rounded up to a multiple of the number of bits set by this option. Permissible values are 8, 32 and 64. The default value varies for different toolchains. For the COFF targeted toolchain the default value is 8. A value of 64 is only allowed if the underlying ABI supports it.
Specifying a larger number can produce faster, more efficient code, but can also increase the size of the program. Different values are potentially incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions.
Generate a call to the function abort at the end of a noreturn function. It is executed if the function tries to return.
Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 64-megabyte addressing range of the offset-based version of subroutine call instruction.
Even if this switch is enabled, not all function calls are turned into long calls. The heuristic is that static functions, functions that have the short_call attribute, functions that are inside the scope of a #pragma no_long_calls directive, and functions whose definitions have already been compiled within the current compilation unit are not turned into long calls. The exceptions to this rule are that weak function definitions, functions with the long_call attribute or the section attribute, and functions that are within the scope of a #pragma long_calls directive are always turned into long calls.
This feature is not enabled by default. Specifying -mno-long-calls restores the default behavior, as does placing the function calls within the scope of a #pragma long_calls_off directive. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers.
Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins.
Specify the register to be used for PIC addressing. For standard PIC base case, the default is any suitable register determined by compiler. For single PIC base case, the default is R9 if target is EABI based or stack-checking is enabled, otherwise the default is R10.
Assume that each data segments are relative to text segment at load time. Therefore, it permits addressing data using PC-relative operations. This option is on by default for targets other than VxWorks RTP.
Write the name of each function into the text section, directly preceding the function prologue. The generated code is similar to this:
t0
.ascii "arm_poke_function_name", 0
.align
t1
.word 0xff000000 + (t1 - t0)
arm_poke_function_name
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
When performing a stack backtrace, code can inspect the value of pc stored at fp + 0. If the trace function then looks at location pc - 12 and the top 8 bits are set, then we know that there is a function name embedded immediately preceding this location and has length ((pc[-3]) & 0xff000000).
Select between generating code that executes in ARM and Thumb states. The default for most configurations is to generate code that executes in ARM state, but the default can be changed by configuring GCC with the --with-mode=```state` configure option.
Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions. (A leaf function is one that does not call any other functions.) The default is -mno-tpcs-frame.
Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions. (A leaf function is one that does not call any other functions.) The default is -mno-apcs-leaf-frame.
Gives all externally visible functions in the file being compiled an ARM instruction set header which switches to Thumb mode before executing the rest of the function. This allows these functions to be called from non-interworking code. This option is not valid in AAPCS configurations because interworking is enabled by default.
Allows calls via function pointers (including virtual functions) to execute correctly regardless of whether the target code has been compiled for interworking or not. There is a small overhead in the cost of executing a function pointer if this option is enabled. This option is not valid in AAPCS configurations because interworking is enabled by default.
Specify the access model for the thread local storage pointer. The valid models are soft, which generates calls to __aeabi_read_tp, cp15, which fetches the thread pointer from cp15 directly (supported in the arm6k architecture), and auto, which uses the best available method for the selected processor. The default setting is auto.
Specify the dialect to use for accessing thread local storage. Two ``dialect``s are supported-gnu and gnu2. The gnu dialect selects the original GNU scheme for supporting local and global dynamic TLS models. The gnu2 dialect selects the GNU descriptor scheme, which provides better performance for shared libraries. The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker and library support. Initial and local exec TLS models are unaffected by this option and always use the original scheme.
Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). This is enabled by default on targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when -fpic or -fPIC is specified.
Some Cortex-M3 cores can cause data corruption when ldrd instructions with overlapping destination and base registers are used. This option avoids generating these instructions. This option is enabled by default when -mcpu=cortex-m3 is specified.
Enables (or disables) reading and writing of 16- and 32- bit values from addresses that are not 16- or 32- bit aligned. By default unaligned access is disabled for all pre-ARMv6 and all ARMv6-M architectures, and enabled for all other architectures. If unaligned access is not enabled then words in packed data structures are accessed a byte at a time.
The ARM attribute Tag_CPU_unaligned_access is set in the generated object file to either true or false, depending upon the setting of this option. If unaligned access is enabled then the preprocessor symbol __ARM_FEATURE_UNALIGNED is also defined.
Enables using Neon to handle scalar 64-bits operations. This is disabled by default since the cost of moving data from core registers to Neon is high.
Assume loading data from flash is slower than fetching instruction. Therefore literal load is minimized for better performance. This option is only supported when compiling for ARMv7 M-profile and off by default.
Assume inline assembler is using unified asm syntax. The default is currently off which implies divided syntax. Currently this option is available only for Thumb1 and has no effect on ARM state and Thumb2. However, this may change in future releases of GCC. Divided syntax should be considered deprecated.
Restricts generation of IT blocks to conform to the rules of ARMv8. IT blocks can only contain a single 16-bit instruction from a select set of instructions. This option is on by default for ARMv8 Thumb mode.
Print CPU tuning information as comment in assembler file. This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code. This option is disabled by default.
These options are defined for AVR implementations:
Specify Atmel AVR instruction set architectures (ISA) or MCU type.
The default for this option is avr2.
GCC supports the following AVR devices and ISAs:
‘Classic’ devices with up to 8 KiB of program memory.
mcu = attiny22, attiny26, at90c8534, at90s2313, at90s2323, at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515, at90s8535.
‘Classic’ devices with up to 8 KiB of program memory and with the MOVW instruction.
mcu = ata5272, ata6616c, attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, attiny25, attiny261, attiny261a, attiny43u, attiny4313, attiny44, attiny44a, attiny441, attiny45, attiny461, attiny461a, attiny48, attiny828, attiny84, attiny84a, attiny841, attiny85, attiny861, attiny861a, attiny87, attiny88, at86rf401.
‘Classic’ devices with 16 KiB up to 64 KiB of program memory.
mcu = at43usb355, at76c711.
‘Classic’ devices with 128 KiB of program memory.
mcu = atmega103, at43usb320.
‘Classic’ devices with 16 KiB up to 64 KiB of program memory and with the MOVW instruction.
mcu = ata5505, ata6617c, ata664251, atmega16u2, atmega32u2, atmega8u2, attiny1634, attiny167, at90usb162, at90usb82.
‘Enhanced’ devices with up to 8 KiB of program memory.
mcu = ata6285, ata6286, ata6289, ata6612c, atmega48, atmega48a, atmega48p, atmega48pa, atmega8, atmega8a, atmega8hva, atmega8515, atmega8535, atmega88, atmega88a, atmega88p, atmega88pa, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81.
‘Enhanced’ devices with 16 KiB up to 64 KiB of program memory.
mcu = ata5702m322, ata5782, ata5790, ata5790n, ata5795, ata5831, ata6613c, ata6614q, atmega16, atmega16a, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, atmega16m1, atmega16u4, atmega161, atmega162, atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega32a, atmega32c1, atmega32hvb, atmega32hvbrevb, atmega32m1, atmega32u4, atmega32u6, atmega323, atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, atmega64c1, atmega64hve, atmega64hve2, atmega64m1, atmega64rfr2, atmega640, atmega644, atmega644a, atmega644p, atmega644pa, atmega644rfr2, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000.
‘Enhanced’ devices with 128 KiB of program memory.
mcu = atmega128, atmega128a, atmega128rfa1, atmega128rfr2, atmega1280, atmega1281, atmega1284, atmega1284p, atmega1284rfr2, at90can128, at90usb1286, at90usb1287.
‘Enhanced’ devices with 3-byte PC, i.e. with more than 128 KiB of program memory.
mcu = atmega256rfr2, atmega2560, atmega2561, atmega2564rfr2.
‘XMEGA’ devices with more than 8 KiB and up to 64 KiB of program memory.
mcu = atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16e5, atxmega32a4, atxmega32a4u, atxmega32c3, atxmega32c4, atxmega32d3, atxmega32d4, atxmega32e5, atxmega8e5.
‘XMEGA’ devices with more than 64 KiB and up to 128 KiB of program memory.
mcu = atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4.
‘XMEGA’ devices with more than 64 KiB and up to 128 KiB of program memory and more than 64 KiB of RAM.
mcu = atxmega64a1, atxmega64a1u.
‘XMEGA’ devices with more than 128 KiB of program memory.
mcu = atxmega128a3, atxmega128a3u, atxmega128b1, atxmega128b3, atxmega128c3, atxmega128d3, atxmega128d4, atxmega192a3, atxmega192a3u, atxmega192c3, atxmega192d3, atxmega256a3, atxmega256a3b, atxmega256a3bu, atxmega256a3u, atxmega256c3, atxmega256d3, atxmega384c3, atxmega384d3.
‘XMEGA’ devices with more than 128 KiB of program memory and more than 64 KiB of RAM.
mcu = atxmega128a1, atxmega128a1u, atxmega128a4u.
‘TINY’ Tiny core devices with 512 B up to 4 KiB of program memory.
mcu = attiny10, attiny20, attiny4, attiny40, attiny5, attiny9.
This ISA is implemented by the minimal AVR core and supported for assembler only.
mcu = attiny11, attiny12, attiny15, attiny28, at90s1200.
Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments once in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards.
Popping the arguments after the function call can be expensive on AVR so that accumulating the stack space might lead to smaller executables because arguments need not to be removed from the stack after such a function call.
This option can lead to reduced code size for functions that perform several calls to functions that get their arguments on the stack like calls to printf-like functions.
Set the branch costs for conditional branch instructions to cost. Reasonable values for cost are small, non-negative integers. The default branch cost is 0.
Functions prologues/epilogues are expanded as calls to appropriate subroutines. Code size is smaller.
Assume int to be 8-bit integer. This affects the sizes of all types: a char is 1 byte, an int is 1 byte, a long is 2 bytes, and long long is 4 bytes. Please note that this option does not conform to the C standards, but it results in smaller code size.
Assume that the flash memory has a size of num times 64 KiB.
Generated code is not compatible with hardware interrupts. Code size is smaller.
Try to replace CALL resp. JMP instruction by the shorter RCALL resp. RJMP instruction if applicable. Setting -mrelax just adds the --mlink-relax option to the assembler’s command line and the --relax option to the linker’s command line.
Jump relaxing is performed by the linker because jump offsets are not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code.
Relaxing must be turned on if linker stubs are needed, see the section on EIND and linker stubs below.
Assume that the device supports the Read-Modify-Write instructions XCH, LAC, LAS and LAT.
Treat the stack pointer register as an 8-bit register, i.e. assume the high byte of the stack pointer is zero. In general, you don’t need to set this option by hand.
This option is used internally by the compiler to select and build multilibs for architectures avr2 and avr25. These architectures mix devices with and without SPH. For any setting other than -mmcu=avr2 or -mmcu=avr25 the compiler driver adds or removes this option from the compiler proper’s command line, because the compiler then knows if the device or architecture has an 8-bit stack pointer and thus no SPH register or not.
Use address register X in a way proposed by the hardware. This means that X is only used in indirect, post-increment or pre-decrement addressing.
Without this option, the X register may be used in the same way as Y or Z which then is emulated by additional instructions. For example, loading a value with X+const addressing with a small non-negative const < 64 to a register Rn is performed as
adiw r26, const ; X += const
ld ``Rn``, X ; ``Rn`` = *X
sbiw r26, const ; X -= const
Only change the lower 8 bits of the stack pointer.
Don’t link against AVR-LibC’s device specific library libdev.a.
Warn about conversions between address spaces in the case where the resulting address space is not contained in the incoming address space.
EIND and Devices with More Than 128 Ki Bytes of Flash .. index:: EIND
Pointers in the implementation are 16 bits wide. The address of a function or label is represented as word address so that indirect jumps and calls can target any code address in the range of 64 Ki words.
In order to facilitate indirect jump on devices with more than 128 Ki bytes of program memory space, there is a special function register called EIND that serves as most significant part of the target address when EICALL or EIJMP instructions are used.
Indirect jumps and calls on these devices are handled as follows by the compiler and are subject to some limitations:
The compiler never sets EIND.
The compiler uses EIND implicitely in EICALL/EIJMP instructions or might read EIND directly in order to emulate an indirect call/jump by means of a RET instruction.
The compiler assumes that EIND never changes during the startup code or during the application. In particular, EIND is not saved/restored in function or interrupt service routine prologue/epilogue.
For indirect calls to functions and computed goto, the linker generates stubs. Stubs are jump pads sometimes also called trampolines. Thus, the indirect call/jump jumps to such a stub. The stub contains a direct jump to the desired address.
Linker relaxation must be turned on so that the linker generates the stubs correctly in all situations. See the compiler option -mrelax and the linker option --relax. There are corner cases where the linker is supposed to generate stubs but aborts without relaxation and without a helpful error message.
The default linker script is arranged for code with EIND = 0. If code is supposed to work for a setup with EIND != 0, a custom linker script has to be used in order to place the sections whose name start with .trampolines into the segment where EIND points to.
The startup code from libgcc never sets EIND. Notice that startup code is a blend of code from libgcc and AVR-LibC. For the impact of AVR-LibC on EIND, see the http://nongnu.org/avr-libc/user-manual/AVR-LibC user manual.
It is legitimate for user-specific startup code to set up EIND early, for example by means of initialization code located in section .init3. Such code runs prior to general startup code that initializes RAM and calls constructors, but after the bit of startup code from AVR-LibC that sets EIND to the segment where the vector table is located.
#include <avr/io.h>
static void
__attribute__((section(".init3"),naked,used,no_instrument_function))
init3_set_eind (void)
{
__asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"
"out %i0,r24" :: "n" (&EIND) : "r24","memory");
}
The __trampolines_start symbol is defined in the linker script.
Stubs are generated automatically by the linker if the following two conditions are met:
The address of a label is taken by means of the gs modifier (short for generate stubs) like so:
LDI r24, lo8(gs(``func``))
LDI r25, hi8(gs(``func``))
The final location of that label is in a code segment outside the segment where the stubs are located.
The compiler emits such gs modifiers for code labels in the following situations:
Jumping to non-symbolic addresses like so is not supported:
int main (void)
{
/* Call function at word address 0x2 */
return ((int(*)(void)) 0x2)();
}
Instead, a stub has to be set up, i.e. the function has to be called through a symbol (func_4 in the example):
int main (void)
{
extern int func_4 (void);
/* Call function at byte address 0x4 */
return func_4();
}
and the application be linked with -Wl,--defsym,func_4=0x4. Alternatively, func_4 can be defined in the linker script.
Handling of the RAMPD, RAMPX, RAMPY and RAMPZ Special Function Registers .. index:: RAMPD
Some AVR devices support memories larger than the 64 KiB range that can be accessed with 16-bit pointers. To access memory locations outside this 64 KiB range, the contentent of a RAMP register is used as high part of the address: The X, Y, Z address register is concatenated with the RAMPX, RAMPY, RAMPZ special function register, respectively, to get a wide address. Similarly, RAMPD is used together with direct addressing.
GCC defines several built-in macros so that the user code can test for the presence or absence of features. Almost any of the following built-in macros are deduced from device capabilities and thus triggered by the -mmcu= command-line option.
For even more AVR-specific built-in macros see AVR Named Address Spaces and AVR Built-in Functions.
Build-in macro that resolves to a decimal number that identifies the architecture and depends on the -mmcu=``mcu`` option. Possible values are:
2, 25, 3, 31, 35, 4, 5, 51, 6
for mcu``=``avr2, avr25, avr3, avr31, avr35, avr4, avr5, avr51, avr6,
respectively and
100, 102, 104, 105, 106, 107
for mcu``=``avrtiny, avrxmega2, avrxmega4, avrxmega5, avrxmega6, avrxmega7, respectively. If mcu specifies a device, this built-in macro is set accordingly. For example, with -mmcu=atmega8 the macro is defined to 4.
Setting -mmcu=``device`` defines this built-in macro which reflects the device’s name. For example, -mmcu=atmega8 defines the built-in macro __AVR_ATmega8__, -mmcu=attiny261a defines __AVR_ATtiny261A__, etc.
The built-in macros’ names follow the scheme __AVR_``Device``__ where Device is the device name as from the AVR user manual. The difference between Device in the built-in macro and device in -mmcu=``device`` is that the latter is always lowercase.
If device is not a device but only a core architecture like avr51, this macro is not defined.
Setting -mmcu=``device`` defines this built-in macro to the device’s name. For example, with -mmcu=atmega8 the macro is defined to atmega8.
If device is not a device but only a core architecture like avr51, this macro is not defined.
Specifies the name of the target Blackfin processor. Currently, cpu can be one of bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf536, bf537, bf538, bf539, bf542, bf544, bf547, bf548, bf549, bf542m, bf544m, bf547m, bf548m, bf549m, bf561, bf592.
The optional sirevision specifies the silicon revision of the target Blackfin processor. Any workarounds available for the targeted silicon revision are enabled. If sirevision is none, no workarounds are enabled. If sirevision is any, all workarounds for the targeted processor are enabled. The __SILICON_REVISION__ macro is defined to two hexadecimal digits representing the major and minor numbers in the silicon revision. If sirevision is none, the __SILICON_REVISION__ is not defined. If sirevision is any, the __SILICON_REVISION__ is defined to be 0xffff. If this optional sirevision is not used, GCC assumes the latest known silicon revision of the targeted Blackfin processor.
GCC defines a preprocessor macro for the specified cpu. For the bfin-elf toolchain, this option causes the hardware BSP provided by libgloss to be linked in if -msim is not given.
Without this option, bf532 is used as the processor by default.
Note that support for bf561 is incomplete. For bf561, only the preprocessor macro is defined.
Specifies that the program will be run on the simulator. This causes the simulator BSP provided by libgloss to be linked in. This option has effect only for bfin-elf toolchain. Certain other options, such as -mid-shared-library and -mfdpic, imply -msim.
Don’t keep the frame pointer in a register for leaf functions. This avoids the instructions to save, set up and restore frame pointers and makes an extra register available in leaf functions. The option -fomit-frame-pointer removes the frame pointer for all functions, which might make debugging harder.
When enabled, the compiler ensures that the generated code does not contain speculative loads after jump instructions. If this option is used, __WORKAROUND_SPECULATIVE_LOADS is defined.
Don’t generate extra code to prevent speculative loads from occurring.
When enabled, the compiler ensures that the generated code does not contain CSYNC or SSYNC instructions too soon after conditional branches. If this option is used, __WORKAROUND_SPECULATIVE_SYNCS is defined.
Don’t generate extra code to prevent CSYNC or SSYNC instructions from occurring too soon after a conditional branch.
When enabled, the compiler is free to take advantage of the knowledge that the entire program fits into the low 64k of memory.
Assume that the program is arbitrarily large. This is the default.
Do stack checking using information placed into L1 scratchpad memory by the uClinux kernel.
Generate code that supports shared libraries via the library ID method. This allows for execute in place and shared libraries in an environment without virtual memory management. This option implies -fPIC. With a bfin-elf target, this option implies -msim.
Generate code that doesn’t assume ID-based shared libraries are being used. This is the default.
Generate code that supports shared libraries via the library ID method, but assumes that this library or executable won’t link against any other ID shared libraries. That allows the compiler to use faster code for jumps and calls.
Do not assume that the code being compiled won’t link against any ID shared libraries. Slower code is generated for jump and call insns.
Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library but is no more space- or time-efficient than omitting this option.
Generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute in place in an environment without virtual memory management by eliminating relocations against the text section.
Generate code that assumes that the data segment follows the text segment. This is the default.
Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 24-bit addressing range of the offset-based version of subroutine call instruction.
This feature is not enabled by default. Specifying -mno-long-calls restores the default behavior. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers.
Link with the fast floating-point library. This library relaxes some of the IEEE floating-point standard’s rules for checking inputs against Not-a-Number (NAN), in the interest of performance.
Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has no effect without -mfdpic.
Build a standalone application for multicore Blackfin processors. This option causes proper start files and link scripts supporting multicore to be used, and defines the macro __BFIN_MULTICORE. It can only be used with -mcpu=bf561[-``sirevision`]`.
This option can be used with -mcorea or -mcoreb, which selects the one-application-per-core programming model. Without -mcorea or -mcoreb, the single-application/dual-core programming model is used. In this model, the main function of Core B should be named as coreb_main.
If this option is not used, the single-core application programming model is used.
Build a standalone application for Core A of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core A, and the macro __BFIN_COREA is defined. This option can only be used in conjunction with -mmulticore.
Build a standalone application for Core B of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core B, and the macro __BFIN_COREB is defined. When this option is used, coreb_main should be used instead of main. This option can only be used in conjunction with -mmulticore.
Build a standalone application for SDRAM. Proper start files and link scripts are used to put the application into SDRAM, and the macro __BFIN_SDRAM is defined. The loader should initialize SDRAM before loading the application.
Assume that ICPLBs are enabled at run time. This has an effect on certain anomaly workarounds. For Linux targets, the default is to assume ICPLBs are enabled; for standalone applications the default is off.
This specifies the name of the target architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. Permissible names are: c62x, c64x, c64x+, c67x, c67x+, c674x.
Generate code for a big-endian target.
Generate code for a little-endian target. This is the default.
Choose startup files and linker script suitable for the simulator.
Put small global and static data in the .neardata section, which is pointed to by register B14. Put small uninitialized global and static data in the .bss section, which is adjacent to the .neardata section. Put small read-only data into the .rodata section. The corresponding sections used for large pieces of data are .fardata, .far and .const.
Put all data, not just small objects, into the sections reserved for small data, and use addressing relative to the B14 register to access them.
Make no use of the sections reserved for small data, and use absolute addresses to access all data. Put all initialized global and static data in the .fardata section, and all uninitialized data in the .far section. Put all constant data into the .const section.
These options are defined specifically for the CRIS ports.
Generate code for the specified architecture. The choices for architecture-type are v3, v8 and v10 for respectively ETRAX4, ETRAX100, and ETRAX100LX. Default is v0 except for cris-axis-linux-gnu, where the default is v10.
Tune to architecture-type everything applicable about the generated code, except for the ABI and the set of available instructions. The choices for architecture-type are the same as for -march=``architecture-type``.
Warn when the stack frame of a function exceeds n bytes.
The options -metrax4 and -metrax100 are synonyms for -march=v3 and -march=v8 respectively.
Work around a bug in the muls and mulu instructions for CPU models where it applies. This option is active by default.
Enable CRIS-specific verbose debug-related information in the assembly code. This option also has the effect of turning off the #NO_APP formatted-code indicator to the assembler at the beginning of the assembly file.
Do not use condition-code results from previous instruction; always emit compare and test instructions before use of condition codes.
Do not emit instructions with side effects in addressing modes other than post-increment.
These options (no- options) arrange (eliminate arrangements) for the stack frame, individual data and constants to be aligned for the maximum single data access size for the chosen CPU model. The default is to arrange for 32-bit alignment. ABI details such as structure layout are not affected by these options.
Similar to the stack- data- and const-align options above, these options arrange for stack frame, writable data and constants to all be 32-bit, 16-bit or 8-bit aligned. The default is 32-bit alignment.
With -mno-prologue-epilogue, the normal function prologue and epilogue which set up the stack frame are omitted and no return instructions or return sequences are generated in the code. Use this option only together with visual inspection of the compiled code: no warnings or errors are generated when call-saved registers must be saved, or storage for local variables needs to be allocated.
With -fpic and -fPIC, don’t generate (do generate) instruction sequences that load addresses for functions from the PLT part of the GOT rather than (traditional on other architectures) calls to the PLT. The default is -mgotplt.
Legacy no-op option only recognized with the cris-axis-elf and cris-axis-linux-gnu targets.
Legacy no-op option only recognized with the cris-axis-linux-gnu target.
This option, recognized for the cris-axis-elf, arranges to link with input-output functions from a simulator library. Code, initialized data and zero-initialized data are allocated consecutively.
These options are defined specifically for the CR16 ports.
Enable the use of multiply-accumulate instructions. Disabled by default.
Generate code for CR16C or CR16C+ architecture. CR16C+ architecture is default.
Links the library libsim.a which is in compatible with simulator. Applicable to ELF compiler only.
Choose integer type as 32-bit wide.
Generates sbit/cbit instructions for bit manipulations.
Choose a data model. The choices for model are near, far or medium. medium is default. However, far is not valid with -mcr16c, as the CR16C architecture does not support the far data model.
These options are defined for all architectures running the Darwin operating system.
FSF GCC on Darwin does not create ‘fat’ object files; it creates an object file for the single architecture that GCC was built to target. Apple’s GCC on Darwin does create ‘fat’ files if multiple -arch options are used; it does so by running the compiler or linker multiple times and joining the results together with lipo.
The subtype of the file created (like ppc7400 or ppc970 or i686) is determined by the flags that specify the ISA that GCC is targeting, like -mcpu or -march. The -force_cpusubtype_ALL option can be used to override this.
The Darwin tools vary in their behavior when presented with an ISA mismatch. The assembler, as, only permits instructions to be used that are valid for the subtype of the file it is generating, so you cannot put 64-bit instructions in a ppc750 object file. The linker for shared libraries, /usr/bin/libtool, fails and prints an error if asked to create a shared library with a less restrictive subtype than its input files (for instance, trying to put a ppc970 object file in a ppc7400 library). The linker for executables, ld, quietly gives the executable the most restrictive subtype of any of its input files.
Add the framework directory dir to the head of the list of directories to be searched for header files. These directories are interleaved with those specified by -I options and are scanned in a left-to-right order.
A framework directory is a directory with frameworks in it. A framework is a directory with a Headers and/or PrivateHeaders directory contained directly in it that ends in .framework. The name of a framework is the name of this directory excluding the .framework. Headers associated with the framework are found in one of those two directories, with Headers being searched first. A subframework is a framework directory that is in a framework’s Frameworks directory. Includes of subframework headers can only appear in a header of a framework that contains the subframework, or in a sibling subframework header. Two subframeworks are siblings if they occur in the same framework. A subframework should not have the same name as a framework; a warning is issued if this is violated. Currently a subframework cannot have subframeworks; in the future, the mechanism may be extended to support this. The standard frameworks can be found in /System/Library/Frameworks and /Library/Frameworks. An example include looks like #include <Framework/header.h>, where Framework denotes the name of the framework and header.h is found in the PrivateHeaders or Headers directory.
Like -F except the directory is a treated as a system directory. The main difference between this -iframework and -F is that with -iframework the compiler does not warn about constructs contained within header files found via dir. This option is valid only for the C family of languages.
Emit debugging information for symbols that are used. For stabs debugging format, this enables -feliminate-unused-debug-symbols. This is by default ON.
Emit debugging information for all symbols and types.
The earliest version of MacOS X that this executable will run on is version. Typical values of version include 10.1, 10.2, and 10.3.9.
If the compiler was built to use the system’s headers by default, then the default for this option is the system version on which the compiler is running, otherwise the default is to make choices that are compatible with as many systems and code bases as possible.
Enable kernel development mode. The -mkernel option sets -static, -fno-common, -fno-use-cxa-atexit, -fno-exceptions, -fno-non-call-exceptions, -fapple-kext, -fno-weak and -fno-rtti where applicable. This mode also sets -mno-altivec, -msoft-float, -fno-builtin and -mlong-branch for PowerPC targets.
Override the defaults for bool so that sizeof(bool)==1. By default sizeof(bool) is 4 when compiling for Darwin/PowerPC and 1 when compiling for Darwin/x86, so this option has no effect on x86.
Warning: The -mone-byte-bool switch causes GCC to generate code that is not binary compatible with code generated without that switch. Using this switch may require recompiling all other modules in a program, including system libraries. Use this switch to conform to a non-default data model.
Generate code suitable for fast turnaround development, such as to allow GDB to dynamically load .o files into already-running programs. -findirect-data and -ffix-and-continue are provided for backwards compatibility.
Loads all members of static archive libraries. See man ld(1) for more information.
Cause the errors having to do with files that have the wrong architecture to be fatal.
Causes the output file to be marked such that the dynamic linker will bind all undefined references when the file is loaded or launched.
Produce a Mach-o bundle format file. See man ld(1) for more information.
This option specifies the executable that will load the build output file being linked. See man ld(1) for more information.
When passed this option, GCC produces a dynamic library instead of an executable when linking, using the Darwin libtool command.
This causes GCC’s output file to have the ALL subtype, instead of one controlled by the -mcpu or -march option.
These options are passed to the Darwin linker. The Darwin linker man page describes them in detail.
These -m options are defined for the DEC Alpha implementations:
Use (do not use) the hardware floating-point instructions for floating-point operations. When -msoft-float is specified, functions in libgcc.a are used to perform floating-point operations. Unless they are replaced by routines that emulate the floating-point operations, or compiled in such a way as to call such emulations routines, these routines issue floating-point operations. If you are compiling for an Alpha without floating-point operations, you must ensure that the library is built so as not to call them.
Note that Alpha implementations without floating-point operations are required to have floating-point registers.
Generate code that uses (does not use) the floating-point register set. -mno-fp-regs implies -msoft-float. If the floating-point register set is not used, floating-point operands are passed in integer registers as if they were integers and floating-point results are passed in $0 instead of $f0. This is a non-standard calling sequence, so any function with a floating-point argument or return value called by code compiled with -mno-fp-regs must also be compiled with that option.
A typical use of this option is building a kernel that does not use, and hence need not save and restore, any floating-point registers.
The Alpha architecture implements floating-point hardware optimized for maximum performance. It is mostly compliant with the IEEE floating-point standard. However, for full compliance, software assistance is required. This option generates code fully IEEE-compliant code except that the inexact-flag is not maintained (see below). If this option is turned on, the preprocessor macro _IEEE_FP is defined during compilation. The resulting code is less efficient but is able to correctly support denormalized numbers and exceptional IEEE values such as not-a-number and plus/minus infinity. Other Alpha compilers call this option -ieee_with_no_inexact.
This is like -mieee except the generated code also maintains the IEEE inexact-flag. Turning on this option causes the generated code to implement fully-compliant IEEE math. In addition to _IEEE_FP, _IEEE_FP_EXACT is defined as a preprocessor macro. On some Alpha implementations the resulting code may execute significantly slower than the code generated by default. Since there is very little code that depends on the inexact-flag, you should normally not specify this option. Other Alpha compilers call this option -ieee_with_inexact.
This option controls what floating-point related traps are enabled. Other Alpha compilers call this option -fptm ``trap-mode``. The trap mode can be set to one of four values:
Selects the IEEE rounding mode. Other Alpha compilers call this option -fprm ``rounding-mode``. The rounding-mode can be one of:
In the Alpha architecture, floating-point traps are imprecise. This means without software assistance it is impossible to recover from a floating trap and program execution normally needs to be terminated. GCC can generate code that can assist operating system trap handlers in determining the exact location that caused a floating-point trap. Depending on the requirements of an application, different levels of precisions can be selected:
Instruction precision. The trap handler can determine the exact instruction that caused a floating-point exception.
Other Alpha compilers provide the equivalent options called
-scope_safe and -resumption_safe.
This option marks the generated code as IEEE conformant. You must not use this option unless you also specify -mtrap-precision=i and either -mfp-trap-mode=su or -mfp-trap-mode=sui. Its only effect is to emit the line .eflag 48 in the function prologue of the generated assembly file.
Normally GCC examines a 32- or 64-bit integer constant to see if it can construct it from smaller constants in two or three instructions. If it cannot, it outputs the constant as a literal and generates code to load it from the data segment at run time.
Use this option to require GCC to construct all integer constants using code, even if it takes more instructions (the maximum is six).
You typically use this option to build a shared library dynamic loader. Itself a shared library, it must relocate itself in memory before it can find the variables and constants in its own data segment.
Indicate whether GCC should generate code to use the optional BWX, CIX, FIX and MAX instruction sets. The default is to use the instruction sets supported by the CPU type specified via -mcpu= option or that of the CPU on which GCC was built if none is specified.
Generate code that uses (does not use) VAX F and G floating-point arithmetic instead of IEEE single and double precision.
Older Alpha assemblers provided no way to generate symbol relocations except via assembler macros. Use of these macros does not allow optimal instruction scheduling. GNU binutils as of version 2.12 supports a new syntax that allows the compiler to explicitly mark which relocations should apply to which instructions. This option is mostly useful for debugging, as GCC detects the capabilities of the assembler when it is built and sets the default accordingly.
When -mexplicit-relocs is in effect, static data is accessed via gp-relative relocations. When -msmall-data is used, objects 8 bytes long or smaller are placed in a small data area (the .sdata and .sbss sections) and are accessed via 16-bit relocations off of the $gp register. This limits the size of the small data area to 64KB, but allows the variables to be directly accessed via a single instruction.
The default is -mlarge-data. With this option the data area is limited to just below 2GB. Programs that require more than 2GB of data must use malloc or mmap to allocate the data in the heap instead of in the program’s data segment.
When generating code for shared libraries, -fpic implies -msmall-data and -fPIC implies -mlarge-data.
When -msmall-text is used, the compiler assumes that the code of the entire program (or shared library) fits in 4MB, and is thus reachable with a branch instruction. When -msmall-data is used, the compiler can assume that all local symbols share the same $gp value, and thus reduce the number of instructions required for a function call from 4 to 1.
The default is -mlarge-text.
Set the instruction set and instruction scheduling parameters for machine type cpu_type. You can specify either the EV style name or the corresponding chip number. GCC supports scheduling parameters for the EV4, EV5 and EV6 family of processors and chooses the default values for the instruction set from the processor you specify. If you do not specify a processor type, GCC defaults to the processor on which the compiler was built.
Supported values for cpu_type are
Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
Native toolchains also support the value native,
which selects the best architecture option for the host processor. -mcpu=native has no effect if GCC does not recognize the processor.
Set only the instruction scheduling parameters for machine type cpu_type. The instruction set is not changed.
Native toolchains also support the value native, which selects the best architecture option for the host processor. -mtune=native has no effect if GCC does not recognize the processor.
Sets the latency the scheduler should assume for typical memory references as seen by the application. This number is highly dependent on the memory access patterns used by the application and the size of the external cache on the machine.
Valid options for time are
These options are defined specifically for the FR30 port.
Use the small address space model. This can produce smaller code, but it does assume that all symbolic values and addresses fit into a 20-bit range.
Assume that runtime support has been provided and so there is no need to include the simulator library (libsim.a) on the linker command line.
Only use the first 32 general-purpose registers.
Use all 64 general-purpose registers.
Use only the first 32 floating-point registers.
Use all 64 floating-point registers.
Use hardware instructions for floating-point operations.
Use library routines for floating-point operations.
Dynamically allocate condition code registers.
Do not try to dynamically allocate condition code registers, only use icc0 and fcc0.
Change ABI to use double word insns.
Do not use double word instructions.
Use floating-point double instructions.
Do not use floating-point double instructions.
Use media instructions.
Do not use media instructions.
Use multiply and add/subtract instructions.
Do not use multiply and add/subtract instructions.
Select the FDPIC ABI, which uses function descriptors to represent pointers to functions. Without any PIC/PIE-related options, it implies -fPIE. With -fpic or -fpie, it assumes GOT entries and small data are within a 12-bit range from the GOT base address; with -fPIC or -fPIE, GOT offsets are computed with 32 bits. With a bfin-elf target, this option implies -msim.
Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has no effect without -mfdpic. It’s enabled by default if optimizing for speed and compiling for shared libraries (i.e., -fPIC or -fpic), or when an optimization option such as -O3 or above is present in the command line.
Assume a large TLS segment when generating thread-local code.
Do not assume a large TLS segment when generating thread-local code.
Enable the use of GPREL relocations in the FDPIC ABI for data that is known to be in read-only sections. It’s enabled by default, except for -fpic or -fpie: even though it may help make the global offset table smaller, it trades 1 instruction for 4. With -fPIC or -fPIE, it trades 3 instructions for 4, one of which may be shared by multiple symbols, and it avoids the need for a GOT entry for the referenced symbol, so it’s more likely to be a win. If it is not, -mno-gprel-ro can be used to disable it.
Link with the (library, not FD) pic libraries. It’s implied by -mlibrary-pic, as well as by -fPIC and -fpic without -mfdpic. You should never have to use it explicitly.
Follow the EABI requirement of always creating a frame pointer whenever a stack frame is allocated. This option is enabled by default and can be disabled with -mno-linked-fp.
Use indirect addressing to call functions outside the current compilation unit. This allows the functions to be placed anywhere within the 32-bit address space.
Try to align labels to an 8-byte boundary by inserting NOPs into the previous packet. This option only has an effect when VLIW packing is enabled. It doesn’t create new packets; it merely adds NOPs to existing ones.
Generate position-independent EABI code.
Use only the first four media accumulator registers.
Use all eight media accumulator registers.
Pack VLIW instructions.
Do not pack VLIW instructions.
Do not mark ABI switches in e_flags.
Enable the use of conditional-move instructions (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Disable the use of conditional-move instructions.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Enable the use of conditional set instructions (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Disable the use of conditional set instructions.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Enable the use of conditional execution (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Disable the use of conditional execution.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Run a pass to pack branches into VLIW instructions (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Do not run a pass to pack branches into VLIW instructions.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Enable optimization of && and || in conditional execution (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Disable optimization of && and || in conditional execution.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Enable nested conditional execution optimizations (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
Disable nested conditional execution optimizations.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
This switch removes redundant membar instructions from the compiler-generated code. It is enabled by default.
This switch disables the automatic removal of redundant membar instructions from the generated code.
Cause gas to print out tomcat statistics.
Select the processor type for which to generate code. Possible values are frv, fr550, tomcat, fr500, fr450, fr405, fr400, fr300 and simple.
These -m options are defined for GNU/Linux targets:
Use the GNU C library. This is the default except on *-*-linux-*uclibc*, *-*-linux-*musl* and *-*-linux-*android* targets.
Use uClibc C library. This is the default on *-*-linux-*uclibc* targets.
Use the musl C library. This is the default on *-*-linux-*musl* targets.
Use Bionic C library. This is the default on *-*-linux-*android* targets.
Compile code compatible with Android platform. This is the default on *-*-linux-*android* targets.
When compiling, this option enables -mbionic, -fPIC, -fno-exceptions and -fno-rtti by default. When linking, this option makes the GCC driver pass Android-specific options to the linker. Finally, this option causes the preprocessor macro __ANDROID__ to be defined.
These -m options are defined for the H8/300 implementations:
Shorten some address references at link time, when possible; uses the linker option -relax. See h8-300, for a fuller description.
Generate code for the H8/300H.
Generate code for the H8S.
Generate code for the H8S and H8/300H in the normal mode. This switch must be used either with -mh or -ms.
Extended registers are stored on stack before execution of function with monitor attribute. Default option is -mexr. This option is valid only for H8S targets.
Extended registers are not stored on stack before execution of function with monitor attribute. Default option is -mno-exr. This option is valid only for H8S targets.
Make int data 32 bits by default.
On the H8/300H and H8S, use the same alignment rules as for the H8/300. The default for the H8/300H and H8S is to align longs and floats on 4-byte boundaries. -malign-300 causes them to be aligned on 2-byte boundaries. This option has no effect on the H8/300.
These -m options are defined for the HPPA family of computers:
Generate code for the specified architecture. The choices for architecture-type are 1.0 for PA 1.0, 1.1 for PA 1.1, and 2.0 for PA 2.0 processors. Refer to /usr/lib/sched.models on an HP-UX system to determine the proper architecture option for your machine. Code compiled for lower numbered architectures runs on higher numbered architectures, but not the other way around.
Synonyms for -march=1.0, -march=1.1, and -march=2.0 respectively.
This option is ignored and provided for compatibility purposes only.
Prevent floating-point registers from being used in any manner. This is necessary for compiling kernels that perform lazy context switching of floating-point registers. If you use this option and attempt to perform floating-point operations, the compiler aborts.
Prevent the compiler from using indexing address modes. This avoids some rather obscure problems when compiling MIG generated code under MACH.
Generate code that assumes the target has no space registers. This allows GCC to generate faster indirect calls and use unscaled index address modes.
Such code is suitable for level 0 PA systems and kernels.
Generate code that assumes calls never cross space boundaries. This allows GCC to emit code that performs faster indirect calls.
This option does not work in the presence of shared libraries or nested functions.
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
Generate 3-instruction load and store sequences as sometimes required by the HP-UX 10 linker. This is equivalent to the +k option to the HP compilers.
Use the portable calling conventions proposed by HP for ELF systems.
Enable the use of assembler directives only GAS understands.
Schedule code according to the constraints for the machine type cpu-type. The choices for cpu-type are 700 7100, 7100LC, 7200, 7300 and 8000. Refer to /usr/lib/sched.models on an HP-UX system to determine the proper scheduling option for your machine. The default scheduling is 8000.
Enable the optimization pass in the HP-UX linker. Note this makes symbolic debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 linkers in which they give bogus error messages when linking some programs.
Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all HPPA targets. Normally the facilities of the machine’s usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation.
-msoft-float changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile libgcc.a, the library that comes with GCC, with -msoft-float in order for this to work.
Generate the predefine, _SIO, for server IO. The default is -mwsio. This generates the predefines, __hp9000s700, __hp9000s700__ and _WSIO, for workstation IO. These options are available under HP-UX and HI-UX.
Use options specific to GNU ld. This passes -shared to ld when building a shared library. It is the default when GCC is configured, explicitly or implicitly, with the GNU linker. This option does not affect which ld is called; it only changes what parameters are passed to that ld. The ld that is called is determined by the --with-ld configure option, GCC’s program search path, and finally by the user’s PATH. The linker used by GCC can be printed using which `gcc -print-prog-name=ld`. This option is only available on the 64-bit HP-UX GCC, i.e. configured with hppa*64*-*-hpux*.
Use options specific to HP ld. This passes -b to ld when building a shared library and passes +Accept TypeMismatch to ld on all links. It is the default when GCC is configured, explicitly or implicitly, with the HP linker. This option does not affect which ld is called; it only changes what parameters are passed to that ld. The ld that is called is determined by the --with-ld configure option, GCC’s program search path, and finally by the user’s PATH. The linker used by GCC can be printed using which `gcc -print-prog-name=ld`. This option is only available on the 64-bit HP-UX GCC, i.e. configured with hppa*64*-*-hpux*.
Generate code that uses long call sequences. This ensures that a call is always able to reach linker generated stubs. The default is to generate long calls only when the distance from the call site to the beginning of the function or translation unit, as the case may be, exceeds a predefined limit set by the branch type being used. The limits for normal calls are 7,600,000 and 240,000 bytes, respectively for the PA 2.0 and PA 1.X architectures. Sibcalls are always limited at 240,000 bytes.
Distances are measured from the beginning of functions when using the -ffunction-sections option, or when using the -mgas and -mno-portable-runtime options together under HP-UX with the SOM linker.
It is normally not desirable to use this option as it degrades performance. However, it may be useful in large applications, particularly when partial linking is used to build the application.
The types of long calls used depends on the capabilities of the assembler and linker, and the type of code being generated. The impact on systems that support long absolute calls, and long pic symbol-difference or pc-relative calls should be relatively small. However, an indirect call is used on 32-bit ELF systems in pic code and it is quite long.
Generate compiler predefines and select a startfile for the specified UNIX standard. The choices for unix-std are 93, 95 and 98. 93 is supported on all HP-UX versions. 95 is available on HP-UX 10.10 and later. 98 is available on HP-UX 11.11 and later. The default values are 93 for HP-UX 10.00, 95 for HP-UX 10.10 though to 11.00, and 98 for HP-UX 11.11 and later.
-munix=93 provides the same predefines as GCC 3.3 and 3.4. -munix=95 provides additional predefines for XOPEN_UNIX and _XOPEN_SOURCE_EXTENDED, and the startfile unix95.o. -munix=98 provides additional predefines for _XOPEN_UNIX, _XOPEN_SOURCE_EXTENDED, _INCLUDE__STDC_A1_SOURCE and _INCLUDE_XOPEN_SOURCE_500, and the startfile unix98.o.
It is important to note that this option changes the interfaces for various library routines. It also affects the operational behavior of the C library. Thus, extreme care is needed in using this option.
Library code that is intended to operate with more than one UNIX standard must test, set and restore the variable __xpg4_extended_mask as appropriate. Most GNU software doesn’t provide this capability.
Suppress the generation of link options to search libdld.sl when the -static option is specified on HP-UX 10 and later.
The HP-UX implementation of setlocale in libc has a dependency on libdld.sl. There isn’t an archive version of libdld.sl. Thus, when the -static option is specified, special link options are needed to resolve this dependency.
On HP-UX 10 and later, the GCC driver adds the necessary options to link with libdld.sl when the -static option is specified. This causes the resulting binary to be dynamic. On the 64-bit port, the linkers generate dynamic binaries by default in any case. The -nolibdld option can be used to prevent the GCC driver from adding these link options.
Add support for multithreading with the dce thread library under HP-UX. This option sets flags for both the preprocessor and linker.
These are the -m options defined for the Intel IA-64 architecture.
Generate code for a big-endian target. This is the default for HP-UX.
Generate code for a little-endian target. This is the default for AIX5 and GNU/Linux.
Generate (or don’t) code for the GNU assembler. This is the default.
Generate (or don’t) code for the GNU linker. This is the default.
Generate code that does not use a global pointer register. The result is not position independent code, and violates the IA-64 ABI.
Generate (or don’t) a stop bit immediately before and after volatile asm statements.
Generate (or don’t) in, loc, and out register names for the stacked registers. This may make assembler output more readable.
Disable (or enable) optimizations that use the small data section. This may be useful for working around optimizer bugs.
Generate code that uses a single constant global pointer value. This is useful when compiling kernel code.
Generate code that is self-relocatable. This implies -mconstant-gp. This is useful when compiling firmware code.
Generate code for inline divides of floating-point values using the minimum latency algorithm.
Generate code for inline divides of floating-point values using the maximum throughput algorithm.
Do not generate inline code for divides of floating-point values.
Generate code for inline divides of integer values using the minimum latency algorithm.
Generate code for inline divides of integer values using the maximum throughput algorithm.
Do not generate inline code for divides of integer values.
Generate code for inline square roots using the minimum latency algorithm.
Generate code for inline square roots using the maximum throughput algorithm.
Do not generate inline code for sqrt.
Do (don’t) generate code that uses the fused multiply/add or multiply/subtract instructions. The default is to use these instructions.
Don’t (or do) generate assembler code for the DWARF 2 line number debugging info. This may be useful when not using the GNU assembler.
Allow stop bits to be placed earlier than immediately preceding the instruction that triggered the stop bit. This can improve instruction scheduling, but does not always do so.
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
Specify bit size of immediate TLS offsets. Valid values are 14, 22, and 64.
Tune the instruction scheduling for a particular CPU, Valid values are itanium, itanium1, merced, itanium2, and mckinley.
Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits. These are HP-UX specific flags.
(Dis/En)able data speculative scheduling before reload. This results in generation of ld.a instructions and the corresponding check instructions (ld.c / chk.a). The default is ‘disable’.
(En/Dis)able data speculative scheduling after reload. This results in generation of ld.a instructions and the corresponding check instructions (ld.c / chk.a). The default is ‘enable’.
(Dis/En)able control speculative scheduling. This feature is available only during region scheduling (i.e. before reload). This results in generation of the ld.s instructions and the corresponding check instructions chk.s. The default is ‘disable’.
(En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads before reload. This is effective only with -msched-br-data-spec enabled. The default is ‘enable’.
(En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads after reload. This is effective only with -msched-ar-data-spec enabled. The default is ‘enable’.
(En/Dis)able speculative scheduling of the instructions that are dependent on the control speculative loads. This is effective only with -msched-control-spec enabled. The default is ‘enable’.
If enabled, data-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the data speculation much more conservative. The default is ‘disable’.
If enabled, control-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the control speculation much more conservative. The default is ‘disable’.
If enabled, speculative dependencies are considered during computation of the instructions priorities. This makes the use of the speculation a bit more conservative. The default is ‘disable’.
Use a simple data speculation check. This option is on by default.
Use a simple check for control speculation. This option is on by default.
Place a stop bit after every cycle when scheduling. This option is on by default.
Assume that floating-point stores and loads are not likely to cause a conflict when placed into the same instruction group. This option is disabled by default.
Generate checks for control speculation in selective scheduling. This flag is disabled by default.
Limit on the number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same instruction group. Frequently useful to prevent cache bank conflicts. The default value is 1.
Makes the limit specified by msched-max-memory-insns a hard limit, disallowing more than that number in an instruction group. Otherwise, the limit is ‘soft’, meaning that non-memory operations are preferred when the limit is reached, but memory operations may still be scheduled.
These -m options are defined for the LatticeMico32 architecture:
Enable barrel-shift instructions.
Enable divide and modulus instructions.
Enable multiply instructions.
Enable sign extend instructions.
Enable user-defined instructions.
Select the CPU for which code is generated. name may be one of r8c for the R8C/Tiny series, m16c for the M16C (up to /60) series, m32cm for the M16C/80 series, or m32c for the M32C/80 series.
Specifies that the program will be run on the simulator. This causes an alternate runtime library to be linked in which supports, for example, file I/O. You must not use this option when generating programs that will run on real hardware; you must provide your own runtime library for whatever I/O functions are needed.
Specifies the number of memory-based pseudo-registers GCC uses during code generation. These pseudo-registers are used like real registers, so there is a tradeoff between GCC’s ability to fit the code into available registers, and the performance penalty of using memory instead of registers. Note that all modules in a program must be compiled with the same value for this option. Because of that, you must not use this option with GCC’s default runtime libraries.
These -m options are defined for Renesas M32R/D architectures:
Generate code for the M32R/2.
Generate code for the M32R/X.
Generate code for the M32R. This is the default.
Assume all objects live in the lower 16MB of memory (so that their addresses can be loaded with the ld24 instruction), and assume all subroutines are reachable with the bl instruction. This is the default.
The addressability of a particular object can be set with the model attribute.
Assume objects may be anywhere in the 32-bit address space (the compiler generates seth/add3 instructions to load their addresses), and assume all subroutines are reachable with the bl instruction.
Assume objects may be anywhere in the 32-bit address space (the compiler generates seth/add3 instructions to load their addresses), and assume subroutines may not be reachable with the bl instruction (the compiler generates the much slower seth/add3/jl instruction sequence).
Disable use of the small data area. Variables are put into one of .data, .bss, or .rodata (unless the section attribute has been specified). This is the default.
The small data area consists of sections .sdata and .sbss. Objects may be explicitly put in the small data area with the section attribute using one of these sections.
Put small global and static data in the small data area, but do not generate special code to reference them.
Put small global and static data in the small data area, and generate special instructions to reference them.
Put global and static objects less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS sections. The default value of num is 8. The -msdata option must be set to one of sdata or use for this option to have any effect.
All modules should be compiled with the same -G ``num`` value. Compiling with different values of num may or may not work; if it doesn’t the linker gives an error message-incorrect code is not generated.
Makes the M32R-specific code in the compiler display some statistics that might help in debugging programs.
Align all loops to a 32-byte boundary.
Do not enforce a 32-byte alignment for loops. This is the default.
Issue number instructions per cycle. number can only be 1 or 2.
number can only be 1 or 2. If it is 1 then branches are preferred over conditional code, if it is 2, then the opposite applies.
Specifies the trap number to use to flush the cache. The default is 12. Valid numbers are between 0 and 15 inclusive.
Specifies that the cache cannot be flushed by using a trap.
Specifies the name of the operating system function to call to flush the cache. The default is _flush_cache, but a function call is only used if a trap is not available.
Indicates that there is no OS function for flushing the cache.
These are the -m options defined for M680x0 and ColdFire processors. The default settings depend on which architecture was selected when the compiler was configured; the defaults for the most common choices are given below.
Generate code for a specific M680x0 or ColdFire instruction set architecture. Permissible values of arch for M680x0 architectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32. ColdFire architectures are selected according to Freescale’s ISA classification and the permissible values are: isaa, isaaplus, isab and isac.
GCC defines a macro __mcf``arch``__ whenever it is generating code for a ColdFire target. The arch in this macro is one of the -march arguments given above.
When used together, -march and -mtune select code that runs on a family of similar processors but that is optimized for a particular microarchitecture.
Generate code for a specific M680x0 or ColdFire processor. The M680x0 ``cpu``s are: 68000, 68010, 68020, 68030, 68040, 68060, 68302, 68332 and cpu32. The ColdFire ``cpu``s are given by the table below, which also classifies the CPUs into families:
| Family | -mcpu arguments |
|---|---|
| 51 | 51 51ac 51ag 51cn 51em 51je 51jf 51jg 51jm 51mm 51qe 51qm |
| 5206 | 5202 5204 5206 |
| 5206e | 5206e |
| 5208 | 5207 5208 |
| 5211a | 5210a 5211a |
| 5213 | 5211 5212 5213 |
| 5216 | 5214 5216 |
| 52235 | 52230 52231 52232 52233 52234 52235 |
| 5225 | 5224 5225 |
| 52259 | 52252 52254 52255 52256 52258 52259 |
| 5235 | 5232 5233 5234 5235 523x |
| 5249 | 5249 |
| 5250 | 5250 |
| 5271 | 5270 5271 |
| 5272 | 5272 |
| 5275 | 5274 5275 |
| 5282 | 5280 5281 5282 528x |
| 53017 | 53011 53012 53013 53014 53015 53016 53017 |
| 5307 | 5307 |
| 5329 | 5327 5328 5329 532x |
| 5373 | 5372 5373 537x |
| 5407 | 5407 |
| 5475 | 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485 |
-mcpu=``cpu`` overrides -march=``arch`` if arch is compatible with cpu. Other combinations of -mcpu and -march are rejected.
GCC defines the macro __mcf_cpu_``cpu`` when ColdFire target cpu is selected. It also defines __mcf_family_``family``, where the value of family is given by the table above.
Tune the code for a particular microarchitecture within the constraints set by -march and -mcpu. The M680x0 microarchitectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32. The ColdFire microarchitectures are: cfv1, cfv2, cfv3, cfv4 and cfv4e.
You can also use -mtune=68020-40 for code that needs to run relatively well on 68020, 68030 and 68040 targets. -mtune=68020-60 is similar but includes 68060 targets as well. These two options select the same tuning decisions as -m68020-40 and -m68020-60 respectively.
GCC defines the macros __mc``arch`` and __mc``arch``__ when tuning for 680x0 architecture arch. It also defines mc``arch`` unless either -ansi or a non-GNU -std option is used. If GCC is tuning for a range of architectures, as selected by -mtune=68020-40 or -mtune=68020-60, it defines the macros for every architecture in the range.
GCC also defines the macro __m``uarch``__ when tuning for ColdFire microarchitecture uarch, where uarch is one of the arguments given above.
Generate output for a 68000. This is the default when the compiler is configured for 68000-based systems. It is equivalent to -march=68000.
Use this option for microcontrollers with a 68000 or EC000 core, including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
Generate output for a 68010. This is the default when the compiler is configured for 68010-based systems. It is equivalent to -march=68010.
Generate output for a 68020. This is the default when the compiler is configured for 68020-based systems. It is equivalent to -march=68020.
Generate output for a 68030. This is the default when the compiler is configured for 68030-based systems. It is equivalent to -march=68030.
Generate output for a 68040. This is the default when the compiler is configured for 68040-based systems. It is equivalent to -march=68040.
This option inhibits the use of 68881/68882 instructions that have to be emulated by software on the 68040. Use this option if your 68040 does not have code to emulate those instructions.
Generate output for a 68060. This is the default when the compiler is configured for 68060-based systems. It is equivalent to -march=68060.
This option inhibits the use of 68020 and 68881/68882 instructions that have to be emulated by software on the 68060. Use this option if your 68060 does not have code to emulate those instructions.
Generate output for a CPU32. This is the default when the compiler is configured for CPU32-based systems. It is equivalent to -march=cpu32.
Use this option for microcontrollers with a CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, 68336, 68340, 68341, 68349 and 68360.
Generate output for a 520X ColdFire CPU. This is the default when the compiler is configured for 520X-based systems. It is equivalent to -mcpu=5206, and is now deprecated in favor of that option.
Use this option for microcontroller with a 5200 core, including the MCF5202, MCF5203, MCF5204 and MCF5206.
Generate output for a 5206e ColdFire CPU. The option is now deprecated in favor of the equivalent -mcpu=5206e.
Generate output for a member of the ColdFire 528X family. The option is now deprecated in favor of the equivalent -mcpu=528x.
Generate output for a ColdFire 5307 CPU. The option is now deprecated in favor of the equivalent -mcpu=5307.
Generate output for a ColdFire 5407 CPU. The option is now deprecated in favor of the equivalent -mcpu=5407.
Generate output for a ColdFire V4e family CPU (e.g. 547x/548x). This includes use of hardware floating-point instructions. The option is equivalent to -mcpu=547x, and is now deprecated in favor of that option.
Generate output for a 68040, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68040.
The option is equivalent to -march=68020 -mtune=68020-40.
Generate output for a 68060, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68060.
The option is equivalent to -march=68020 -mtune=68020-60.
Generate floating-point instructions. This is the default for 68020 and above, and for ColdFire devices that have an FPU. It defines the macro __HAVE_68881__ on M680x0 targets and __mcffpu__ on ColdFire targets.
Do not generate floating-point instructions; use library calls instead. This is the default for 68000, 68010, and 68832 targets. It is also the default for ColdFire devices that have no FPU.
Generate (do not generate) ColdFire hardware divide and remainder instructions. If -march is used without -mcpu, the default is ‘on’ for ColdFire architectures and ‘off’ for M680x0 architectures. Otherwise, the default is taken from the target CPU (either the default CPU, or the one specified by -mcpu). For example, the default is ‘off’ for -mcpu=5206 and ‘on’ for -mcpu=5206e.
GCC defines the macro __mcfhwdiv__ when this option is enabled.
Consider type int to be 16 bits wide, like short int. Additionally, parameters passed on the stack are also aligned to a 16-bit boundary even on targets whose API mandates promotion to 32-bit.
Do not consider type int to be 16 bits wide. This is the default.
Do not use the bit-field instructions. The -m68000, -mcpu32 and -m5200 options imply -mnobitfield.
Do use the bit-field instructions. The -m68020 option implies -mbitfield. This is the default if you use a configuration designed for a 68020.
Use a different function-calling convention, in which functions that take a fixed number of arguments return with the rtd instruction, which pops their arguments while returning. This saves one instruction in the caller since there is no need to pop the arguments there.
This calling convention is incompatible with the one normally used on Unix, so you cannot use it if you need to call libraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that take variable numbers of arguments (including printf); otherwise incorrect code is generated for calls to those functions.
In addition, seriously incorrect code results if you call a function with too many arguments. (Normally, extra arguments are harmlessly ignored.)
The rtd instruction is supported by the 68010, 68020, 68030, 68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
Control whether GCC aligns int, long, long long, float, double, and long double variables on a 32-bit boundary (-malign-int) or a 16-bit boundary (-mno-align-int). Aligning variables on 32-bit boundaries produces code that runs somewhat faster on processors with 32-bit busses at the expense of more memory.
Warning: if you use the -malign-int switch, GCC aligns structures containing the above types differently than most published application binary interface specifications for the m68k.
Use the pc-relative addressing mode of the 68000 directly, instead of using a global offset table. At present, this option implies -fpic, allowing at most a 16-bit offset for pc-relative addressing. -fPIC is not presently supported with -mpcrel, though this could be supported for 68020 and higher processors.
Do not (do) assume that unaligned memory references are handled by the system.
When generating position-independent code for ColdFire, generate code that works if the GOT has more than 8192 entries. This code is larger and slower than code generated without this option. On M680x0 processors, this option is not needed; -fPIC suffices.
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as:
relocation truncated to fit: R_68K_GOT16O foobar
If this happens, you should recompile your code with -mxgot. It should then work with very large GOTs. However, code generated with -mxgot is less efficient, since it takes 4 instructions to fetch the value of a global symbol.
Note that some linkers, including newer versions of the GNU linker, can create multiple GOTs and sort GOT entries. If you have such a linker, you should only need to use -mxgot when compiling a single object file that accesses more than 8192 GOT entries. Very few do.
These options have no effect unless GCC is generating position-independent code.
These are the -m options defined for the Motorola M*Core processors.
Inline constants into the code stream if it can be done in two instructions or less.
Use the divide instruction. (Enabled by default).
Allow arbitrary-sized immediates in bit operations.
Always treat bit-fields as int-sized.
Force all functions to be aligned to a 4-byte boundary.
Emit callgraph information.
Prefer word access when reading byte quantities.
Generate code for a little-endian target.
Generate code for the 210 processor.
Assume that runtime support has been provided and so omit the simulator library (libsim.a) from the linker command line.
Set the maximum amount for a single stack increment operation. Large values can increase the speed of programs that contain functions that need a large amount of stack space, but they can also trigger a segmentation fault if the stack is extended too much. The default value is 0x1000.
Enables the abs instruction, which is the absolute difference between two registers.
Enables all the optional instructions-average, multiply, divide, bit operations, leading zero, absolute difference, min/max, clip, and saturation.
Enables the ave instruction, which computes the average of two registers.
Variables of size n bytes or smaller are placed in the .based section by default. Based variables use the $tp register as a base register, and there is a 128-byte limit to the .based section.
Enables the bit operation instructions-bit test (btstm), set (bsetm), clear (bclrm), invert (bnotm), and test-and-set (tas).
Selects which section constant data is placed in. name may be tiny, near, or far.
Enables the clip instruction. Note that -mclip is not useful unless you also provide -mminmax.
Selects one of the built-in core configurations. Each MeP chip has one or more modules in it; each module has a core CPU and a variety of coprocessors, optional instructions, and peripherals. The MeP-Integrator tool, not part of GCC, provides these configurations through this option; using this option is the same as using all the corresponding command-line options. The default configuration is default.
Enables the coprocessor instructions. By default, this is a 32-bit coprocessor. Note that the coprocessor is normally enabled via the -mconfig= option.
Enables the 32-bit coprocessor’s instructions.
Enables the 64-bit coprocessor’s instructions.
Enables IVC2 scheduling. IVC2 is a 64-bit VLIW coprocessor.
Causes constant variables to be placed in the .near section.
Enables the div and divu instructions.
Generate big-endian code.
Generate little-endian code.
Tells the compiler that any variable marked with the io attribute is to be considered volatile.
Causes variables to be assigned to the .far section by default.
Enables the leadz (leading zero) instruction.
Causes variables to be assigned to the .near section by default.
Enables the min and max instructions.
Enables the multiplication and multiply-accumulate instructions.
Disables all the optional instructions enabled by -mall-opts.
Enables the repeat and erepeat instructions, used for low-overhead looping.
Causes all variables to default to the .tiny section. Note that there is a 65536-byte limit to this section. Accesses to these variables use the %gp base register.
Enables the saturation instructions. Note that the compiler does not currently generate these itself, but this option is included for compatibility with other tools, like as.
Link the SDRAM-based runtime instead of the default ROM-based runtime.
Link the simulator run-time libraries.
Link the simulator runtime libraries, excluding built-in support for reset and exception vectors and tables.
Causes all functions to default to the .far section. Without this option, functions default to the .near section.
Variables that are n bytes or smaller are allocated to the .tiny section. These variables use the $gp base register. The default for this option is 4, but note that there’s a 65536-byte limit to the .tiny section.
Use software emulation for floating point (default).
Use hardware floating-point instructions.
Do not optimize block moves, use memcpy.
This option is deprecated. Use -fno-zero-initialized-in-bss instead.
Use features of, and schedule code for, the given CPU. Supported values are in the format v``X`.``YY``.``Z```, where X is a major version, YY is the minor version, and Z is compatibility code. Example values are v3.00.a, v4.00.b, v5.00.a, v5.00.b, v5.00.b, v6.00.a.
Use software multiply emulation (default).
Use software emulation for divides (default).
Use the hardware barrel shifter.
Use pattern compare instructions.
Use table lookup optimization for small signed integer divisions.
This option is deprecated. Use -fstack-check instead.
Use GP-relative .sdata/.sbss sections.
Use multiply high instructions for high part of 32x32 multiply.
Use hardware floating-point conversion instructions.
Use hardware floating-point square root instruction.
Generate code for a big-endian target.
Generate code for a little-endian target.
Use reorder instructions (swap and byte reversed load/store).
Select application model app-model. Valid models are
for applications that do not require any of the MicroBlaze vectors. This option may be useful for applications running within a monitoring application. This model uses crt3.o as a startup file.
Option -xl-mode-``app-model`` is a deprecated alias for
-mxl-mode-``app-model``.
Generate big-endian code.
Generate little-endian code. This is the default for mips*el-*-* configurations.
Generate code that runs on arch, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: mips1, mips2, mips3, mips4, mips32, mips32r2, mips32r3, mips32r5, mips32r6, mips64, mips64r2, mips64r3, mips64r5 and mips64r6. The processor names are: 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, 5kc, 5kf, 20kc, 24kc, 24kf2_1, 24kf1_1, 24kec, 24kef2_1, 24kef1_1, 34kc, 34kf2_1, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf1_1, loongson2e, loongson2f, loongson3a, m4k, m14k, m14kc, m14ke, m14kec, octeon, octeon+, octeon2, octeon3, orion, p5600, r2000, r3000, r3900, r4000, r4400, r4600, r4650, r4700, r6000, r8000, rm7000, rm9000, r10000, r12000, r14000, r16000, sb1, sr71000, vr4100, vr4111, vr4120, vr4130, vr4300, vr5000, vr5400, vr5500, xlr and xlp. The special value from-abi selects the most compatible architecture for the selected ABI (that is, mips1 for 32-bit ABIs and mips3 for 64-bit ABIs).
The native Linux/GNU toolchain also supports the value native, which selects the best architecture option for the host processor. -march=native has no effect if GCC does not recognize the processor.
In processor names, a final 000 can be abbreviated as k (for example, -march=r2k). Prefixes are optional, and vr may be written r.
Names of the form :samp:``n``f2_1 refer to processors with FPUs clocked at half the rate of the core, names of the form :samp:``n``f1_1 refer to processors with FPUs clocked at the same rate as the core, and names of the form :samp:``n``f3_2 refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, :samp:``n``f is accepted as a synonym for :samp:``n``f2_1 while :samp:``n``x and :samp:``b``fx are accepted as synonyms for :samp:``n``f1_1.
GCC defines two macros based on the value of this option. The first is _MIPS_ARCH, which gives the name of target architecture, as a string. The second has the form _MIPS_ARCH_``foo``, where foo is the capitalized value of _MIPS_ARCH. For example, -march=r2000 sets _MIPS_ARCH to "r2000" and defines the macro _MIPS_ARCH_R2000.
Note that the _MIPS_ARCH macro uses the processor names given above. In other words, it has the full prefix and does not abbreviate 000 as k. In the case of from-abi, the macro names the resolved architecture (either "mips1" or "mips3"). It names the default architecture when no -march option is given.
Optimize for arch. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of arch values is the same as for -march.
When this option is not used, GCC optimizes for the processor specified by -march. By using -march and -mtune together, it is possible to generate code that runs on a family of processors, but optimize the code for one particular member of that family.
-mtune defines the macros _MIPS_TUNE and _MIPS_TUNE_``foo``, which work in the same way as the -march ones described above.
Equivalent to -march=mips1.
Equivalent to -march=mips2.
Equivalent to -march=mips3.
Equivalent to -march=mips4.
Equivalent to -march=mips32.
Equivalent to -march=mips32r3.
Equivalent to -march=mips32r5.
Equivalent to -march=mips32r6.
Equivalent to -march=mips64.
Equivalent to -march=mips64r2.
Equivalent to -march=mips64r3.
Equivalent to -march=mips64r5.
Equivalent to -march=mips64r6.
Generate (do not generate) MIPS16 code. If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.
MIPS16 code generation can also be controlled on a per-function basis by means of mips16 and nomips16 attributes. See Declaring Attributes of Functions, for more information.
Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code.
-minterlink-compressed .. option:: -mno-interlink-compressed, -minterlink-compressed
Require (do not require) that code using the standard (uncompressed) MIPS ISA be link-compatible with MIPS16 and microMIPS code, and vice versa.
For example, code using the standard ISA encoding cannot jump directly to MIPS16 or microMIPS code; it must either use a call or an indirect jump. -minterlink-compressed therefore disables direct jumps unless GCC knows that the target of the jump is not compressed.
Aliases of -minterlink-compressed and -mno-interlink-compressed. These options predate the microMIPS ASE and are retained for backwards compatibility.
Generate code for the given ABI.
Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.
For information about the O64 ABI, see http://gcc.gnu.org//projects//mipso64-abi.html.
GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with -mabi=32 -mfp64. This ABI relies on the mthc1 and mfhc1 instructions and is therefore only supported for MIPS32R2, MIPS32R3 and MIPS32R5 processors.
The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in $f0 only, not a $f0/$f1 pair. The set of call-saved registers also remains the same in that the even-numbered double-precision registers are saved.
Two additional variants of the o32 ABI are supported to enable a transition from 32-bit to 64-bit registers. These are FPXX (-mfpxx) and FP64A (-mfp64 -mno-odd-spreg). The FPXX extension mandates that all code must execute correctly when run using 32-bit or 64-bit registers. The code can be interlinked with either FP32 or FP64, but not both. The FP64A extension is similar to the FP64 extension but forbids the use of odd-numbered single-precision registers. This can be used in conjunction with the FRE mode of FPUs in MIPS32R5 processors and allows both FP32 and FP64A code to interlink and run in the same process without changing FPU modes.
Generate (do not generate) code that is suitable for SVR4-style dynamic objects. -mabicalls is the default for SVR4-based systems.
Generate (do not generate) code that is fully position-independent, and that can therefore be linked into shared libraries. This option only affects -mabicalls.
All -mabicalls code has traditionally been position-independent, regardless of options like -fPIC and -fpic. However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions. This mode is selected by -mno-shared.
-mno-shared depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects. Using -mno-shared generally makes executables both smaller and quicker.
-mshared is the default.
Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects -mno-shared -mabicalls. For the n64 ABI, this option has no effect without -msym32.
You can make -mplt the default by configuring GCC with --with-mips-plt. The default is -mno-plt otherwise.
Lift (do not lift) the usual restrictions on the size of the global offset table.
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as:
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with -mxgot. This works with very large GOTs, although the code is also less efficient, since it takes three instructions to fetch the value of a global symbol.
Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k’s worth of GOT entries. Very few do.
These options have no effect unless GCC is generating position independent code.
Assume that general-purpose registers are 32 bits wide.
Assume that general-purpose registers are 64 bits wide.
Assume that floating-point registers are 32 bits wide.
Assume that floating-point registers are 64 bits wide.
Do not assume the width of floating-point registers.
Use floating-point coprocessor instructions.
Do not use floating-point coprocessor instructions. Implement floating-point calculations using library calls instead.
Equivalent to -msoft-float, but additionally asserts that the program being compiled does not perform any floating-point operations. This option is presently supported only by some bare-metal MIPS configurations, where it may select a special set of libraries that lack all floating-point support (including, for example, the floating-point printf formats). If code compiled with -mno-float accidentally contains floating-point operations, it is likely to suffer a link-time or run-time failure.
Assume that the floating-point coprocessor only supports single-precision operations.
Assume that the floating-point coprocessor supports double-precision operations. This is the default.
Enable the use of odd-numbered single-precision floating-point registers for the o32 ABI. This is the default for processors that are known to support these registers. When using the o32 FPXX ABI, -mno-odd-spreg is set by default.
These options control the treatment of the special not-a-number (NaN) IEEE 754 floating-point data with the abs.fmt and neg.fmt machine instructions.
By default or when -mabs=legacy is used the legacy treatment is selected. In this case these instructions are considered arithmetic and avoided where correct operation is required and the input operand might be a NaN. A longer sequence of instructions that manipulate the sign bit of floating-point datum manually is used instead unless the -ffinite-math-only option has also been specified.
The -mabs=2008 option selects the IEEE 754-2008 treatment. In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN. These instructions are therefore always used for the respective operations.
These options control the encoding of the special not-a-number (NaN) IEEE 754 floating-point data.
The -mnan=legacy option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signalling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1.
The -mnan=2008 option selects the IEEE 754-2008 encoding. In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0.
The default is -mnan=legacy unless GCC has been configured with --with-nan=2008.
Use (do not use) ll, sc, and sync instructions to implement atomic memory built-in functions. When neither option is specified, GCC uses the instructions if the target architecture supports them.
-mllsc is useful if the runtime environment can emulate the instructions and -mno-llsc can be useful when compiling for nonstandard ISAs. You can make either option the default by configuring GCC with --with-llsc and --without-llsc respectively. --with-llsc is the default for some configurations; see the installation documentation for details.
Use (do not use) revision 1 of the MIPS DSP ASE. See MIPS DSP Built-in Functions. This option defines the preprocessor macro __mips_dsp. It also defines __mips_dsp_rev to 1.
Use (do not use) revision 2 of the MIPS DSP ASE. See MIPS DSP Built-in Functions. This option defines the preprocessor macros __mips_dsp and __mips_dspr2. It also defines __mips_dsp_rev to 2.
Use (do not use) the MIPS SmartMIPS ASE.
Use (do not use) paired-single floating-point instructions. See MIPS Paired-Single Support. This option requires hardware floating-point support to be enabled.
Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled.
Use (do not use) the MIPS-3D ASE. See MIPS-3D Built-in Functions. The option -mips3d implies -mpaired-single.
Generate (do not generate) microMIPS code.
MicroMIPS code generation can also be controlled on a per-function basis by means of micromips and nomicromips attributes. See Declaring Attributes of Functions, for more information.
Use (do not use) MT Multithreading instructions.
Use (do not use) the MIPS MCU ASE instructions.
Use (do not use) the MIPS Enhanced Virtual Addressing instructions.
Use (do not use) the MIPS Virtualization Application Specific instructions.
Use (do not use) the MIPS eXtended Physical Address (XPA) instructions.
Force long types to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the pointer size is determined.
Force long, int, and pointer types to be 32 bits wide.
The default size of ``int``s, ``long``s and pointers depends on the ABI. All the supported ABIs use 32-bit ``int``s. The n64 ABI uses 64-bit ``long``s, as does the 64-bit EABI; the others use 32-bit ``long``s. Pointers are the same size as ``long``s, or the same size as integer registers, whichever is smaller.
Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with -mabi=64 and -mno-abicalls because it allows GCC to generate shorter and faster references to symbolic addresses.
Put definitions of externally-visible data in a small data section if that data is no bigger than num bytes. GCC can then generate more efficient accesses to the data; see -mgpopt for details.
The default -G option depends on the configuration.
Extend (do not extend) the -G behavior to local data too, such as to static variables in C. -mlocal-sdata is the default for all configurations.
If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with -mno-local-sdata. You might also want to build large libraries with -mno-local-sdata, so that the libraries leave more room for the main program.
Assume (do not assume) that externally-defined data is in a small data section if the size of that data is within the -G limit. -mextern-sdata is the default for all configurations.
If you compile a module Mod with -mextern-sdata -G ``num`` -mgpopt, and Mod references a variable Var that is no bigger than num bytes, you must make sure that Var is placed in a small data section. If Var is defined by another module, you must either compile that module with a high-enough -G setting or attach a section attribute to Var‘s definition. If Var is common, you must link the application with a high-enough -G setting.
The easiest way of satisfying these restrictions is to compile and link every module with the same -G option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported -G setting and additionally using -mno-extern-sdata to stop the library from making assumptions about externally-defined data.
Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see -G, -mlocal-sdata and -mextern-sdata. -mgpopt is the default for all configurations.
-mno-gpopt is useful for cases where the $gp register might not hold the value of _gp. For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines pass an unknown value in $gp. (In such situations, the boot monitor itself is usually compiled with -G0.)
-mno-gpopt implies -mno-local-sdata and -mno-extern-sdata.
Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems.
Put uninitialized const variables in the read-only data section. This option is only meaningful in conjunction with -membedded-data.
Specify whether GCC may generate code that reads from executable sections. There are three possible settings:
Enable (disable) use of the %hi() and %lo() assembler relocation operators. This option has been superseded by -mexplicit-relocs but is retained for backwards compatibility.
Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, selected by -mno-explicit-relocs, is to use assembler macros instead.
-mexplicit-relocs is the default if GCC was configured to use an assembler that supports relocation operators.
Trap (do not trap) on integer division by zero.
The default is -mcheck-zero-division.
MIPS systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (SIGFPE). Use -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force the use of breaks.
The default is usually -mdivide-traps, but this can be overridden at configure time using --with-divide=breaks. Divide-by-zero checks can be completely disabled using -mno-check-zero-division.
Force (do not force) the use of memcpy for non-trivial block moves. The default is -mno-memcpy, which allows GCC to inline most constant-sized copies.
Disable (do not disable) use of the jal instruction. Calling functions using jal is more efficient but requires the caller and callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code. The default is -mno-long-calls.
Enable (disable) use of the mad, madu and mul instructions, as provided by the R4650 ISA.
Enable (disable) use of the madd and msub integer instructions. The default is -mimadd on architectures that support madd and msub except for the 74k architecture where it was found to generate slower code.
Enable (disable) use of the floating-point multiply-accumulate instructions, when they are available. The default is -mfused-madd.
On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances. On other processors the result is numerically identical to the equivalent computation using separate multiply, add, subtract and negate instructions.
Tell the MIPS assembler to not run its preprocessor over user assembler files (with a .s suffix) when assembling them.
-mfix-24k .. option:: -mno-fix-24k, -mfix-24k
Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the assembler rather than by GCC.
Work around certain R4000 CPU errata:
Work around certain R4400 CPU errata:
Work around certain R10000 errata:
This option can only be used if the target architecture supports branch-likely instructions. -mfix-r10000 is the default when -march=r10000 is used; -mno-fix-r10000 is the default otherwise.
Work around the RM7000 dmult/dmultu errata. The workarounds are implemented by the assembler rather than by GCC.
Work around certain VR4120 errata:
The workarounds for the division errata rely on special functions in libgcc.a. At present, these functions are only provided by the mips64vr*-elf configurations.
Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself.
Work around the VR4130 mflo/mfhi errata. The workarounds are implemented by the assembler rather than by GCC, although GCC avoids using mflo and mfhi if the VR4130 macc, macchi, dmacc and dmacchi instructions are available instead.
Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 ‘F1’ and ‘F2’ floating-point errata.)
Specify whether GCC should insert cache barriers to avoid the side-effects of speculation on R10K processors.
In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the ‘taken’ branch. It later aborts these instructions if the predicted outcome is wrong. However, on the R10K, even aborted instructions can have side effects.
This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted. If a DMA operation writes to the same area of memory before the ‘dirty’ line is flushed, the cached data overwrites the DMA-ed data. See the R10K processor manual for a full description, including other potential problems.
One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted. -mr10k-cache-barrier=``setting`` controls GCC’s implementation of this workaround. It assumes that aborted accesses to any byte in the following regions does not have side effects:
It is the kernel’s responsibility to ensure that speculative accesses to these regions are indeed safe.
If the input program contains a function declaration such as:
void foo (void);
then the implementation of foo must allow j foo and jal foo to be executed speculatively. GCC honors this restriction for functions it compiles itself. It expects non-GCC functions (such as hand-written assembly code) to do the same.
The option has three forms:
Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common _flush_func, that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either _flush_func or __cpu_flush.
Set the cost of branches to roughly num ‘simple’ instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, which is based on the -mtune setting.
Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors that implement those architectures; for those, Branch Likely instructions are not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use.
Specifies whether FP exceptions are enabled. This affects how FP instructions are scheduled for some processors. The default is that FP exceptions are enabled.
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe.
The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC aligns pairs of instructions that it thinks should execute in parallel.
This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3.
Enable (disable) generation of synci instructions on architectures that support it. The synci instructions (if enabled) are generated when __builtin___clear_cache is compiled.
This option defaults to -mno-synci, but the default can be overridden by configuring GCC with --with-synci.
When compiling code for single processor systems, it is generally safe to use synci. However, on many multi-core (SMP) systems, it does not invalidate the instruction caches on all cores and may lead to undefined behavior.
Try to turn PIC calls that are normally dispatched via register $25 into direct calls. This is only possible if the linker can resolve the destination at link-time and if the destination is within range for a direct call.
-mrelax-pic-calls is the default if GCC was configured to use an assembler and a linker that support the .reloc assembly directive and -mexplicit-relocs is in effect. With -mno-explicit-relocs, this optimization can be performed by the assembler and the linker alone without help from the compiler.
Emit (do not emit) code that allows _mcount to modify the calling function’s return address. When enabled, this option extends the usual _mcount interface with a new ra-address parameter, which has type intptr_t * and is passed in register $12. _mcount can then modify the return address by doing both of the following:
The default is -mno-mcount-ra-address.
These options are defined for the MMIX:
Specify that intrinsic library functions are being compiled, passing all values in registers, no matter the size.
Generate floating-point comparison instructions that compare with respect to the rE epsilon register.
Generate code that passes function parameters and return values that (in the called function) are seen as registers $0 and up, as opposed to the GNU ABI which uses global registers $231 and up.
When reading data from memory in sizes shorter than 64 bits, use (do not use) zero-extending load instructions by default, rather than sign-extending ones.
Make the result of a division yielding a remainder have the same sign as the divisor. With the default, -mno-knuthdiv, the sign of the remainder follows the sign of the dividend. Both methods are arithmetically valid, the latter being almost exclusively used.
Prepend (do not prepend) a : to all global symbols, so the assembly code can be used with the PREFIX assembly directive.
Generate an executable in the ELF format, rather than the default mmo format used by the mmix simulator.
Use (do not use) the probable-branch instructions, when static branch prediction indicates a probable branch.
Generate (do not generate) code that uses base addresses. Using a base address automatically generates a request (handled by the assembler and the linker) for a constant to be set up in a global register. The register is used for one or more base address requests within the range 0 to 255 from the value held in the register. The generally leads to short and fast code, but the number of different data items that can be addressed is limited. This means that a program that uses lots of static data may require -mno-base-addresses.
Force (do not force) generated code to have a single exit point in each function.
These -m options are defined for Matsushita MN10300 architectures:
Generate code to avoid bugs in the multiply instructions for the MN10300 processors. This is the default.
Do not generate code to avoid bugs in the multiply instructions for the MN10300 processors.
Generate code using features specific to the AM33 processor.
Do not generate code using features specific to the AM33 processor. This is the default.
Generate code using features specific to the AM33/2.0 processor.
Generate code using features specific to the AM34 processor.
Use the timing characteristics of the indicated CPU type when scheduling instructions. This does not change the targeted processor type. The CPU type must be one of mn10300, am33, am33-2 or am34.
When generating a function that returns a pointer, return the pointer in both a0 and d0. Otherwise, the pointer is returned only in a0, and attempts to call such functions without a prototype result in errors. Note that this option is on by default; use -mno-return-pointer-on-d0 to disable it.
Do not link in the C run-time initialization object file.
Indicate to the linker that it should perform a relaxation optimization pass to shorten branches, calls and absolute memory addresses. This option only has an effect when used on the command line for the final link step.
This option makes symbolic debugging impossible.
Allow the compiler to generate Long Instruction Word instructions if the target is the AM33 or later. This is the default. This option defines the preprocessor macro __LIW__.
Do not allow the compiler to generate Long Instruction Word instructions. This option defines the preprocessor macro __NO_LIW__.
Allow the compiler to generate the SETLB and Lcc instructions if the target is the AM33 or later. This is the default. This option defines the preprocessor macro __SETLB__.
Do not allow the compiler to generate SETLB or Lcc instructions. This option defines the preprocessor macro __NO_SETLB__.
Generate big-endian code. This is the default for moxie-*-* configurations.
Generate little-endian code.
Generate mul.x and umul.x instructions. This is the default for moxiebox-*-* configurations.
Do not link in the C run-time initialization object file.
These options are defined for the MSP430:
Force assembly output to always use hex constants. Normally such constants are signed decimals, but this option is available for testsuite and/or aesthetic purposes.
Select the MCU to target. This is used to create a C preprocessor symbol based upon the MCU name, converted to upper case and pre- and post-fixed with __. This in turn is used by the msp430.h header file to select an MCU-specific supplementary header file.
The option also sets the ISA to use. If the MCU name is one that is known to only support the 430 ISA then that is selected, otherwise the 430X ISA is selected. A generic MCU name of msp430 can also be used to select the 430 ISA. Similarly the generic msp430x MCU name selects the 430X ISA.
In addition an MCU-specific linker script is added to the linker command line. The script’s name is the name of the MCU with .ld appended. Thus specifying -mmcu=xxx on the gcc command line defines the C preprocessor symbol __XXX__ and cause the linker to search for a script called xxx.ld.
This option is also passed on to the assembler.
Specifies the ISA to use. Accepted values are msp430, msp430x and msp430xv2. This option is deprecated. The -mmcu= option should be used to select the ISA.
Link to the simulator runtime libraries and linker script. Overrides any scripts that would be selected by the -mmcu= option.
Use large-model addressing (20-bit pointers, 32-bit size_t).
Use small-model addressing (16-bit pointers, 16-bit size_t).
This option is passed to the assembler and linker, and allows the linker to perform certain optimizations that cannot be done until the final link.
Describes the type of hardware multiply supported by the target. Accepted values are none for no hardware multiply, 16bit for the original 16-bit-only multiply supported by early MCUs. 32bit for the 16/32-bit multiply supported by later MCUs and f5series for the 16/32-bit multiply supported by F5-series MCUs. A value of auto can also be given. This tells GCC to deduce the hardware multiply support based upon the MCU name provided by the -mmcu option. If no -mmcu option is specified then 32bit hardware multiply support is assumed. auto is the default setting.
Hardware multiplies are normally performed by calling a library routine. This saves space in the generated code. When compiling at -O3 or higher however the hardware multiplier is invoked inline. This makes for bigger, but faster code.
The hardware multiply routines disable interrupts whilst running and restore the previous interrupt state when they finish. This makes them safe to use inside interrupt handlers as well as in normal code.
Enable the use of a minimum runtime environment - no static initializers or constructors. This is intended for memory-constrained devices. The compiler includes special symbols in some objects that tell the linker and runtime which code fragments are required.
These options tell the compiler where to place functions and data that do not have one of the lower, upper, either or section attributes. Possible values are lower, upper, either or any. The first three behave like the corresponding attribute. The fourth possible value - any - is the default. It leaves placement entirely up to the linker script and how it assigns the standard sections (.text, .data etc) to the memory regions.
These options are defined for NDS32 implementations:
Generate code in big-endian mode.
Generate code in little-endian mode.
Use reduced-set registers for register allocation.
Use full-set registers for register allocation.
Generate conditional move instructions.
Do not generate conditional move instructions.
Generate performance extension instructions.
Do not generate performance extension instructions.
Generate v3 push25/pop25 instructions.
Do not generate v3 push25/pop25 instructions.
Generate 16-bit instructions.
Do not generate 16-bit instructions.
Specify the size of each interrupt vector, which must be 4 or 16.
Specify the size of each cache block, which must be a power of 2 between 4 and 512.
Specify the name of the target architecture.
Set the code model to one of
Enable constructor/destructor feature.
Guide linker to relax instructions.
These are the options defined for the Altera Nios II processor.
Put global and static objects less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS sections. The default value of num is 8.
-mgpopt=option .. option:: -mgpopt, -mno-gpopt
Generate (do not generate) GP-relative accesses. The following option names are recognized:
- none
- Do not generate GP-relative accesses.
- local
- Generate GP-relative accesses for small data objects that are not external or weak. Also use GP-relative addressing for objects that have been explicitly placed in a small data section via a section attribute.
- global
- As for local, but also generate GP-relative accesses for small data objects that are external or weak. If you use this option, you must ensure that all parts of your program (including libraries) are compiled with the same -G setting.
- data
- Generate GP-relative accesses for all data objects in the program. If you use this option, the entire data and BSS segments of your program must fit in 64K of memory and you must use an appropriate linker script to allocate them within the addressible range of the global pointer.
- all
Generate GP-relative addresses for function pointers as well as data pointers. If you use this option, the entire text, data, and BSS segments of your program must fit in 64K of memory and you must use an appropriate linker script to allocate them within the addressible range of the global pointer.
-mgpopt is equivalent to -mgpopt=local, and
-mno-gpopt is equivalent to -mgpopt=none.
The default is -mgpopt except when -fpic or -fPIC is specified to generate position-independent code. Note that the Nios II ABI does not permit GP-relative accesses from shared libraries.
You may need to specify -mno-gpopt explicitly when building programs that include large amounts of small data, including large GOT data sections. In this case, the 16-bit offset for GP-relative addressing may not be large enough to allow access to the entire small data section.
Generate little-endian (default) or big-endian (experimental) code, respectively.
Force all load and store instructions to always bypass cache by using I/O variants of the instructions. The default is not to bypass the cache.
Volatile memory access bypass the cache using the I/O variants of the load and store instructions. The default is not to bypass the cache.
Do not use table-based fast divide for small numbers. The default is to use the fast divide at -O3 and above.
Enable or disable emitting mul, mulx and div family of instructions by the compiler. The default is to emit mul and not emit div and mulx.
Each -mcustom-``insn``=``N`` option enables use of a custom instruction with encoding N when generating code that uses insn. For example, -mcustom-fadds=253 generates custom instruction 253 for single-precision floating-point add operations instead of the default behavior of using a library call.
The following values of insn are supported. Except as otherwise noted, floating-point operations are expected to be implemented with normal IEEE 754 semantics and correspond directly to the C operators or the equivalent GCC built-in functions (see Other Built-in Functions Provided by GCC).
Single-precision floating point:
Floating-point trigonometric and exponential functions. These instructions are only generated if -funsafe-math-optimizations is also specified.
Double-precision floating point:
Double-precision trigonometric and exponential functions. These instructions are only generated if -funsafe-math-optimizations is also specified.
Conversions:
Conversion from signed or unsigned integer types to floating-point types.
In addition, all of the following transfer instructions for internal
registers X and Y must be provided to use any of the double-precision floating-point instructions. Custom instructions taking two double-precision source operands expect the first operand in the 64-bit register X. The other operand (or only operand of a unary operation) is given to the custom arithmetic instruction with the least significant half in source register src1 and the most significant half in src2. A custom instruction that returns a double-precision result returns the most significant 32 bits in the destination register and the other half in 32-bit register Y. GCC automatically generates the necessary code sequences to write register X and/or read register Y when double-precision floating-point instructions are used.
Read the value of Y and store it into dest.
Note that you can gain more local control over generation of Nios II custom
instructions by using the target("custom-``insn``=``N”)`` and target("no-custom-``insn”)`` function attributes (see Declaring Attributes of Functions) or pragmas (see Function Specific Option Pragmas).
This option enables a predefined, named set of custom instruction encodings (see -mcustom-``insn`` above). Currently, the following sets are defined:
-mcustom-fpu-cfg=60-1 is equivalent to:
-mcustom-fmuls=252 -mcustom-fadds=253 -mcustom-fsubs=254 -fsingle-precision-constant -mcustom-fpu-cfg=60-2 is equivalent to:
-mcustom-fmuls=252 -mcustom-fadds=253 -mcustom-fsubs=254 -mcustom-fdivs=255 -fsingle-precision-constant -mcustom-fpu-cfg=72-3 is equivalent to:
-mcustom-floatus=243 -mcustom-fixsi=244 -mcustom-floatis=245 -mcustom-fcmpgts=246 -mcustom-fcmples=249 -mcustom-fcmpeqs=250 -mcustom-fcmpnes=251 -mcustom-fmuls=252 -mcustom-fadds=253 -mcustom-fsubs=254 -mcustom-fdivs=255 -fsingle-precision-constant Custom instruction assignments given by individual -mcustom-``insn``= options override those given by -mcustom-fpu-cfg=, regardless of the order of the options on the command line.
Note that you can gain more local control over selection of a FPU configuration by using the target("custom-fpu-cfg=``name”)`` function attribute (see Declaring Attributes of Functions) or pragma (see Function Specific Option Pragmas).
These additional -m options are available for the Altera Nios II ELF (bare-metal) target:
Link with HAL BSP. This suppresses linking with the GCC-provided C runtime startup and termination code, and is typically used in conjunction with -msys-crt0= to specify the location of the alternate startup code provided by the HAL BSP.
Link with a limited version of the C library, -lsmallc, rather than Newlib.
startfile is the file name of the startfile (crt0) to use when linking. This option is only useful in conjunction with -mhal.
systemlib is the library name of the library that provides low-level system calls required by the C library, e.g. read and write. This option is typically used to link with a library provided by a HAL BSP.
These options are defined for Nvidia PTX:
Generate code for 32-bit or 64-bit ABI.
Link in code for a __main kernel. This is for stand-alone instead of offloading execution.
These options are defined for the PDP-11:
Use hardware FPP floating point. This is the default. (FIS floating point on the PDP-11/40 is not supported.)
Do not use hardware floating point.
Return floating-point results in ac0 (fr0 in Unix assembler syntax).
Return floating-point results in memory. This is the default.
Generate code for a PDP-11/40.
Generate code for a PDP-11/45. This is the default.
Generate code for a PDP-11/10.
Use inline movmemhi patterns for copying memory. This is the default.
Do not use inline movmemhi patterns for copying memory.
Use 16-bit int. This is the default.
Use 32-bit int.
Use 64-bit float. This is the default.
Use 32-bit float.
Use abshi2 pattern. This is the default.
Do not use abshi2 pattern.
Pretend that branches are expensive. This is for experimenting with code generation only.
Do not pretend that branches are expensive. This is the default.
Use Unix assembler syntax. This is the default when configured for pdp11-*-bsd.
Use DEC assembler syntax. This is the default when configured for any PDP-11 target other than pdp11-*-bsd.
These -m options are defined for picoChip implementations:
Set the instruction set, register set, and instruction scheduling parameters for array element type ae_type. Supported values for ae_type are ANY, MUL, and MAC.
-mae=ANY selects a completely generic AE type. Code generated with this option runs on any of the other AE types. The code is not as efficient as it would be if compiled for a specific AE type, and some types of operation (e.g., multiplication) do not work properly on all types of AE.
-mae=MUL selects a MUL AE type. This is the most useful AE type for compiled code, and is the default.
-mae=MAC selects a DSP-style MAC AE. Code compiled with this option may suffer from poor performance of byte (char) manipulation, since the DSP AE does not provide hardware support for byte load/stores.
These are listed under See IBM RS/6000 and PowerPC Options.
Links in additional target libraries to support operation within a simulator.
Specifies the type of hardware multiplication and division support to be used. The simplest is none, which uses software for both multiplication and division. This is the default. The g13 value is for the hardware multiply/divide peripheral found on the RL78/G13 (S2 core) targets. The g14 value selects the use of the multiplication and division instructions supported by the RL78/G14 (S3 core) parts. The value rl78 is an alias for g14 and the value mg10 is an alias for none.
In addition a C preprocessor macro is defined, based upon the setting of this option. Possible values are: __RL78_MUL_NONE__, __RL78_MUL_G13__ or __RL78_MUL_G14__.
Specifies the RL78 core to target. The default is the G14 core, also known as an S3 core or just RL78. The G13 or S2 core does not have multiply or divide instructions, instead it uses a hardware peripheral for these operations. The G10 or S1 core does not have register banks, so it uses a different calling convention.
If this option is set it also selects the type of hardware multiply support to use, unless this is overridden by an explicit -mmul=none option on the command line. Thus specifying -mcpu=g13 enables the use of the G13 hardware multiply peripheral and specifying -mcpu=g10 disables the use of hardware multipications altogether.
Note, although the RL78/G14 core is the default target, specifying -mcpu=g14 or -mcpu=rl78 on the command line does change the behaviour of the toolchain since it also enables G14 hardware multiply support. If these options are not specified on the command line then software multiplication routines will be used even though the code targets the RL78 core. This is for backwards compatibility with older toolchains which did not have hardware multiply and divide support.
In addition a C preprocessor macro is defined, based upon the setting of this option. Possible values are: __RL78_G10__, __RL78_G13__ or __RL78_G14__.
These are aliases for the corresponding -mcpu= option. They are provided for backwards compatibility.
Allow the compiler to use all of the available registers. By default registers r24..r31 are reserved for use in interrupt handlers. With this option enabled these registers can be used in ordinary functions as well.
Make the double data type be 64 bits (-m64bit-doubles) or 32 bits (-m32bit-doubles) in size. The default is -m32bit-doubles.
These -m options are defined for the IBM RS/6000 and PowerPC:
You use these options to specify which instructions are available on the processor you are using. The default value of these options is determined when configuring GCC. Specifying the -mcpu=``cpu_type`` overrides the specification of these options. We recommend you use the -mcpu=``cpu_type`` option rather than the options listed above.
Specifying -mpowerpc-gpopt allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying -mpowerpc-gfxopt allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select.
The -mmfcrf option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. The -mpopcntb option allows GCC to generate the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. The -mpopcntd option allows GCC to generate the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture. The -mfprnd option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The -mcmpb option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. The -mmfpgpr option allows GCC to generate the FP move to/from general-purpose register instructions implemented on the POWER6X processor and other processors that support the extended PowerPC V2.05 architecture. The -mhard-dfp option allows GCC to generate the decimal floating-point instructions implemented on some POWER processors.
The -mpowerpc64 option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to -mno-powerpc64.
Set architecture type, register usage, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are 401, 403, 405, 405fp, 440, 440fp, 464, 464fp, 476, 476fp, 505, 601, 602, 603, 603e, 604, 604e, 620, 630, 740, 7400, 7450, 750, 801, 821, 823, 860, 970, 8540, a2, e300c2, e300c3, e500mc, e500mc64, e5500, e6500, ec603e, G3, G4, G5, titan, power3, power4, power5, power5+, power6, power6x, power7, power8, powerpc, powerpc64, powerpc64le, and rs64.
-mcpu=powerpc, -mcpu=powerpc64, and -mcpu=powerpc64le specify pure 32-bit PowerPC (either endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes.
The other options specify a specific processor. Code generated under those options runs best on that processor, and may not run at all on others.
The -mcpu options automatically enable or disable the following options:
-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple -mpopcntb -mpopcntd -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx -mcrypto -mdirect-move -mpower8-fusion -mpower8-vector -mquad-memory -mquad-memory-atomic The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn’t necessarily reflect the actual hardware’s capabilities. If you wish to set an individual option to a particular value, you may specify it after the -mcpu option, like -mcpu=970 -mno-altivec.
On AIX, the -maltivec and -mpowerpc64 options are not enabled or disabled by the -mcpu option at present because AIX does not have full support for these options. You may still enable or disable them individually if you’re sure it’ll work in your environment.
Set the instruction scheduling parameters for machine type cpu_type, but do not set the architecture type or register usage, as -mcpu=``cpu_type`` does. The same values for cpu_type are used for -mtune as for -mcpu. If both are specified, the code generated uses the architecture and registers set by -mcpu, but the scheduling parameters set by -mtune.
Generate PowerPC64 code for the small model: The TOC is limited to 64k.
Generate PowerPC64 code for the medium model: The TOC and other static data may be up to a total of 4G in size.
Generate PowerPC64 code for the large model: The TOC may be up to 4G in size. Other data and code is only limited by the 64-bit address space.
Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set -mabi=altivec to adjust the current ABI with AltiVec ABI enhancements.
When -maltivec is used, rather than -maltivec=le or -maltivec=be, the element order for Altivec intrinsics such as vec_splat, vec_extract, and vec_insert match array element order corresponding to the endianness of the target. That is, element zero identifies the leftmost element in a vector register when targeting a big-endian platform, and identifies the rightmost element in a vector register when targeting a little-endian platform.
Generate Altivec instructions using big-endian element order, regardless of whether the target is big- or little-endian. This is the default when targeting a big-endian platform.
The element order is used to interpret element numbers in Altivec intrinsics such as vec_splat, vec_extract, and vec_insert. By default, these match array element order corresponding to the endianness for the target.
Generate Altivec instructions using little-endian element order, regardless of whether the target is big- or little-endian. This is the default when targeting a little-endian platform. This option is currently ignored when targeting a big-endian platform.
The element order is used to interpret element numbers in Altivec intrinsics such as vec_splat, vec_extract, and vec_insert. By default, these match array element order corresponding to the endianness for the target.
Generate VRSAVE instructions when generating AltiVec code.
Generate Cell microcode instructions.
Warn when a Cell microcode instruction is emitted. An example of a Cell microcode instruction is a variable shift.
Generate code that allows ld and ld.so to build executables and shared libraries with non-executable .plt and .got sections. This is a PowerPC 32-bit SYSV ABI option.
Generate code that uses a BSS .plt section that ld.so fills in, and requires .plt and .got sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option.
This switch enables or disables the generation of ISEL instructions.
This switch enables or disables the generation of SPE simd instructions.
This switch enables or disables the generation of PAIRED simd instructions.
Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set.
Enable the use (disable) of the built-in functions that allow direct access to the cryptographic instructions that were added in version 2.07 of the PowerPC ISA.
Generate code that uses (does not use) the instructions to move data between the general purpose registers and the vector/scalar (VSX) registers that were added in version 2.07 of the PowerPC ISA.
Generate code that keeps (does not keeps) some integer operations adjacent so that the instructions can be fused together on power8 and later processors.
Generate code that uses (does not use) the vector and scalar instructions that were added in version 2.07 of the PowerPC ISA. Also enable the use of built-in functions that allow more direct access to the vector instructions.
Generate code that uses (does not use) the non-atomic quad word memory instructions. The -mquad-memory option requires use of 64-bit mode.
Generate code that uses (does not use) the atomic quad word memory instructions. The -mquad-memory-atomic option requires use of 64-bit mode.
Generate code that uses (does not use) the scalar double precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.06 of the PowerPC ISA. -mupper-regs-df is turned on by default if you use any of the -mcpu=power7, -mcpu=power8, or -mvsx options.
Generate code that uses (does not use) the scalar single precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.07 of the PowerPC ISA. -mupper-regs-sf is turned on by default if you use either of the -mcpu=power8 or -mpower8-vector options.
Generate code that uses (does not use) the scalar instructions that target all 64 registers in the vector/scalar floating point register set, depending on the model of the machine.
If the -mno-upper-regs option is used, it turns off both -mupper-regs-sf and -mupper-regs-df options.
This switch enables or disables the generation of floating-point operations on the general-purpose registers for architectures that support it.
The argument yes or single enables the use of single-precision floating-point operations.
The argument double enables the use of single and double-precision floating-point operations.
The argument no disables floating-point operations on the general-purpose registers.
This option is currently only available on the MPC854x.
Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux). The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for -mpowerpc64.
Modify generation of the TOC (Table Of Contents), which is created for every executable file. The -mfull-toc option is selected by default. In that case, GCC allocates at least one TOC entry for each unique non-automatic variable reference in your program. GCC also places floating-point constants in the TOC. However, only 16,384 entries are available in the TOC.
If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the -mno-fp-in-toc and -mno-sum-in-toc options. -mno-fp-in-toc prevents GCC from putting floating-point constants in the TOC and -mno-sum-in-toc forces GCC to generate code to calculate the sum of an address and a constant at run time instead of putting that sum into the TOC. You may specify one or both of these options. Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space.
If you still run out of space in the TOC even when you specify both of these options, specify -mminimal-toc instead. This option causes GCC to make only one TOC entry for every file. When you specify this option, GCC produces code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently-executed code.
Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit long type, and the infrastructure needed to support them. Specifying -maix64 implies -mpowerpc64, while -maix32 disables the 64-bit ABI and implies -mno-powerpc64. GCC defaults to -maix32.
Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI. Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs. Do not assume that most significant double in 128-bit long double value is properly rounded when comparing values and converting to double. Use XL symbol names for long double support routines.
The AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared. IBM XL compilers access floating-point arguments that do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization.
Support IBM RS/6000 SP Parallel Environment (PE). Link an application written to use message passing with special startup code to enable the application to run. The system must have PE installed in the standard location (/usr/lpp/ppe.poe/), or the specs file must be overridden with the -specs= option to specify the appropriate directory location. The Parallel Environment does not support threads, so the -mpe option and the -pthread option are incompatible.
On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option -malign-natural overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option -malign-power instructs GCC to follow the ABI-specified alignment rules. GCC defaults to the standard alignment defined in the ABI.
On 64-bit Darwin, natural alignment is the default, and -malign-power is not supported.
Generate code that does not use (uses) the floating-point register set. Software floating-point emulation is provided if you use the -msoft-float option, and pass the option to GCC when linking.
Generate code for single- or double-precision floating-point operations. -mdouble-float implies -msingle-float.
Do not generate sqrt and div instructions for hardware floating-point unit.
Specify type of floating-point unit. Valid values for name are sp_lite (equivalent to -msingle-float -msimple-fpu), dp_lite (equivalent to -mdouble-float -msimple-fpu), sp_full (equivalent to -msingle-float), and dp_full (equivalent to -mdouble-float).
Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mmultiple on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode.
Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mstring on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode.
Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. These instructions are generated by default. If you use -mno-update, there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data.
Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targeting Power6 and disabled otherwise.
Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. The machine-dependent -mfused-madd option is now mapped to the machine-independent -ffp-contract=fast option, and -mno-fused-madd is mapped to -ffp-contract=off.
Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors.
Generate code that uses (does not use) the string-search dlmzb instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors.
On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field.
For example, by default a structure containing nothing but 8 unsigned bit-fields of length 1 is aligned to a 4-byte boundary and has a size of 4 bytes. By using -mno-bit-align, the structure is aligned to a 1-byte boundary and is 1 byte in size.
On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references are handled by the system.
Generate code that allows (does not allow) a static executable to be relocated to a different address at run time. A simple embedded PowerPC system loader should relocate the entire contents of .got2 and 4-byte locations listed in the .fixup section, a table of 32-bit addresses generated by this option. For this to work, all objects linked together must be compiled with -mrelocatable or -mrelocatable-lib. -mrelocatable code aligns the stack to an 8-byte boundary.
Like -mrelocatable, -mrelocatable-lib generates a .fixup section to allow static executables to be relocated at run time, but -mrelocatable-lib does not use the smaller stack alignment of -mrelocatable. Objects compiled with -mrelocatable-lib may be linked with objects compiled with any combination of the -mrelocatable options.
On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program.
On System V.4 and embedded PowerPC systems compile code for the processor in little-endian mode. The -mlittle-endian option is the same as -mlittle.
On System V.4 and embedded PowerPC systems compile code for the processor in big-endian mode. The -mbig-endian option is the same as -mbig.
On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries.
Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins.
This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass. The argument priority takes the value 0, 1, or 2 to assign no, highest, or second-highest (respectively) priority to dispatch-slot restricted instructions.
This option controls which dependences are considered costly by the target during instruction scheduling. The argument dependence_type takes one of the following values:
This option controls which NOP insertion scheme is used during the second scheduling pass. The argument scheme takes one of the following values:
On System V.4 and embedded PowerPC systems compile code using calling conventions that adhere to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement. This is the default unless you configured GCC using powerpc-*-eabiaix.
Specify both -mcall-sysv and -meabi options.
Specify both -mcall-sysv and -mno-eabi options.
On System V.4 and embedded PowerPC systems compile code for the AIX operating system.
On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system.
On System V.4 and embedded PowerPC systems compile code for the FreeBSD operating system.
On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system.
On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system.
Return all structures in memory (as specified by the AIX ABI).
Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI).
Extend the current ABI with a particular extension, or remove such extension. Valid values are altivec, no-altivec, spe, no-spe, ibmlongdouble, ieeelongdouble, elfv1, elfv2.
Extend the current ABI with SPE ABI extensions. This does not change the default ABI, instead it adds the SPE ABI extensions to the current ABI.
Disable Book-E SPE ABI extensions for the current ABI.
Change the current ABI to use IBM extended-precision long double. This is a PowerPC 32-bit SYSV ABI option.
Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option.
Change the current ABI to use the ELFv1 ABI. This is the default ABI for big-endian PowerPC 64-bit Linux. Overriding the default ABI requires special system support and is likely to fail in spectacular ways.
Change the current ABI to use the ELFv2 ABI. This is the default ABI for little-endian PowerPC 64-bit Linux. Overriding the default ABI requires special system support and is likely to fail in spectacular ways.
On System V.4 and embedded PowerPC systems assume that all calls to variable argument functions are properly prototyped. Otherwise, the compiler must insert an instruction before every non-prototyped call to set or clear bit 6 of the condition code register (CR) to indicate whether floating-point values are passed in the floating-point registers in case the function takes variable arguments. With -mprototype, only calls to prototyped variable argument functions set or clear the bit.
On embedded PowerPC systems, assume that the startup module is called sim-crt0.o and that the standard C libraries are libsim.a and libc.a. This is the default for powerpc-*-eabisim configurations.
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libmvme.a and libc.a.
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libads.a and libc.a.
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libyk.a and libc.a.
On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system.
On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags header to indicate that eabi extended relocations are used.
On System V.4 and embedded PowerPC systems do (do not) adhere to the Embedded Applications Binary Interface (EABI), which is a set of modifications to the System V.4 specifications. Selecting -meabi means that the stack is aligned to an 8-byte boundary, a function __eabi is called from main to set up the EABI environment, and the -msdata option can use both r2 and r13 to point to two separate small data areas. Selecting -mno-eabi means that the stack is aligned to a 16-byte boundary, no EABI initialization function is called from main, and the -msdata option only uses r13 to point to a single small data area. The -meabi option is on by default if you configured GCC using one of the powerpc*-*-eabi* options.
On System V.4 and embedded PowerPC systems, put small initialized const global and static data in the .sdata2 section, which is pointed to by register r2. Put small initialized non-const global and static data in the .sdata section, which is pointed to by register r13. Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=eabi option is incompatible with the -mrelocatable option. The -msdata=eabi option also sets the -memb option.
On System V.4 and embedded PowerPC systems, put small global and static data in the .sdata section, which is pointed to by register r13. Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=sysv option is incompatible with the -mrelocatable option.
On System V.4 and embedded PowerPC systems, if -meabi is used, compile code the same as -msdata=eabi, otherwise compile code the same as -msdata=sysv.
On System V.4 and embedded PowerPC systems, put small global data in the .sdata section. Put small uninitialized global data in the .sbss section. Do not use register r13 to address small data however. This is the default behavior unless other -msdata options are used.
On embedded PowerPC systems, put all initialized global and static data in the .data section, and all uninitialized data in the .bss section.
Inline all block moves (such as calls to memcpy or structure copies) less than or equal to num bytes. The minimum value for num is 32 bytes on 32-bit targets and 64 bytes on 64-bit targets. The default value is target-specific.
On embedded PowerPC systems, put global and static items less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS section. By default, num is 8. The -G ``num`` switch is also passed to the linker. All modules should be compiled with the same -G ``num`` value.
On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms.
By default assume that all calls are far away so that a longer and more expensive calling sequence is required. This is required for calls farther than 32 megabytes (33,554,432 bytes) from the current location. A short call is generated if the compiler knows the call cannot be that far away. This setting can be overridden by the shortcall function attribute, or by #pragma longcall(0).
Some linkers are capable of detecting out-of-range calls and generating glue code on the fly. On these systems, long calls are unnecessary and generate slower code. As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64. It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well.
On Darwin/PPC systems, #pragma longcall generates jbsr callee, L42, plus a branch island (glue code). The two target addresses represent the callee and the branch island. The Darwin/PPC linker prefers the first address and generates a bl callee if the PPC bl instruction reaches the callee directly; otherwise, the linker generates bl L42 to call the branch island. The branch island is appended to the body of the calling function; it computes the full 32-bit address of the callee and jumps to it.
On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it.
In the future, GCC may ignore all longcall specifications when the linker is known to generate glue.
Mark (do not mark) calls to __tls_get_addr with a relocation specifying the function argument. The relocation allows the linker to reliably associate function call with argument setup instructions for TLS optimization, which in turn allows GCC to better schedule the sequence.
Adds support for multithreading with the pthreads library. This option sets flags for both the preprocessor and linker.
This option enables use of the reciprocal estimate and reciprocal square root estimate instructions with additional Newton-Raphson steps to increase precision instead of doing a divide or square root and divide for floating-point arguments. You should use the -ffast-math option when using -mrecip (or at least -funsafe-math-optimizations, -finite-math-only, -freciprocal-math and -fno-trapping-math). Note that while the throughput of the sequence is generally higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square roots.
This option controls which reciprocal estimate instructions may be used. opt is a comma-separated list of options, which may be preceded by a ! to invert the option:
Enable the double-precision reciprocal square root approximation instructions.
So, for example, -mrecip=all,!rsqrtd enables
all of the reciprocal estimate instructions, except for the FRSQRTE, XSRSQRTEDP, and XVRSQRTEDP instructions which handle the double-precision reciprocal square root calculations.
Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI. Selecting -mcpu=power6, -mcpu=power7 or -mcpu=power8 automatically selects -mrecip-precision. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an estimate that converges after three steps.
Specifies the ABI type to use for vectorizing intrinsics using an external library. The only type supported at present is mass, which specifies to use IBM’s Mathematical Acceleration Subsystem (MASS) libraries for vectorizing intrinsics using external libraries. GCC currently emits calls to acosd2, acosf4, acoshd2, acoshf4, asind2, asinf4, asinhd2, asinhf4, atan2d2, atan2f4, atand2, atanf4, atanhd2, atanhf4, cbrtd2, cbrtf4, cosd2, cosf4, coshd2, coshf4, erfcd2, erfcf4, erfd2, erff4, exp2d2, exp2f4, expd2, expf4, expm1d2, expm1f4, hypotd2, hypotf4, lgammad2, lgammaf4, log10d2, log10f4, log1pd2, log1pf4, log2d2, log2f4, logd2, logf4, powd2, powf4, sind2, sinf4, sinhd2, sinhf4, sqrtd2, sqrtf4, tand2, tanf4, tanhd2, and tanhf4 when generating code for power7. Both -ftree-vectorize and -funsafe-math-optimizations must also be enabled. The MASS libraries must be specified at link time.
Generate (do not generate) the friz instruction when the -funsafe-math-optimizations option is used to optimize rounding of floating-point values to 64-bit integer and back to floating point. The friz instruction does not return the same value if the floating-point number is too large to fit in an integer.
Generate (do not generate) code to load up the static chain register (r11) when calling through a pointer on AIX and 64-bit Linux systems where a function pointer points to a 3-word descriptor giving the function address, TOC value to be loaded in register r2, and static chain value to be loaded in register r11. The -mpointers-to-nested-functions is on by default. You cannot call through pointers to nested functions or pointers to functions compiled in other languages that use the static chain if you use -mno-pointers-to-nested-functions.
Generate (do not generate) code to save the TOC value in the reserved stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The -mno-save-toc-indirect option is the default.
Generate (do not generate) code to pass structure parameters with a maximum alignment of 64 bits, for compatibility with older versions of GCC.
Older versions of GCC (prior to 4.9.0) incorrectly did not align a structure parameter on a 128-bit boundary when that structure contained a member requiring 128-bit alignment. This is corrected in more recent versions of GCC. This option may be used to generate code that is compatible with functions compiled with older versions of GCC.
The -mno-compat-align-parm option is the default.
These command-line options are defined for RX targets:
Make the double data type be 64 bits (-m64bit-doubles) or 32 bits (-m32bit-doubles) in size. The default is -m32bit-doubles. Note RX floating-point hardware only works on 32-bit values, which is why the default is -m32bit-doubles.
Enables (-fpu) or disables (-nofpu) the use of RX floating-point hardware. The default is enabled for the RX600 series and disabled for the RX200 series.
Floating-point instructions are only generated for 32-bit floating-point values, however, so the FPU hardware is not used for doubles if the -m64bit-doubles option is used.
Note If the -fpu option is enabled then -funsafe-math-optimizations is also enabled automatically. This is because the RX FPU instructions are themselves unsafe.
Selects the type of RX CPU to be targeted. Currently three types are supported, the generic RX600 and RX200 series hardware and the specific RX610 CPU. The default is RX600.
The only difference between RX600 and RX610 is that the RX610 does not support the MVTIPL instruction.
The RX200 series does not have a hardware floating-point unit and so -nofpu is enabled by default when this type is selected.
Store data (but not code) in the big-endian format. The default is -mlittle-endian-data, i.e. to store data in the little-endian format.
Specifies the maximum size in bytes of global and static variables which can be placed into the small data area. Using the small data area can lead to smaller and faster code, but the size of area is limited and it is up to the programmer to ensure that the area does not overflow. Also when the small data area is used one of the RX’s registers (usually r13) is reserved for use pointing to this area, so it is no longer available for use by the compiler. This could result in slower and/or larger code if variables are pushed onto the stack instead of being held in this register.
Note, common variables (variables that have not been initialized) and constants are not placed into the small data area as they are assigned to other sections in the output executable.
The default value is zero, which disables this feature. Note, this feature is not enabled by default with higher optimization levels (-O2 etc) because of the potentially detrimental effects of reserving a register. It is up to the programmer to experiment and discover whether this feature is of benefit to their program. See the description of the -mpid option for a description of how the actual register to hold the small data area pointer is chosen.
Use the simulator runtime. The default is to use the libgloss board-specific runtime.
When generating assembler output use a syntax that is compatible with Renesas’s AS100 assembler. This syntax can also be handled by the GAS assembler, but it has some restrictions so it is not generated by default.
Specifies the maximum size, in bytes, of a constant that can be used as an operand in a RX instruction. Although the RX instruction set does allow constants of up to 4 bytes in length to be used in instructions, a longer value equates to a longer instruction. Thus in some circumstances it can be beneficial to restrict the size of constants that are used in instructions. Constants that are too big are instead placed into a constant pool and referenced via register indirection.
The value N can be between 0 and 4. A value of 0 (the default) or 4 means that constants of any size are allowed.
Enable linker relaxation. Linker relaxation is a process whereby the linker attempts to reduce the size of a program by finding shorter versions of various instructions. Disabled by default.
Specify the number of registers to reserve for fast interrupt handler functions. The value N can be between 0 and 4. A value of 1 means that register r13 is reserved for the exclusive use of fast interrupt handlers. A value of 2 reserves r13 and r12. A value of 3 reserves r13, r12 and r11, and a value of 4 reserves r13 through r10. A value of 0, the default, does not reserve any registers.
Specifies that interrupt handler functions should preserve the accumulator register. This is only necessary if normal code might use the accumulator register, for example because it performs 64-bit multiplications. The default is to ignore the accumulator as this makes the interrupt handlers faster.
Enables the generation of position independent data. When enabled any access to constant data is done via an offset from a base address held in a register. This allows the location of constant data to be determined at run time without requiring the executable to be relocated, which is a benefit to embedded applications with tight memory constraints. Data that can be modified is not affected by this option.
Note, using this feature reserves a register, usually r13, for the constant data base address. This can result in slower and/or larger code, especially in complicated functions.
The actual register chosen to hold the constant data base address depends upon whether the -msmall-data-limit and/or the -mint-register command-line options are enabled. Starting with register r13 and proceeding downwards, registers are allocated first to satisfy the requirements of -mint-register, then -mpid and finally -msmall-data-limit. Thus it is possible for the small data area register to be r8 if both -mint-register=4 and -mpid are specified on the command line.
By default this feature is not enabled. The default can be restored via the -mno-pid command-line option.
Prevents GCC from issuing a warning message if it finds more than one fast interrupt handler when it is compiling a file. The default is to issue a warning for each extra fast interrupt handler found, as the RX only supports one such interrupt.
Enables or disables the use of the string manipulation instructions SMOVF, SCMPU, SMOVB, SMOVU, SUNTIL SWHILE and also the RMPA instruction. These instructions may prefetch data, which is not safe to do if accessing an I/O register. (See section 12.2.7 of the RX62N Group User’s Manual for more information).
The default is to allow these instructions, but it is not possible for GCC to reliably detect all circumstances where a string instruction might be used to access an I/O register, so their use cannot be disabled automatically. Instead it is reliant upon the programmer to use the -mno-allow-string-insns option if their program accesses I/O space.
When the instructions are enabled GCC defines the C preprocessor symbol __RX_ALLOW_STRING_INSNS__, otherwise it defines the symbol __RX_DISALLOW_STRING_INSNS__.
Note: The generic GCC command-line option -ffixed-``reg`` has special significance to the RX port when used with the interrupt function attribute. This attribute indicates a function intended to process fast interrupts. GCC ensures that it only uses the registers r10, r11, r12 and/or r13 and only provided that the normal use of the corresponding registers have been restricted via the -ffixed-``reg`` or -mint-register command-line options.
These are the -m options defined for the S/390 and zSeries architecture.
Use (do not use) the hardware floating-point instructions and registers for floating-point operations. When -msoft-float is specified, functions in libgcc.a are used to perform floating-point operations. When -mhard-float is specified, the compiler generates IEEE floating-point instructions. This is the default.
Use (do not use) the hardware decimal-floating-point instructions for decimal-floating-point operations. When -mno-hard-dfp is specified, functions in libgcc.a are used to perform decimal-floating-point operations. When -mhard-dfp is specified, the compiler generates decimal-floating-point hardware instructions. This is the default for -march=z9-ec or higher.
These switches control the size of long double type. A size of 64 bits makes the long double type equivalent to the double type. This is the default.
Store (do not store) the address of the caller’s frame as backchain pointer into the callee’s stack frame. A backchain may be needed to allow debugging using tools that do not understand DWARF 2 call frame information. When -mno-packed-stack is in effect, the backchain pointer is stored at the bottom of the stack frame; when -mpacked-stack is in effect, the backchain is placed into the topmost word of the 96/160 byte register save area.
In general, code compiled with -mbackchain is call-compatible with code compiled with -mmo-backchain; however, use of the backchain for debugging purposes usually requires that the whole binary is built with -mbackchain. Note that the combination of -mbackchain, -mpacked-stack and -mhard-float is not supported. In order to build a linux kernel use -msoft-float.
The default is to not maintain the backchain.
Use (do not use) the packed stack layout. When -mno-packed-stack is specified, the compiler uses the all fields of the 96/160 byte register save area only for their default purpose; unused fields still take up stack space. When -mpacked-stack is specified, register save slots are densely packed at the top of the register save area; unused space is reused for other purposes, allowing for more efficient use of the available stack space. However, when -mbackchain is also in effect, the topmost word of the save area is always used to store the backchain, and the return address register is always saved two words below the backchain.
As long as the stack frame backchain is not used, code generated with -mpacked-stack is call-compatible with code generated with -mno-packed-stack. Note that some non-FSF releases of GCC 2.95 for S/390 or zSeries generated code that uses the stack frame backchain at run time, not just for debugging purposes. Such code is not call-compatible with code compiled with -mpacked-stack. Also, note that the combination of -mbackchain, -mpacked-stack and -mhard-float is not supported. In order to build a linux kernel use -msoft-float.
The default is to not use the packed stack layout.
Generate (or do not generate) code using the bras instruction to do subroutine calls. This only works reliably if the total executable size does not exceed 64k. The default is to use the basr instruction instead, which does not have this limitation.
When -m31 is specified, generate code compliant to the GNU/Linux for S/390 ABI. When -m64 is specified, generate code compliant to the GNU/Linux for zSeries ABI. This allows GCC in particular to generate 64-bit instructions. For the s390 targets, the default is -m31, while the s390x targets default to -m64.
When -mzarch is specified, generate code using the instructions available on z/Architecture. When -mesa is specified, generate code using the instructions available on ESA/390. Note that -mesa is not possible with -m64. When generating code compliant to the GNU/Linux for S/390 ABI, the default is -mesa. When generating code compliant to the GNU/Linux for zSeries ABI, the default is -mzarch.
Generate (or do not generate) code using the mvcle instruction to perform block moves. When -mno-mvcle is specified, use a mvc loop instead. This is the default unless optimizing for size.
Print (or do not print) additional debug information when compiling. The default is to not print debug information.
Generate code that runs on cpu-type, which is the name of a system representing a certain processor type. Possible values for cpu-type are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12. When generating code using the instructions available on z/Architecture, the default is -march=z900. Otherwise, the default is -march=g5.
Tune to cpu-type everything applicable about the generated code, except for the ABI and the set of available instructions. The list of cpu-type values is the same as for -march. The default is the value used for -march.
Generate code that adds (does not add) in TPF OS specific branches to trace routines in the operating system. This option is off by default, even when compiling for the TPF OS.
Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used.
Emit a warning if the current function exceeds the given frame size. Because this is a compile-time check it doesn’t need to be a real problem when the program runs. It is intended to identify functions that most probably cause a stack overflow. It is useful to be used in an environment with limited stack size e.g. the linux kernel.
Emit a warning if the function calls alloca or uses dynamically-sized arrays. This is generally a bad idea with a limited stack size.
If these options are provided the S/390 back end emits additional instructions in the function prologue that trigger a trap if the stack size is stack-guard bytes above the stack-size (remember that the stack on S/390 grows downward). If the stack-guard option is omitted the smallest power of 2 larger than the frame size of the compiled function is chosen. These options are intended to be used to help debugging stack overflow problems. The additionally emitted code causes only little overhead and hence can also be used in production-like systems without greater performance degradation. The given values have to be exact powers of 2 and stack-size has to be greater than stack-guard without exceeding 64k. In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by stack-size. The stack-guard option can only be used in conjunction with stack-size.
If the hotpatch option is enabled, a ‘hot-patching’ function prologue is generated for all functions in the compilation unit. The funtion label is prepended with the given number of two-byte NOP instructions (pre-halfwords, maximum 1000000). After the label, 2 * post-halfwords bytes are appended, using the largest NOP like instructions the architecture allows (maximum 1000000).
If both arguments are zero, hotpatching is disabled.
This option can be overridden for individual functions with the hotpatch attribute.
These options are defined for Score implementations:
Compile code for big-endian mode. This is the default.
Compile code for little-endian mode.
Disable generation of bcnz instructions.
Enable generation of unaligned load and store instructions.
Enable the use of multiply-accumulate instructions. Disabled by default.
Specify the SCORE5 as the target architecture.
Specify the SCORE5U of the target architecture.
Specify the SCORE7 as the target architecture. This is the default.
Specify the SCORE7D as the target architecture.
These -m options are defined for the SH implementations:
Generate code for the SH1.
Generate code for the SH2.
Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way that the floating-point unit is not used.
Generate code for the SH2a-FPU, in such a way that no double-precision floating-point operations are used.
Generate code for the SH2a-FPU assuming the floating-point unit is in single-precision mode by default.
Generate code for the SH2a-FPU assuming the floating-point unit is in double-precision mode by default.
Generate code for the SH3.
Generate code for the SH3e.
Generate code for the SH4 without a floating-point unit.
Generate code for the SH4 with a floating-point unit that only supports single-precision arithmetic.
Generate code for the SH4 assuming the floating-point unit is in single-precision mode by default.
Generate code for the SH4.
Generate code for SH4-100.
Generate code for SH4-100 in such a way that the floating-point unit is not used.
Generate code for SH4-100 assuming the floating-point unit is in single-precision mode by default.
Generate code for SH4-100 in such a way that no double-precision floating-point operations are used.
Generate code for SH4-200.
Generate code for SH4-200 without in such a way that the floating-point unit is not used.
Generate code for SH4-200 assuming the floating-point unit is in single-precision mode by default.
Generate code for SH4-200 in such a way that no double-precision floating-point operations are used.
Generate code for SH4-300.
Generate code for SH4-300 without in such a way that the floating-point unit is not used.
Generate code for SH4-300 in such a way that no double-precision floating-point operations are used.
Generate code for SH4-300 in such a way that no double-precision floating-point operations are used.
Generate code for SH4-340 (no MMU, no FPU).
Generate code for SH4-500 (no FPU). Passes -isa=sh4-nofpu to the assembler.
Generate code for the SH4al-dsp, or for a SH4a in such a way that the floating-point unit is not used.
Generate code for the SH4a, in such a way that no double-precision floating-point operations are used.
Generate code for the SH4a assuming the floating-point unit is in single-precision mode by default.
Generate code for the SH4a.
Same as -m4a-nofpu, except that it implicitly passes -dsp to the assembler. GCC doesn’t generate any DSP instructions at the moment.
Generate 32-bit code for SHmedia.
Generate 32-bit code for SHmedia in such a way that the floating-point unit is not used.
Generate 64-bit code for SHmedia.
Generate 64-bit code for SHmedia in such a way that the floating-point unit is not used.
Generate code for SHcompact.
Generate code for SHcompact in such a way that the floating-point unit is not used.
Compile code for the processor in big-endian mode.
Compile code for the processor in little-endian mode.
Align doubles at 64-bit boundaries. Note that this changes the calling conventions, and thus some functions from the standard C library do not work unless you recompile it first with -mdalign.
Shorten some address references at link time, when possible; uses the linker option -relax.
Use 32-bit offsets in switch tables. The default is to use 16-bit offsets.
Enable the use of bit manipulation instructions on SH2A.
Comply with the calling conventions defined by Renesas.
Comply with the calling conventions defined for GCC before the Renesas conventions were available. This option is the default for all targets of the SH toolchain.
Control the IEEE compliance of floating-point comparisons, which affects the handling of cases where the result of a comparison is unordered. By default -mieee is implicitly enabled. If -ffinite-math-only is enabled -mno-ieee is implicitly set, which results in faster floating-point greater-equal and less-equal comparisons. The implcit settings can be overridden by specifying either -mieee or -mno-ieee.
Inline code to invalidate instruction cache entries after setting up nested function trampolines. This option has no effect if -musermode is in effect and the selected code generation option (e.g. -m4) does not allow the use of the icbi instruction. If the selected code generation option does not allow the use of the icbi instruction, and -musermode is not in effect, the inlined code manipulates the instruction cache address array directly with an associative write. This not only requires privileged mode at run time, but it also fails if the cache line had been mapped via the TLB and has become unmapped.
Dump instruction size and location in the assembly code.
This option is deprecated. It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI.
Sets the model of atomic operations and additional parameters as a comma separated list. For details on the atomic built-in functions see __atomic Builtins. The following models and parameters are supported:
Generate the tas.b opcode for __atomic_test_and_set. Notice that depending on the particular hardware and software configuration this can degrade overall performance due to the operand cache line flushes that are implied by the tas.b instruction. On multi-core SH4A processors the tas.b instruction must be used with caution since it can result in data corruption for certain cache configurations.
When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table.
Don’t allow (allow) the compiler generating privileged mode code. Specifying -musermode also implies -mno-inline-ic_invalidate if the inlined code would not work in user mode. -musermode is the default when the target is sh*-*-linux*. If the target is SH1* or SH2* -musermode has no effect, since there is no user mode.
Set the cost to assume for a multiply insn.
Set the division strategy to be used for integer division operations. For SHmedia strategy can be one of:
Variants of the inv:minlat strategy. In the case that the inverse calculation is not separated from the multiply, they speed up division where the dividend fits into 20 bits (plus sign where applicable) by inserting a test to skip a number of operations in this case; this test slows down the case of larger dividends. inv20u assumes the case of a such a small dividend to be unlikely, and inv20l assumes it to be likely.
For targets other than SHmedia strategy can be one of:
Calls a library function that uses a lookup table for small divisors and the div1 instruction with case distinction for larger divisors. Division by zero calculates an unspecified result and does not trap. This is the default for SH4. Specifying this for targets that do not have dynamic shift instructions defaults to call-div1.
When a division strategy has not been specified the default strategy is
selected based on the current target. For SH2A the default strategy is to use the divs and divu instructions instead of library function calls.
Reserve space once for outgoing arguments in the function prologue rather than around each call. Generally beneficial for performance and size. Also needed for unwinding to avoid changing the stack frame around conditional code.
Set the name of the library function used for 32-bit signed division to name. This only affects the name used in the call and inv:call division strategies, and the compiler still expects the same sets of input/output/clobbered registers as if this option were not present.
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator can not use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
Enable the use of the indexed addressing mode for SHmedia32/SHcompact. This is only safe if the hardware and/or OS implement 32-bit wrap-around semantics for the indexed addressing mode. The architecture allows the implementation of processors with 64-bit MMU, which the OS could use to get 32-bit addressing, but since no current hardware implementation supports this or any other way to make the indexed addressing mode safe to use in the 32-bit ABI, the default is -mno-indexed-addressing.
Set the cost assumed for the gettr instruction to number. The default is 2 if -mpt-fixed is in effect, 100 otherwise.
Assume pt* instructions won’t trap. This generally generates better-scheduled code, but is unsafe on current hardware. The current architecture definition says that ptabs and ptrel trap when the target anded with 3 is 3. This has the unintentional effect of making it unsafe to schedule these instructions before a branch, or hoist them out of a loop. For example, __do_global_ctors, a part of libgcc that runs constructors at program startup, calls functions in a list which is delimited by -1. With the -mpt-fixed option, the ptabs is done before testing against -1. That means that all the constructors run a bit more quickly, but when the loop comes to the end of the list, the program crashes because ptabs loads -1 into a target register.
Since this option is unsafe for any hardware implementing the current architecture specification, the default is -mno-pt-fixed. Unless specified explicitly with -mgettrcost, -mno-pt-fixed also implies -mgettrcost=100; this deters register allocation from using target registers for storing ordinary integers.
Assume symbols might be invalid. Ordinary function symbols generated by the compiler are always valid to load with movi/shori/ptabs or movi/shori/ptrel, but with assembler and/or linker tricks it is possible to generate symbols that cause ptabs or ptrel to trap. This option is only meaningful when -mno-pt-fixed is in effect. It prevents cross-basic-block CSE, hoisting and most scheduling of symbol loads. The default is -mno-invalid-symbols.
Assume num to be the cost for a branch instruction. Higher numbers make the compiler try to generate more branch-free code if possible. If not specified the value is selected depending on the processor type that is being compiled for.
Assume (do not assume) that zero displacement conditional branch instructions bt and bf are fast. If -mzdcbranch is specified, the compiler prefers zero displacement branch code sequences. This is enabled by default when generating code for SH4 and SH4A. It can be explicitly disabled by specifying -mno-zdcbranch.
Force the usage of delay slots for conditional branches, which stuffs the delay slot with a nop if a suitable instruction can’t be found. By default this option is disabled. It can be enabled to work around hardware bugs as found in the original SH7055.
Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. The machine-dependent -mfused-madd option is now mapped to the machine-independent -ffp-contract=fast option, and -mno-fused-madd is mapped to -ffp-contract=off.
Allow or disallow the compiler to emit the fsca instruction for sine and cosine approximations. The option -mfsca must be used in combination with -funsafe-math-optimizations. It is enabled by default when generating code for SH4A. Using -mno-fsca disables sine and cosine approximations even if -funsafe-math-optimizations is in effect.
Allow or disallow the compiler to emit the fsrra instruction for reciprocal square root approximations. The option -mfsrra must be used in combination with -funsafe-math-optimizations and -ffinite-math-only. It is enabled by default when generating code for SH4A. Using -mno-fsrra disables reciprocal square root approximations even if -funsafe-math-optimizations and -ffinite-math-only are in effect.
Prefer zero-displacement conditional branches for conditional move instruction patterns. This can result in faster code on the SH4 processor.
These -m options are supported on Solaris 2:
-mclear-hwcap tells the compiler to remove the hardware capabilities generated by the Solaris assembler. This is only necessary when object files use ISA extensions not supported by the current machine, but check at runtime whether or not to use them.
-mimpure-text, used in addition to -shared, tells the compiler to not pass -z text to the linker when linking a shared object. Using this option, you can link position-dependent code into a shared object.
-mimpure-text suppresses the ‘relocations remain against allocatable but non-writable sections’ linker error message. However, the necessary relocations trigger copy-on-write, and the shared object is not actually shared across processes. Instead of using -mimpure-text, you should compile all source code with -fpic or -fPIC.
These switches are supported in addition to the above on Solaris 2:
Add support for multithreading using the POSIX threads library. This option sets flags for both the preprocessor and linker. This option does not affect the thread safety of object code produced by the compiler or that of libraries supplied with it.
These -m options are supported on the SPARC:
Specify -mapp-regs to generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications. Like the global register 1, each global register 2 through 4 is then treated as an allocable register that is clobbered by function calls. This is the default.
To be fully SVR4 ABI-compliant at the cost of some performance loss, specify -mno-app-regs. You should compile libraries and system software with this option.
With -mflat, the compiler does not generate save/restore instructions and uses a ‘flat’ or single register window model. This model is compatible with the regular register window model. The local registers and the input registers (0-5) are still treated as ‘call-saved’ registers and are saved on the stack as needed.
With -mno-flat (the default), the compiler generates save/restore instructions (except for leaf functions). This is the normal operating mode.
Generate output containing floating-point instructions. This is the default.
Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all SPARC targets. Normally the facilities of the machine’s usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation. The embedded targets sparc-*-aout and sparclite-*-* do provide software floating-point support.
-msoft-float changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile libgcc.a, the library that comes with GCC, with -msoft-float in order for this to work.
Generate output containing quad-word (long double) floating-point instructions.
Generate output containing library calls for quad-word (long double) floating-point instructions. The functions called are those specified in the SPARC ABI. This is the default.
As of this writing, there are no SPARC implementations that have hardware support for the quad-word floating-point instructions. They all invoke a trap handler for one of these instructions, and then the trap handler emulates the effect of the instruction. Because of the trap handler overhead, this is much slower than calling the ABI library routines. Thus the -msoft-quad-float option is the default.
Assume that doubles have 8-byte alignment. This is the default.
With -munaligned-doubles, GCC assumes that doubles have 8-byte alignment only if they are contained in another type, or if they have an absolute address. Otherwise, it assumes they have 4-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code.
Do not generate code that can only run in supervisor mode. This is relevant only for the casa instruction emitted for the LEON3 processor. The default is -mno-user-mode.
With -mfaster-structs, the compiler assumes that structures should have 8-byte alignment. This enables the use of pairs of ldd and std instructions for copies in structure assignment, in place of twice as many ld and st pairs. However, the use of this changed alignment directly violates the SPARC ABI. Thus, it’s intended only for use on targets where the developer acknowledges that their resulting code is not directly in line with the rules of the ABI.
Set the instruction set, register set, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are v7, cypress, v8, supersparc, hypersparc, leon, leon3, leon3v7, sparclite, f930, f934, sparclite86x, sparclet, tsc701, v9, ultrasparc, ultrasparc3, niagara, niagara2, niagara3 and niagara4.
Native Solaris and GNU/Linux toolchains also support the value native, which selects the best architecture option for the host processor. -mcpu=native has no effect if GCC does not recognize the processor.
Default instruction scheduling parameters are used for values that select an architecture and not an implementation. These are v7, v8, sparclite, sparclet, v9.
Here is a list of each supported architecture and their supported implementations.
ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
By default (unless configured otherwise), GCC generates code for the V7
variant of the SPARC architecture. With -mcpu=cypress, the compiler additionally optimizes it for the Cypress CY7C602 chip, as used in the SPARCStation/SPARCServer 3xx series. This is also appropriate for the older SPARCStation 1, 2, IPX etc.
With -mcpu=v8, GCC generates code for the V8 variant of the SPARC architecture. The only difference from V7 code is that the compiler emits the integer multiply and integer divide instructions which exist in SPARC-V8 but not in SPARC-V7. With -mcpu=supersparc, the compiler additionally optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000 series.
With -mcpu=sparclite, GCC generates code for the SPARClite variant of the SPARC architecture. This adds the integer multiply, integer divide step and scan (ffs) instructions which exist in SPARClite but not in SPARC-V7. With -mcpu=f930, the compiler additionally optimizes it for the Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With -mcpu=f934, the compiler additionally optimizes it for the Fujitsu MB86934 chip, which is the more recent SPARClite with FPU.
With -mcpu=sparclet, GCC generates code for the SPARClet variant of the SPARC architecture. This adds the integer multiply, multiply/accumulate, integer divide step and scan (ffs) instructions which exist in SPARClet but not in SPARC-V7. With -mcpu=tsc701, the compiler additionally optimizes it for the TEMIC SPARClet chip.
With -mcpu=v9, GCC generates code for the V9 variant of the SPARC architecture. This adds 64-bit integer and floating-point move instructions, 3 additional floating-point condition code registers and conditional move instructions. With -mcpu=ultrasparc, the compiler additionally optimizes it for the Sun UltraSPARC I/II/IIi chips. With -mcpu=ultrasparc3, the compiler additionally optimizes it for the Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With -mcpu=niagara, the compiler additionally optimizes it for Sun UltraSPARC T1 chips. With -mcpu=niagara2, the compiler additionally optimizes it for Sun UltraSPARC T2 chips. With -mcpu=niagara3, the compiler additionally optimizes it for Sun UltraSPARC T3 chips. With -mcpu=niagara4, the compiler additionally optimizes it for Sun UltraSPARC T4 chips.
Set the instruction scheduling parameters for machine type cpu_type, but do not set the instruction set or register set that the option -mcpu=``cpu_type`` does.
The same values for -mcpu=``cpu_type`` can be used for -mtune=``cpu_type``, but the only useful values are those that select a particular CPU implementation. Those are cypress, supersparc, hypersparc, leon, leon3, leon3v7, f930, f934, sparclite86x, tsc701, ultrasparc, ultrasparc3, niagara, niagara2, niagara3 and niagara4. With native Solaris and GNU/Linux toolchains, native can also be used.
With -mv8plus, GCC generates code for the SPARC-V8+ ABI. The difference from the V8 ABI is that the global and out registers are considered 64 bits wide. This is enabled by default on Solaris in 32-bit mode for all SPARC-V9 processors.
With -mvis, GCC generates code that takes advantage of the UltraSPARC Visual Instruction Set extensions. The default is -mno-vis.
With -mvis2, GCC generates code that takes advantage of version 2.0 of the UltraSPARC Visual Instruction Set extensions. The default is -mvis2 when targeting a cpu that supports such instructions, such as UltraSPARC-III and later. Setting -mvis2 also sets -mvis.
With -mvis3, GCC generates code that takes advantage of version 3.0 of the UltraSPARC Visual Instruction Set extensions. The default is -mvis3 when targeting a cpu that supports such instructions, such as niagara-3 and later. Setting -mvis3 also sets -mvis2 and -mvis.
With -mcbcond, GCC generates code that takes advantage of compare-and-branch instructions, as defined in the Sparc Architecture 2011. The default is -mcbcond when targeting a cpu that supports such instructions, such as niagara-4 and later.
With -mpopc, GCC generates code that takes advantage of the UltraSPARC population count instruction. The default is -mpopc when targeting a cpu that supports such instructions, such as Niagara-2 and later.
With -mfmaf, GCC generates code that takes advantage of the UltraSPARC Fused Multiply-Add Floating-point extensions. The default is -mfmaf when targeting a cpu that supports such instructions, such as Niagara-3 and later.
Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor).
Enable the documented workarounds for the floating-point errata and the data cache nullify errata of the UT699 processor.
These -m options are supported in addition to the above on SPARC-V9 processors in 64-bit environments:
Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.
Set the code model to one of
Set the memory model in force on the processor to one of
Sequential Consistency
These memory models are formally defined in Appendix D of the Sparc V9
architecture manual, as set in the processor’s PSTATE.MM field.
With -mstack-bias, GCC assumes that the stack pointer, and frame pointer if present, are offset by -2047 which must be added back when making stack frame references. This is the default in 64-bit mode. Otherwise, assume no such offset is present.
These -m options are supported on the SPU:
The loader for SPU does not handle dynamic relocations. By default, GCC gives an error when it generates code that requires a dynamic relocation. -mno-error-reloc disables the error, -mwarn-reloc generates a warning instead.
Instructions that initiate or test completion of DMA must not be reordered with respect to loads and stores of the memory that is being accessed. With -munsafe-dma you must use the volatile keyword to protect memory accesses, but that can lead to inefficient code in places where the memory is known to not change. Rather than mark the memory as volatile, you can use -msafe-dma to tell the compiler to treat the DMA instructions as potentially affecting all memory.
By default, GCC generates a branch hint instruction to avoid pipeline stalls for always-taken or probably-taken branches. A hint is not generated closer than 8 instructions away from its branch. There is little reason to disable them, except for debugging purposes, or to make an object a little bit smaller.
By default, GCC generates code assuming that addresses are never larger than 18 bits. With -mlarge-mem code is generated that assumes a full 32-bit address.
By default, GCC links against startup code that assumes the SPU-style main function interface (which has an unconventional parameter list). With -mstdmain, GCC links your program against startup code that assumes a C99-style interface to main, including a local copy of argv strings.
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
Compile code assuming that pointers to the PPU address space accessed via the __ea named address space qualifier are either 32 or 64 bits wide. The default is 32 bits. As this is an ABI-changing option, all object code in an executable must be compiled with the same setting.
Allow/disallow treating the __ea address space as superset of the generic address space. This enables explicit type casts between __ea and generic pointer as well as implicit conversions of generic pointers to __ea pointers. The default is to allow address space pointer conversions.
This option controls the version of libgcc that the compiler links to an executable and selects a software-managed cache for accessing variables in the __ea address space with a particular cache size. Possible options for cache-size are 8, 16, 32, 64 and 128. The default cache size is 64KB.
This option controls the version of libgcc that the compiler links to an executable and selects whether atomic updates to the software-managed cache of PPU-side variables are used. If you use atomic updates, changes to a PPU variable from SPU code using the __ea named address space qualifier do not interfere with changes to other PPU variables residing in the same cache line from PPU code. If you do not use atomic updates, such interference may occur; however, writing back cache lines is more efficient. The default behavior is to use atomic updates.
By default, GCC inserts nops to increase dual issue when it expects it to increase performance. n can be a value from 0 to 10. A smaller n inserts fewer nops. 10 is the default, 0 is the same as -mno-dual-nops. Disabled with -Os.
Maximum number of nops to insert for a branch hint. A branch hint must be at least 8 instructions away from the branch it is affecting. GCC inserts up to n nops to enforce this, otherwise it does not generate the branch hint.
The encoding of the branch hint instruction limits the hint to be within 256 instructions of the branch it is affecting. By default, GCC makes sure it is within 125.
Work around a hardware bug that causes the SPU to stall indefinitely. By default, GCC inserts the hbrp instruction to make sure this stall won’t happen.
These additional options are available on System V Release 4 for compatibility with other compilers on those systems:
Identify the versions of each tool used by the compiler, in a .ident assembler directive in the output.
Refrain from adding .ident directives to the output file (this is the default).
Search the directories dirs, and no others, for libraries specified with -l.
Look in the directory dir to find the M4 preprocessor. The assembler uses this option.
These -m options are supported on the TILE-Gx:
Generate code for the small model. The distance for direct calls is limited to 500M in either direction. PC-relative addresses are 32 bits. Absolute addresses support the full address range.
Generate code for the large model. There is no limitation on call distance, pc-relative addresses, or absolute addresses.
Selects the type of CPU to be targeted. Currently the only supported type is tilegx.
Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long, and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.
Generate code in big/little endian mode, respectively.
These -m options are supported on the TILEPro:
Selects the type of CPU to be targeted. Currently the only supported type is tilepro.
Generate code for a 32-bit environment, which sets int, long, and pointer to 32 bits. This is the only supported behavior so the flag is essentially ignored.
These -m options are defined for V850 implementations:
Treat all calls as being far away (near). If calls are assumed to be far away, the compiler always loads the function’s address into a register, and calls indirect through the pointer.
Do not optimize (do optimize) basic blocks that use the same index pointer 4 or more times to copy pointer into the ep register, and use the shorter sld and sst instructions. The -mep option is on by default if you optimize.
Do not use (do use) external functions to save and restore registers at the prologue and epilogue of a function. The external functions are slower, but use less code space if more than one function saves the same number of registers. The -mprolog-function option is on by default if you optimize.
Try to make the code as small as possible. At present, this just turns on the -mep and -mprolog-function options.
Put static or global variables whose size is n bytes or less into the tiny data area that register ep points to. The tiny data area can hold up to 256 bytes in total (128 bytes for byte references).
Put static or global variables whose size is n bytes or less into the small data area that register gp points to. The small data area can hold up to 64 kilobytes.
Put static or global variables whose size is n bytes or less into the first 32 kilobytes of memory.
Specify that the target processor is the V850.
Specify that the target processor is the V850E3V5. The preprocessor constant __v850e3v5__ is defined if this option is used.
Specify that the target processor is the V850E3V5. This is an alias for the -mv850e3v5 option.
Specify that the target processor is the V850E2V3. The preprocessor constant __v850e2v3__ is defined if this option is used.
Specify that the target processor is the V850E2. The preprocessor constant __v850e2__ is defined if this option is used.
Specify that the target processor is the V850E1. The preprocessor constants __v850e1__ and __v850e__ are defined if this option is used.
Specify that the target processor is the V850ES. This is an alias for the -mv850e1 option.
Specify that the target processor is the V850E. The preprocessor constant __v850e__ is defined if this option is used.
If neither -mv850 nor -mv850e nor -mv850e1 nor -mv850e2 nor -mv850e2v3 nor -mv850e3v5 are defined then a default target processor is chosen and the relevant __v850*__ preprocessor constant is defined.
The preprocessor constants __v850 and __v851__ are always defined, regardless of which processor variant is the target.
This option suppresses generation of the CALLT instruction for the v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 architecture.
This option is enabled by default when the RH850 ABI is in use (see -mrh850-abi), and disabled by default when the GCC ABI is in use. If CALLT instructions are being generated then the C preprocessor symbol __V850_CALLT__ is defined.
Disable (or re-enable) the generation of PC-relative jump instructions.
Disable (or re-enable) the generation of hardware floating point instructions. This option is only significant when the target architecture is V850E2V3 or higher. If hardware floating point instructions are being generated then the C preprocessor symbol __FPU_OK__ is defined, otherwise the symbol __NO_FPU__ is defined.
Enables the use of the e3v5 LOOP instruction. The use of this instruction is not enabled by default when the e3v5 architecture is selected because its use is still experimental.
Enables support for the RH850 version of the V850 ABI. This is the default. With this version of the ABI the following rules apply:
When this version of the ABI is enabled the C preprocessor symbol __V850_RH850_ABI__ is defined.
Enables support for the old GCC version of the V850 ABI. With this version of the ABI the following rules apply:
When this version of the ABI is enabled the C preprocessor symbol __V850_GCC_ABI__ is defined.
Enables support for double and long long types to be aligned on 8-byte boundaries. The default is to restrict the alignment of all objects to at most 4-bytes. When -m8byte-align is in effect the C preprocessor symbol __V850_8BYTE_ALIGN__ is defined.
Generate code suitable for big switch tables. Use this option only if the assembler/linker complain about out of range branches within a switch table.
This option causes r2 and r5 to be used in the code generated by the compiler. This setting is the default.
This option causes r2 and r5 to be treated as fixed registers.
These -m options are defined for the VAX:
Do not output certain jump instructions (aobleq and so on) that the Unix assembler for the VAX cannot handle across long ranges.
Do output those jump instructions, on the assumption that the GNU assembler is being used.
Output code for G-format floating-point numbers instead of D-format.
A program which performs file I/O and is destined to run on an MCM target should be linked with this option. It causes the libraries libc.a and libdebug.a to be linked. The program should be run on the target under the control of the GDB remote debugging stub.
A program which performs file I/O and is destined to run on the simulator should be linked with option. This causes libraries libc.a and libsim.a to be linked.
Generate code containing floating-point instructions. This is the default.
Generate code containing library calls for floating-point.
-msoft-float changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile libgcc.a, the library that comes with GCC, with -msoft-float in order for this to work.
Set the instruction set, register set, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are mcm, gr5 and gr6.
mcm is a synonym of gr5 present for backward compatibility.
By default (unless configured otherwise), GCC generates code for the GR5 variant of the Visium architecture.
With -mcpu=gr6, GCC generates code for the GR6 variant of the Visium architecture. The only difference from GR5 code is that the compiler will generate block move instructions.
Set the instruction scheduling parameters for machine type cpu_type, but do not set the instruction set or register set that the option -mcpu=``cpu_type`` would.
Generate code for the supervisor mode, where there are no restrictions on the access to general registers. This is the default.
Generate code for the user mode, where the access to some general registers is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this mode; on the GR6, only registers r29 to r31 are affected.
These -m options are defined for the VMS implementations:
Return VMS condition codes from main. The default is to return POSIX-style condition (e.g.error) codes.
Flag the first routine whose name starts with prefix as the main routine for the debugger.
Default to 64-bit memory allocation routines.
Set the default size of pointers. Possible options for size are 32 or short for 32 bit pointers, 64 or long for 64 bit pointers, and no for supporting only 32 bit pointers. The later option disables pragma pointer_size.
The options in this section are defined for all VxWorks targets. Options specific to the target hardware are listed with the other options for that target.
GCC can generate code for both VxWorks kernels and real time processes (RTPs). This option switches from the former to the latter. It also defines the preprocessor macro __RTP__.
Link an RTP executable against shared libraries rather than static libraries. The options -static and -shared can also be used for RTPs (see Options for Linking); -static is the default.
These options are passed down to the linker. They are defined for compatibility with Diab.
Enable lazy binding of function calls. This option is equivalent to -Wl,-z,now and is defined for compatibility with Diab.
Disable lazy binding of function calls. This option is the default and is defined for compatibility with Diab.
These -m options are defined for the x86 family of computers.
Generate instructions for the machine type cpu-type. In contrast to -mtune=``cpu-type``, which merely tunes the generated code for the specified cpu-type, -march=``cpu-type`` allows GCC to generate code that may not run at all on processors other than the one indicated. Specifying -march=``cpu-type`` implies -mtune=``cpu-type``.
The choices for cpu-type are:
Tune to cpu-type everything applicable about the generated code, except for the ABI and the set of available instructions. While picking a specific cpu-type schedules things appropriately for that particular chip, the compiler does not generate any code that cannot run on the default machine type unless you use a -march=``cpu-type`` option. For example, if GCC is configured for i686-pc-linux-gnu then -mtune=pentium4 generates code that is tuned for Pentium 4 but still runs on i686 machines.
The choices for cpu-type are the same as for -march. In addition, -mtune supports 2 extra choices for cpu-type:
Produce code optimized for the most common IA32//AMD64//EM64T processors. If you know the CPU on which your code will run, then you should use the corresponding -mtune or -march option instead of -mtune=generic. But, if you do not know exactly what CPU users of your application will have, then you should use this option.
As new processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the processors that are most common at the time that version of GCC is released.
There is no -march=generic option because -march indicates the instruction set the compiler can use, and there is no generic instruction set applicable to all processors. In contrast, -mtune indicates the processor (or, in this case, collection of processors) for which the code is optimized.
Produce code optimized for the most current Intel processors, which are Haswell and Silvermont for this version of GCC. If you know the CPU on which your code will run, then you should use the corresponding -mtune or -march option instead of -mtune=intel. But, if you want your application performs better on both Haswell and Silvermont, then you should use this option.
As new Intel processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the most current Intel processors at the time that version of GCC is released.
There is no -march=intel option because -march indicates the instruction set the compiler can use, and there is no common instruction set applicable to all processors. In contrast, -mtune indicates the processor (or, in this case, collection of processors) for which the code is optimized.
Generate floating-point arithmetic for selected unit unit. The choices for unit are:
Use the standard 387 floating-point coprocessor present on the majority of chips and emulated otherwise. Code compiled with this option runs almost everywhere. The temporary results are computed in 80-bit precision instead of the precision specified by the type, resulting in slightly different results compared to most of other chips. See -ffloat-store for more detailed description.
This is the default choice for x86-32 targets.
Use scalar floating-point instructions present in the SSE instruction set. This instruction set is supported by Pentium III and newer chips, and in the AMD line by Athlon-4, Athlon XP and Athlon MP chips. The earlier version of the SSE instruction set supports only single-precision arithmetic, thus the double and extended-precision arithmetic are still done using 387. A later version, present only in Pentium 4 and AMD x86-64 chips, supports double-precision arithmetic too.
For the x86-32 compiler, you must use -march=``cpu-type``, -msse or -msse2 switches to enable SSE extensions and make this option effective. For the x86-64 compiler, these extensions are enabled by default.
The resulting code should be considerably faster in the majority of cases and avoid the numerical instability problems of 387 code, but may break some existing code that expects temporaries to be 80 bits.
This is the default choice for the x86-64 compiler.
Output assembly instructions using selected dialect. Also affects which dialect is used for basic asm (see Basic Asm - Assembler Instructions Without Operands) and extended asm (see Extended Asm - Assembler Instructions with C Expression Operands). Supported choices (in dialect order) are att or intel. The default is att. Darwin does not support intel.
Control whether or not the compiler uses IEEE floating-point comparisons. These correctly handle the case where the result of a comparison is unordered.
Generate output containing library calls for floating point.
Warning: the requisite libraries are not part of GCC. Normally the facilities of the machine’s usual C compiler are used, but this can’t be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation.
On machines where a function returns floating-point results in the 80387 register stack, some floating-point opcodes may be emitted even if -msoft-float is used.
Do not use the FPU registers for return values of functions.
The usual calling convention has functions return values of types float and double in an FPU register, even if there is no FPU. The idea is that the operating system should emulate an FPU.
The option -mno-fp-ret-in-387 causes such values to be returned in ordinary CPU registers instead.
Some 387 emulators do not support the sin, cos and sqrt instructions for the 387. Specify this option to avoid generating those instructions. This option is the default on FreeBSD, OpenBSD and NetBSD. This option is overridden when -march indicates that the target CPU always has an FPU and so the instruction does not need emulation. These instructions are not generated unless you also use the -funsafe-math-optimizations switch.
Control whether GCC aligns double, long double, and long long variables on a two-word boundary or a one-word boundary. Aligning double variables on a two-word boundary produces code that runs somewhat faster on a Pentium at the expense of more memory.
On x86-64, -malign-double is enabled by default.
Warning: if you use the -malign-double switch, structures containing the above types are aligned differently than the published application binary interface specifications for the x86-32 and are not binary compatible with structures in code compiled without that switch.
These switches control the size of long double type. The x86-32 application binary interface specifies the size to be 96 bits, so -m96bit-long-double is the default in 32-bit mode.
Modern architectures (Pentium and newer) prefer long double to be aligned to an 8- or 16-byte boundary. In arrays or structures conforming to the ABI, this is not possible. So specifying -m128bit-long-double aligns long double to a 16-byte boundary by padding the long double with an additional 32-bit zero.
In the x86-64 compiler, -m128bit-long-double is the default choice as its ABI specifies that long double is aligned on 16-byte boundary.
Notice that neither of these options enable any extra precision over the x87 standard of 80 bits for a long double.
Warning: if you override the default value for your target ABI, this changes the size of structures and arrays containing long double variables, as well as modifying the function calling convention for functions taking long double. Hence they are not binary-compatible with code compiled without that switch.
These switches control the size of long double type. A size of 64 bits makes the long double type equivalent to the double type. This is the default for 32-bit Bionic C library. A size of 128 bits makes the long double type equivalent to the __float128 type. This is the default for 64-bit Bionic C library.
Warning: if you override the default value for your target ABI, this changes the size of structures and arrays containing long double variables, as well as modifying the function calling convention for functions taking long double. Hence they are not binary-compatible with code compiled without that switch.
Control how GCC aligns variables. Supported values for type are compat uses increased alignment value compatible uses GCC 4.8 and earlier, abi uses alignment value as specified by the psABI, and cacheline uses increased alignment value to match the cache line size. compat is the default.
When -mcmodel=medium is specified, data objects larger than threshold are placed in the large data section. This value must be the same across all objects linked into the binary, and defaults to 65535.
Use a different function-calling convention, in which functions that take a fixed number of arguments return with the ret ``num`` instruction, which pops their arguments while returning. This saves one instruction in the caller since there is no need to pop the arguments there.
You can specify that an individual function is called with this calling sequence with the function attribute stdcall. You can also override the -mrtd option by using the function attribute cdecl. See Declaring Attributes of Functions.
Warning: this calling convention is incompatible with the one normally used on Unix, so you cannot use it if you need to call libraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that take variable numbers of arguments (including printf); otherwise incorrect code is generated for calls to those functions.
In addition, seriously incorrect code results if you call a function with too many arguments. (Normally, extra arguments are harmlessly ignored.)
Control how many registers are used to pass integer arguments. By default, no registers are used to pass arguments, and at most 3 registers can be used. You can control this behavior for a specific function by using the function attribute regparm. See Declaring Attributes of Functions.
Warning: if you use this switch, and num is nonzero, then you must build all modules with the same value, including any libraries. This includes the system libraries and startup modules.
Use SSE register passing conventions for float and double arguments and return values. You can control this behavior for a specific function by using the function attribute sseregparm. See Declaring Attributes of Functions.
Warning: if you use this switch then you must build all modules with the same value, including any libraries. This includes the system libraries and startup modules.
Return 8-byte vectors in memory instead of MMX registers. This is the default on Solaris 8 and 9 and VxWorks to match the ABI of the Sun Studio compilers until version 12. Later compiler versions (starting with Studio 12 Update 1) follow the ABI used by other x86 targets, which is the default on Solaris 10 and later. Only use this option if you need to remain compatible with existing code produced by those previous compiler versions or older versions of GCC.
Set 80387 floating-point precision to 32, 64 or 80 bits. When -mpc32 is specified, the significands of results of floating-point operations are rounded to 24 bits (single precision); -mpc64 rounds the significands of results of floating-point operations to 53 bits (double precision) and -mpc80 rounds the significands of results of floating-point operations to 64 bits (extended double precision), which is the default. When this option is used, floating-point operations in higher precisions are not available to the programmer without setting the FPU control word explicitly.
Setting the rounding of floating-point operations to less than the default 80 bits can speed some programs by 2% or more. Note that some mathematical libraries assume that extended-precision (80-bit) floating-point operations are enabled by default; routines in such libraries could suffer significant loss of accuracy, typically through so-called ‘catastrophic cancellation’, when this option is used to set the precision to less than extended precision.
Realign the stack at entry. On the x86, the -mstackrealign option generates an alternate prologue and epilogue that realigns the run-time stack if necessary. This supports mixing legacy codes that keep 4-byte stack alignment with modern codes that keep 16-byte stack alignment for SSE compatibility. See also the attribute force_align_arg_pointer, applicable to individual functions.
Attempt to keep the stack boundary aligned to a 2 raised to num byte boundary. If -mpreferred-stack-boundary is not specified, the default is 4 (16 bytes or 128 bits).
Warning: When generating code for the x86-64 architecture with SSE extensions disabled, -mpreferred-stack-boundary=3 can be used to keep the stack boundary aligned to 8 byte boundary. Since x86-64 ABI require 16 byte stack alignment, this is ABI incompatible and intended to be used in controlled environment where stack space is important limitation. This option leads to wrong code when functions compiled with 16 byte stack alignment (such as functions from a standard library) are called with misaligned stack. In this case, SSE instructions may lead to misaligned memory access traps. In addition, variable arguments are handled incorrectly for 16 byte aligned objects (including x87 long double and __int128), leading to wrong results. You must build all modules with -mpreferred-stack-boundary=3, including any libraries. This includes the system libraries and startup modules.
Assume the incoming stack is aligned to a 2 raised to num byte boundary. If -mincoming-stack-boundary is not specified, the one specified by -mpreferred-stack-boundary is used.
On Pentium and Pentium Pro, double and long double values should be aligned to an 8-byte boundary (see -malign-double) or suffer significant run time performance penalties. On Pentium III, the Streaming SIMD Extension (SSE) data type __m128 may not work properly if it is not 16-byte aligned.
To ensure proper alignment of this values on the stack, the stack boundary must be as aligned as that required by any value stored on the stack. Further, every function must be generated such that it keeps the stack aligned. Thus calling a function compiled with a higher preferred stack boundary from a function compiled with a lower preferred stack boundary most likely misaligns the stack. It is recommended that libraries that use callbacks always use the default setting.
This extra alignment does consume extra stack space, and generally increases code size. Code that is sensitive to stack space usage, such as embedded systems and operating system kernels, may want to reduce the preferred alignment to -mpreferred-stack-boundary=2.
These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, MPX or 3DNow! extended instruction sets. Each has a corresponding -mno- option to disable use of these instructions.
These extensions are also available as built-in functions: see x86 Built-in Functions, for details of the functions enabled and disabled by these switches.
To generate SSE/SSE2 instructions automatically from floating-point code (as opposed to 387 instructions), see -mfpmath=sse.
GCC depresses SSEx instructions when -mavx is used. Instead, it generates new AVX instructions or AVX equivalence for all SSEx instructions when needed.
These options enable GCC to use these extended instructions in generated code, even without -mfpmath=sse. Applications that perform run-time CPU detection must compile separate files for each supported architecture, using the appropriate flags. In particular, the file containing the CPU detection code should be compiled without these options.
This option instructs GCC to dump the names of the x86 performance tuning features and default settings. The names can be used in -mtune-ctrl=``feature-list``.
This option is used to do fine grain control of x86 code generation features. feature-list is a comma separated list of feature names. See also -mdump-tune-features. When specified, the feature is turned on if it is not preceded with ^, otherwise, it is turned off. -mtune-ctrl=``feature-list`` is intended to be used by GCC developers. Using it may lead to code paths not covered by testing and can potentially result in compiler ICEs or runtime errors.
This option instructs GCC to turn off all tunable features. See also -mtune-ctrl=``feature-list`` and -mdump-tune-features.
This option instructs GCC to emit a cld instruction in the prologue of functions that use string instructions. String instructions depend on the DF flag to select between autoincrement or autodecrement mode. While the ABI specifies the DF flag to be cleared on function entry, some operating systems violate this specification by not clearing the DF flag in their exception dispatchers. The exception handler can be invoked with the DF flag set, which leads to wrong direction mode when string instructions are used. This option can be enabled by default on 32-bit x86 targets by configuring GCC with the --enable-cld configure option. Generation of cld instructions can be suppressed with the -mno-cld compiler option in this case.
This option instructs GCC to emit a vzeroupper instruction before a transfer of control flow out of the function to minimize the AVX to SSE transition penalty as well as remove unnecessary zeroupper intrinsics.
This option instructs GCC to use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
This option enables GCC to generate CMPXCHG16B instructions. CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high-resolution counters that can be updated by multiple processors (or cores). This instruction is generated as part of atomic built-in functions: see __sync Builtins or __atomic Builtins for details.
This option enables generation of SAHF instructions in 64-bit code. Early Intel Pentium 4 CPUs with Intel 64 support, prior to the introduction of Pentium 4 G1 step in December 2005, lacked the LAHF and SAHF instructions which are supported by AMD64. These are load and store instructions, respectively, for certain status flags. In 64-bit mode, the SAHF instruction is used to optimize fmod, drem, and remainder built-in functions; see Other Builtins for details.
This option enables use of the movbe instruction to implement __builtin_bswap32 and __builtin_bswap64.
This option enables built-in functions __builtin_ia32_crc32qi, __builtin_ia32_crc32hi, __builtin_ia32_crc32si and __builtin_ia32_crc32di to generate the crc32 machine instruction.
This option enables use of RCPSS and RSQRTSS instructions (and their vectorized variants RCPPS and RSQRTPS) with an additional Newton-Raphson step to increase precision instead of DIVSS and SQRTSS (and their vectorized variants) for single-precision floating-point arguments. These instructions are generated only when -funsafe-math-optimizations is enabled together with -finite-math-only and -fno-trapping-math. Note that while the throughput of the sequence is higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
Note that GCC implements 1.0f/sqrtf(``x)`` in terms of RSQRTSS (or RSQRTPS) already with -ffast-math (or the above option combination), and doesn’t need -mrecip.
Also note that GCC emits the above sequence with additional Newton-Raphson step for vectorized single-float division and vectorized sqrtf(``x)`` already with -ffast-math (or the above option combination), and doesn’t need -mrecip.
This option controls which reciprocal estimate instructions may be used. opt is a comma-separated list of options, which may be preceded by a ! to invert the option:
Enable the approximation for vectorized square root.
So, for example, -mrecip=all,!sqrt enables
all of the reciprocal approximations, except for square root.
Specifies the ABI type to use for vectorizing intrinsics using an external library. Supported values for type are svml for the Intel short vector math library and acml for the AMD math core library. To use this option, both -ftree-vectorize and -funsafe-math-optimizations have to be enabled, and an SVML or ACML ABI-compatible library must be specified at link time.
GCC currently emits calls to vmldExp2, vmldLn2, vmldLog102, vmldLog102, vmldPow2, vmldTanh2, vmldTan2, vmldAtan2, vmldAtanh2, vmldCbrt2, vmldSinh2, vmldSin2, vmldAsinh2, vmldAsin2, vmldCosh2, vmldCos2, vmldAcosh2, vmldAcos2, vmlsExp4, vmlsLn4, vmlsLog104, vmlsLog104, vmlsPow4, vmlsTanh4, vmlsTan4, vmlsAtan4, vmlsAtanh4, vmlsCbrt4, vmlsSinh4, vmlsSin4, vmlsAsinh4, vmlsAsin4, vmlsCosh4, vmlsCos4, vmlsAcosh4 and vmlsAcos4 for corresponding function type when -mveclibabi=svml is used, and __vrd2_sin, __vrd2_cos, __vrd2_exp, __vrd2_log, __vrd2_log2, __vrd2_log10, __vrs4_sinf, __vrs4_cosf, __vrs4_expf, __vrs4_logf, __vrs4_log2f, __vrs4_log10f and __vrs4_powf for the corresponding function type when -mveclibabi=acml is used.
Generate code for the specified calling convention. Permissible values are sysv for the ABI used on GNU/Linux and other systems, and ms for the Microsoft ABI. The default is to use the Microsoft ABI when targeting Microsoft Windows and the SysV ABI on all other systems. You can control this behavior for specific functions by using the function attributes ms_abi and sysv_abi. See Declaring Attributes of Functions.
Generate code to access thread-local storage using the gnu or gnu2 conventions. gnu is the conservative default; gnu2 is more efficient, but it may add compile- and run-time requirements that cannot be satisfied on all systems.
Use PUSH operations to store outgoing parameters. This method is shorter and usually equally fast as method using SUB/MOV operations and is enabled by default. In some cases disabling it may improve performance because of improved scheduling and reduced dependencies.
If enabled, the maximum amount of space required for outgoing arguments is computed in the function prologue. This is faster on most modern CPUs because of reduced dependencies, improved scheduling and reduced stack usage when the preferred stack boundary is not equal to 2. The drawback is a notable increase in code size. This switch implies -mno-push-args.
Support thread-safe exception handling on MinGW. Programs that rely on thread-safe exception handling must compile and link all code with the -mthreads option. When compiling, -mthreads defines -D_MT; when linking, it links in a special thread helper library -lmingwthrd which cleans up per-thread exception-handling data.
Do not align the destination of inlined string operations. This switch reduces code size and improves performance in case the destination is already aligned, but GCC doesn’t know about it.
By default GCC inlines string operations only when the destination is known to be aligned to least a 4-byte boundary. This enables more inlining and increases code size, but may improve performance of code that depends on fast memcpy, strlen, and memset for short lengths.
For string operations of unknown size, use run-time checks with inline code for small blocks and a library call for large blocks.
Override the internal decision heuristic for the particular algorithm to use for inlining string operations. The allowed values for alg are:
Override the internal decision heuristic to decide if __builtin_memcpy should be inlined and what inline algorithm to use when the expected size of the copy operation is known. strategy is a comma-separated list of alg:max_size:dest_align triplets. alg is specified in -mstringop-strategy, max_size specifies the max byte size with which inline algorithm alg is allowed. For the last triplet, the max_size must be -1. The max_size of the triplets in the list must be specified in increasing order. The minimal byte size for alg is 0 for the first triplet and ``max_size + 1`` of the preceding range.
The option is similar to -mmemcpy-strategy= except that it is to control __builtin_memset expansion.
Don’t keep the frame pointer in a register for leaf functions. This avoids the instructions to save, set up, and restore frame pointers and makes an extra register available in leaf functions. The option -fomit-leaf-frame-pointer removes the frame pointer for leaf functions, which might make debugging harder.
Controls whether TLS variables may be accessed with offsets from the TLS segment register (%gs for 32-bit, %fs for 64-bit), or whether the thread base pointer must be added. Whether or not this is valid depends on the operating system, and whether it maps the segment to cover the entire TLS area.
For systems that use the GNU C Library, the default is on.
Specify that the assembler should encode SSE instructions with VEX prefix. The option -mavx turns this on by default.
If profiling is active (-pg), put the profiling counter call before the prologue. Note: On x86 architectures the attribute ms_hook_prologue isn’t possible at the moment for -mfentry and -pg.
If profiling is active (-pg), generate a __mcount_loc section that contains pointers to each profiling call. This is useful for automatically patching and out calls.
If profiling is active (-pg), generate the calls to the profiling functions as nops. This is useful when they should be patched in later dynamically. This is likely only useful together with -mrecord-mcount.
When generating code for the x86-64 architecture with SSE extensions disabled, -skip-rax-setup can be used to skip setting up RAX register when there are no variable arguments passed in vector registers.
Warning: Since RAX register is used to avoid unnecessarily saving vector registers on stack when passing variable arguments, the impacts of this option are callees may waste some stack space, misbehave or jump to a random location. GCC 4.4 or newer don’t have those issues, regardless the RAX register value.
On some processors, like Intel Atom, 8-bit unsigned integer divide is much faster than 32-bit/64-bit integer divide. This option generates a run-time check. If both dividend and divisor are within range of 0 to 255, 8-bit unsigned integer divide is used instead of 32-bit/64-bit integer divide.
Split 32-byte AVX unaligned load and store.
Generate stack protection code using canary at guard. Supported locations are global for global canary or tls for per-thread canary in the TLS block (the default). This option has effect only when -fstack-protector or -fstack-protector-all is specified.
These -m switches are supported in addition to the above on x86-64 processors in 64-bit environments.
Generate code for a 16-bit, 32-bit or 64-bit environment. The -m32 option sets int, long, and pointer types to 32 bits, and generates code that runs on any i386 system.
The -m64 option sets int to 32 bits and long and pointer types to 64 bits, and generates code for the x86-64 architecture. For Darwin only the -m64 option also turns off the -fno-pic and -mdynamic-no-pic options.
The -mx32 option sets int, long, and pointer types to 32 bits, and generates code for the x86-64 architecture.
The -m16 option is the same as -m32, except for that it outputs the .code16gcc assembly directive at the beginning of the assembly output so that the binary can run in 16-bit mode.
Do not use a so-called ‘red zone’ for x86-64 code. The red zone is mandated by the x86-64 ABI; it is a 128-byte area beyond the location of the stack pointer that is not modified by signal or interrupt handlers and therefore can be used for temporary data without adjusting the stack pointer. The flag -mno-red-zone disables this red zone.
Generate code for the small code model: the program and its symbols must be linked in the lower 2 GB of the address space. Pointers are 64 bits. Programs can be statically or dynamically linked. This is the default code model.
Generate code for the kernel code model. The kernel runs in the negative 2 GB of the address space. This model has to be used for Linux kernel code.
Generate code for the medium model: the program is linked in the lower 2 GB of the address space. Small symbols are also placed there. Symbols with sizes larger than -mlarge-data-threshold are put into large data or BSS sections and can be located above 2GB. Programs can be statically or dynamically linked.
Generate code for the large model. This model makes no assumptions about addresses and sizes of sections.
Generate code for long address mode. This is only supported for 64-bit and x32 environments. It is the default address mode for 64-bit environments.
Generate code for short address mode. This is only supported for 32-bit and x32 environments. It is the default address mode for 32-bit and x32 environments.
These additional options are available for Microsoft Windows targets:
This option specifies that a console application is to be generated, by instructing the linker to set the PE header subsystem type required for console applications. This option is available for Cygwin and MinGW targets and is enabled by default on those targets.
This option is available for Cygwin and MinGW targets. It specifies that a DLL-a dynamic link library-is to be generated, enabling the selection of the required runtime startup object and entry point.
This option is available for Cygwin and MinGW targets. It specifies that the dllimport attribute should be ignored.
This option is available for MinGW targets. It specifies that MinGW-specific thread support is to be used.
This option is available for MinGW-w64 targets. It causes the UNICODE preprocessor macro to be predefined, and chooses Unicode-capable runtime startup code.
This option is available for Cygwin and MinGW targets. It specifies that the typical Microsoft Windows predefined macros are to be set in the pre-processor, but does not influence the choice of runtime library/startup code.
This option is available for Cygwin and MinGW targets. It specifies that a GUI application is to be generated by instructing the linker to set the PE header subsystem type appropriately.
This option is available for MinGW targets. It specifies that the executable flag for the stack used by nested functions isn’t set. This is necessary for binaries running in kernel mode of Microsoft Windows, as there the User32 API, which is used to set executable privileges, isn’t available.
This option is available for MinGW and Cygwin targets. It specifies that relocated-data in read-only section is put into .data section. This is a necessary for older runtimes not supporting modification of .rdata sections for pseudo-relocation.
This option is available for Cygwin and MinGW targets. It specifies that the GNU extension to the PE file format that permits the correct alignment of COMMON variables should be used when generating code. It is enabled by default if GCC detects that the target assembler found during configuration supports the feature.
See also under x86 Options for standard options.
These options are defined for Xstormy16:
Choose startup files and linker script suitable for the simulator.
These options are supported for Xtensa targets:
Enable or disable use of CONST16 instructions for loading constant values. The CONST16 instruction is currently not a standard option from Tensilica. When enabled, CONST16 instructions are always used in place of the standard L32R instructions. The use of CONST16 is enabled by default only if the L32R instruction is not available.
Enable or disable use of fused multiply/add and multiply/subtract instructions in the floating-point option. This has no effect if the floating-point option is not also enabled. Disabling fused multiply/add and multiply/subtract instructions forces the compiler to use separate instructions for the multiply and add/subtract operations. This may be desirable in some cases where strict IEEE 754-compliant results are required: the fused multiply add/subtract instructions do not round the intermediate result, thereby producing results with more bits of precision than specified by the IEEE standard. Disabling fused multiply add/subtract instructions also ensures that the program output is not sensitive to the compiler’s ability to combine multiply and add/subtract operations.
When this option is enabled, GCC inserts MEMW instructions before volatile memory references to guarantee sequential consistency. The default is -mserialize-volatile. Use -mno-serialize-volatile to omit the MEMW instructions.
For targets, like GNU/Linux, where all user-mode Xtensa code must be position-independent code (PIC), this option disables PIC for compiling kernel code.
These options control the treatment of literal pools. The default is -mno-text-section-literals, which places literals in a separate section in the output file. This allows the literal pool to be placed in a data RAM/ROM, and it also allows the linker to combine literal pools from separate object files to remove redundant literals and improve code size. With -mtext-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files.
When this option is enabled, GCC instructs the assembler to automatically align instructions to reduce branch penalties at the expense of some code density. The assembler attempts to widen density instructions to align branch targets and the instructions following call instructions. If there are not enough preceding safe density instructions to align a target, no widening is performed. The default is -mtarget-align. These options do not affect the treatment of auto-aligned instructions like LOOP, which the assembler always aligns, either by widening density instructions or by inserting NOP instructions.
When this option is enabled, GCC instructs the assembler to translate direct calls to indirect calls unless it can determine that the target of a direct call is in the range allowed by the call instruction. This translation typically occurs for calls to functions in other source files. Specifically, the assembler translates a direct CALL instruction into an L32R followed by a CALLX instruction. The default is -mno-longcalls. This option should be used in programs where the call target can potentially be out of range. This option is implemented in the assembler, not the compiler, so the assembly code generated by GCC still shows direct call instructions-look at the disassembled object code to see the actual instructions. Note that the assembler uses an indirect call for every cross-file call, not just those that really are out of range.
These are listed under See S/390 and zSeries Options.