- Generated by
1.8.1.1
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GCC Middle and Back End API Reference
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Data Structures | |
| struct | inc_insn |
| struct | mem_insn |
Enumerations | |
| enum | form { FORM_PRE_ADD, FORM_PRE_INC, FORM_POST_ADD, FORM_POST_INC, FORM_last } |
| enum | inc_state { INC_ZERO, INC_NEG_SIZE, INC_POS_SIZE, INC_NEG_ANY, INC_POS_ANY, INC_REG, INC_last } |
| enum | gen_form { NOTHING, SIMPLE_PRE_INC, SIMPLE_POST_INC, SIMPLE_PRE_DEC, SIMPLE_POST_DEC, DISP_PRE, DISP_POST, REG_PRE, REG_POST } |
Functions | |
| static enum inc_state | set_inc_state () |
| static void | init_decision_table () |
| static void | dump_inc_insn () |
| static void | dump_mem_insn () |
| static void | move_dead_notes () |
| static rtx | insert_move_insn_before () |
| static bool | attempt_change () |
| static bool | try_merge () |
| static rtx | get_next_ref () |
| static void | reverse_mem () |
| static void | reverse_inc () |
| static bool | parse_add_or_inc () |
| static int | find_address () |
| static bool | find_inc () |
| static bool | find_mem () |
| static void | merge_in_block () |
| static unsigned int | rest_of_handle_auto_inc_dec () |
| static bool | gate_auto_inc_dec () |
| rtl_opt_pass * | make_pass_inc_dec () |
Variables | |
| static rtx | mem_tmp |
| static bool | initialized = false |
| static enum gen_form | decision_table [INC_last][INC_last][FORM_last] |
| static struct inc_insn | inc_insn |
| static struct mem_insn | mem_insn |
| static rtx * | reg_next_use = NULL |
| static rtx * | reg_next_inc_use = NULL |
| static rtx * | reg_next_def = NULL |
| enum form |
@verbatim
Discovery of auto-inc and auto-dec instructions. Copyright (C) 2006-2013 Free Software Foundation, Inc. Contributed by Kenneth Zadeck zadeck@naturalbridge.com
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see http://www.gnu.org/licenses/.
This pass was originally removed from flow.c. However there is
almost nothing that remains of that code.
There are (4) basic forms that are matched:
(1) FORM_PRE_ADD
a <- b + c
...
*a
becomes
a <- b
...
*(a += c) pre
(2) FORM_PRE_INC
a += c
...
*a
becomes
*(a += c) pre
(3) FORM_POST_ADD
*a
...
b <- a + c
(For this case to be true, b must not be assigned or used between
the *a and the assignment to b. B must also be a Pmode reg.)
becomes
b <- a
...
*(b += c) post
(4) FORM_POST_INC
*a
...
a <- a + c
becomes
*(a += c) post
There are three types of values of c.
1) c is a constant equal to the width of the value being accessed by
the pointer. This is useful for machines that have
HAVE_PRE_INCREMENT, HAVE_POST_INCREMENT, HAVE_PRE_DECREMENT or
HAVE_POST_DECREMENT defined.
2) c is a constant not equal to the width of the value being accessed
by the pointer. This is useful for machines that have
HAVE_PRE_MODIFY_DISP, HAVE_POST_MODIFY_DISP defined.
3) c is a register. This is useful for machines that have
HAVE_PRE_MODIFY_REG, HAVE_POST_MODIFY_REG
The is one special case: if a already had an offset equal to it +-
its width and that offset is equal to -c when the increment was
before the ref or +c if the increment was after the ref, then if we
can do the combination but switch the pre/post bit.
| enum gen_form |
| enum inc_state |
The states of the second operands of mem refs and inc insns. If no second operand of the mem_ref was found, it is assumed to just be ZERO. SIZE is the size of the mode accessed in the memref. The ANY is used for constants that are not +-size or 0. REG is used if the forms are reg1 + reg2.
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Change mem_insn.mem_loc so that uses NEW_ADDR which has an increment of INC_REG. To have reached this point, the change is a legitimate one from a dataflow point of view. The only questions are is this a valid change to the instruction and is this a profitable change to the instruction.
There are four cases: For the two cases that involve an add
instruction, we are going to have to delete the add and insert a
mov. We are going to assume that the mov is free. This is
fairly early in the backend and there are a lot of opportunities
for removing that move later. In particular, there is the case
where the move may be dead, this is what dead code elimination
passes are for. The two cases where we have an inc insn will be
handled mov free. The first item of business is to see if this is profitable.
Jump through a lot of hoops to keep the attributes up to date. We
do not want to call one of the change address variants that take
an offset even though we know the offset in many cases. These
assume you are changing where the address is pointing by the
offset. From here to the end of the function we are committed to the
change, i.e. nothing fails. Generate any necessary movs, move
any regnotes, and fix up the reg_next_{use,inc_use,def}. Replace the addition with a move. Do it at the location of
the addition since the operand of the addition may change
before the memory reference. Fallthru.
Do not move anything to the mov insn because the instruction
pointer for the main iteration has not yet hit that. It is
still pointing to the mem insn. Record that this insn has an implicit side effect.
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Dump the parsed inc insn to FILE.
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Dump the parsed mem insn to FILE.
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A recursive function that checks all of the mem uses in ADDRESS_OF_X to see if any single one of them is compatible with what has been found in inc_insn. -1 is returned for success. 0 is returned if nothing was found and 1 is returned for failure.
Match with *reg0.
Match with *(reg0 + reg1) where reg1 is a const.
Match with *(reg0 + reg1).
If REG occurs inside a MEM used in a bit-field reference,
that is unacceptable. Time for some deep diving.
If this is the first use, let it go so the rest of the
insn can be checked. More than one match was found.
If this is the first use, let it go so the rest of
the insn can be checked. More than one match was found.
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Once a suitable mem reference has been found and the MEM_INSN structure has been filled in, FIND_INC is called to see if there is a suitable add or inc insn that follows the mem reference and determine if it is suitable to merge. In the case where the MEM_INSN has two registers in the reference, this function may be called recursively. The first time looking for an add of the first register, and if that fails, looking for an add of the second register. The FIRST_TRY parameter is used to only allow the parameters to be reversed once.
Make sure this reg appears only once in this insn.
Find the next use that is an inc.
Even though we know the next use is an add or inc because it came
from the reg_next_inc_use, we must still reparse. Next use was not an add. Look for one extra case. It could be
that we have:
*(a + b)
...= a;
...= b + a
if we reverse the operands in the mem ref we would
find this. Only try it once though. Need to assure that none of the operands of the inc instruction are
assigned to by the mem insn. Make sure that there is no insn that assigns to inc_insn.res
between the mem_insn and the inc_insn. For the post_add to work, the result_reg of the inc must not be
used in the mem insn since this will become the new index
register. The mem looks like *r0 and the rhs of the add has two
registers. The trick is that we are not going to increment r0,
we are going to increment the result of the add insn.
For this trick to be correct, the result reg of
the inc must be a valid addressing reg. We also need to make sure that the next use of
inc result is after the inc. Both the inc/add and the mem have a constant. Need to check
that the constants are ok. The mem insn is of the form *(a + b) where a and b are both
regs. It may be that in order to match the add or inc we
need to treat it as if it was *(b + a). It may also be that
the add is of the form a + c where c does not match b and
then we just abandon this. Make sure this reg appears only once in this insn.
For this trick to be correct, the result reg of the inc
must be a valid addressing reg. See comment above on find_inc (false) call.
Need to check that there are no assignments to b
before the add insn. All ok for the next step.
We know that mem_insn.reg0 must equal inc_insn.reg1
or else we would not have found the inc insn. See comment above on find_inc (false) call.
To have gotten here know that.
*(b + a)
... = (b + a)
We also know that the lhs of the inc is not b or a. We
need to make sure that there are no assignments to b
between the mem ref and the inc. Need to check that the next use of the add result is later than
add insn since this will be the reg incremented. See comment above on find_inc (false) call.
To have gotten here know that.
*(a + b)
... = (a + b)
We also know that the lhs of the inc is not b. We need to make
sure that there are no assignments to b between the mem ref and
the inc. When we found inc_insn, we were looking for the
next add or inc, not the next insn that used the
reg. Because we are going to increment the reg
in this form, we need to make sure that there
were no intervening uses of reg.
References dump_file.
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A recursive function that walks ADDRESS_OF_X to find all of the mem uses in pat that could be used as an auto inc or dec. It then calls FIND_INC for each one.
Match with *reg0.
Match with *(reg0 + c) where c is a const.
Match with *(reg0 + reg1).
If REG occurs inside a MEM used in a bit-field reference,
that is unacceptable. Time for some deep diving.
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Discover auto-inc auto-dec instructions.
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Return the next insn that uses (if reg_next_use is passed in NEXT_ARRAY) or defines (if reg_next_def is passed in NEXT_ARRAY) REGNO in BB.
Lazy about cleaning out the next_arrays.
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Prefer the simple form if both are available.
Prefer the simple form if both are available.
Prefer the simple form if both are available.
Prefer the simple form if both are available.
This is much simpler than the other cases because we do not look
for the reg1-reg2 case. Note that we do not have a INC_POS_REG
and INC_NEG_REG states. Most of the use of such states would be
on a target that had an R1 - R2 update address form.
There is the remote possibility that you could also catch a = a +
b; *(a - b) as a postdecrement of (a + b). However, it is
unclear if *(a - b) would ever be generated on a machine that did
not have that kind of addressing mode. The IA-64 and RS6000 will
not do this, and I cannot speak for any other. If any
architecture does have an a-b update for, these cases should be
added.
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Create a mov insn DEST_REG <- SRC_REG and insert it before NEXT_INSN.
References mem_insn::insn, mem_insn::mem_loc, new_cost(), and optimize_bb_for_speed_p().
| rtl_opt_pass* make_pass_inc_dec | ( | ) |
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Try to combine all incs and decs by constant values with memory references in BB.
This continue is deliberate. We do not want the uses of the
jump put into reg_next_use because it is not considered safe to
combine a preincrement with a jump. Does this instruction increment or decrement a register?
Cannot handle case where there are three separate regs
before a mem ref. Too many moves would be needed to be
profitable. We are only here if we are going to try a
HAVE_*_MODIFY_REG type transformation. c is a
reg and we must sure that the path from the
inc_insn to the mem_insn.insn is both def and use
clear of c because the inc insn is going to move
into the mem_insn.insn. If the inc insn was merged with a mem, the inc insn is gone
and there is noting to update. Need to update next use.
If we were successful, try again. There may have been several
opportunities that were interleaved. This is rare but
gcc.c-torture/compile/pr17273.c actually exhibits this. In this case, we must clear these vectors since the trick of
testing if the stale insn in the block will not work.
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Move dead note that match PATTERN to TO_INSN from FROM_INSN. We do not really care about moving any other notes from the inc or add insn. Moving the REG_EQUAL and REG_EQUIV is clearly wrong and it does not appear that there are any other kinds of relevant notes.
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Return true if INSN is of a form "a = b op c" where a and b are regs. op is + if c is a reg and +|- if c is a const. Fill in INC_INSN with what is found. This function is called in two contexts, if BEFORE_MEM is true, this is called for each insn in the basic block. If BEFORE_MEM is false, it is called for the instruction in the block that uses the index register for some memory reference that is currently being processed.
Result must be single reg.
Process a = b + c where c is a const.
Process a = b + c where c is a reg.
Reverse the two operands and turn *_ADD into *_INC since
a = c + a.
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Reverse the operands in a inc insn.
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Reverse the operands in a mem insn.
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Try to combine the instruction in INC_INSN with the instruction in MEM_INSN. First the form is determined using the DECISION_TABLE and the results of parsing the INC_INSN and the MEM_INSN. Assuming the form is ok, a prototype new address is built which is passed to ATTEMPT_CHANGE for final processing.
The width of the mem being accessed.
Cannot handle auto inc of the stack.
Look to see if the inc register is dead after the memory
reference. If it is, do not do the combination. Now get the form that we are generating.
References dump_file.
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The DECISION_TABLE that describes what form, if any, the increment or decrement will take. It is a three dimensional table. The first index is the type of constant or register found as the second operand of the inc insn. The second index is the type of constant or register found as the second operand of the memory reference (if no second operand exists, 0 is used). The third index is the form and location (relative to the mem reference) of inc insn.
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Tmp mem rtx for use in cost modeling.
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@verbatim
The following three arrays contain pointers to instructions. They are indexed by REGNO. At any point in the basic block where we are looking these three arrays contain, respectively, the next insn that uses REGNO, the next inc or add insn that uses REGNO and the next insn that sets REGNO.
The arrays are not cleared when we move from block to block so whenever an insn is retrieved from these arrays, it's block number must be compared with the current block.
1.8.1.1