#include "config.h"#include "system.h"#include "coretypes.h"#include "tm.h"#include "diagnostic-core.h"#include "rtl.h"#include "tree.h"#include "tm_p.h"#include "flags.h"#include "insn-config.h"#include "expr.h"#include "optabs.h"#include "recog.h"#include "langhooks.h"#include "df.h"#include "target.h"#include "expmed.h"
Data Structures | |
| struct | init_expmed_rtl |
Macros | |
| #define | EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0) |
Enumerations | |
| enum | mult_variant { basic_variant, negate_variant, add_variant } |
Functions | |
| static void | store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, rtx) |
| static void | store_split_bit_field (rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, rtx) |
| static rtx | extract_fixed_bit_field (enum machine_mode, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, rtx, int) |
| static rtx | mask_rtx (enum machine_mode, int, int, int) |
| static rtx | lshift_value (enum machine_mode, unsigned HOST_WIDE_INT, int) |
| static rtx | extract_split_bit_field (rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, int) |
| static void | do_cmp_and_jump (rtx, rtx, enum rtx_code, enum machine_mode, rtx) |
| static rtx | expand_smod_pow2 (enum machine_mode, rtx, HOST_WIDE_INT) |
| static rtx | expand_sdiv_pow2 (enum machine_mode, rtx, HOST_WIDE_INT) |
| static void | init_expmed_one_conv (struct init_expmed_rtl *all, enum machine_mode to_mode, enum machine_mode from_mode, bool speed) |
| static void | init_expmed_one_mode (struct init_expmed_rtl *all, enum machine_mode mode, int speed) |
| void | init_expmed () |
| rtx | negate_rtx () |
| static rtx | narrow_bit_field_mem (rtx mem, enum machine_mode mode, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, unsigned HOST_WIDE_INT *new_bitnum) |
| static rtx | adjust_bit_field_mem_for_reg (enum extraction_pattern pattern, rtx op0, HOST_WIDE_INT bitsize, HOST_WIDE_INT bitnum, unsigned HOST_WIDE_INT bitregion_start, unsigned HOST_WIDE_INT bitregion_end, enum machine_mode fieldmode, unsigned HOST_WIDE_INT *new_bitnum) |
| static bool | lowpart_bit_field_p (unsigned HOST_WIDE_INT bitnum, unsigned HOST_WIDE_INT bitsize, enum machine_mode struct_mode) |
| static bool | simple_mem_bitfield_p (rtx op0, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, enum machine_mode mode) |
| static bool | store_bit_field_using_insv (const extraction_insn *insv, rtx op0, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, rtx value) |
| static bool | store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, unsigned HOST_WIDE_INT bitregion_start, unsigned HOST_WIDE_INT bitregion_end, enum machine_mode fieldmode, rtx value, bool fallback_p) |
| void | store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, unsigned HOST_WIDE_INT bitregion_start, unsigned HOST_WIDE_INT bitregion_end, enum machine_mode fieldmode, rtx value) |
| static rtx | convert_extracted_bit_field (rtx x, enum machine_mode mode, enum machine_mode tmode, bool unsignedp) |
| static rtx | extract_bit_field_using_extv (const extraction_insn *extv, rtx op0, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target, enum machine_mode mode, enum machine_mode tmode) |
| static rtx | extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target, enum machine_mode mode, enum machine_mode tmode, bool fallback_p) |
| rtx | extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target, enum machine_mode mode, enum machine_mode tmode) |
| static rtx | mask_rtx () |
| rtx | extract_low_bits () |
| void | expand_inc () |
| void | expand_dec () |
| static rtx | expand_shift_1 (enum tree_code code, enum machine_mode mode, rtx shifted, rtx amount, rtx target, int unsignedp) |
| rtx | expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted, int amount, rtx target, int unsignedp) |
| rtx | expand_variable_shift (enum tree_code code, enum machine_mode mode, rtx shifted, tree amount, rtx target, int unsignedp) |
| static void | synth_mult (struct algorithm *, unsigned HOST_WIDE_INT, const struct mult_cost *, enum machine_mode mode) |
| static bool | choose_mult_variant (enum machine_mode, HOST_WIDE_INT, struct algorithm *, enum mult_variant *, int) |
| static rtx | expand_mult_const (enum machine_mode, rtx, HOST_WIDE_INT, rtx, const struct algorithm *, enum mult_variant) |
| static unsigned HOST_WIDE_INT | invert_mod2n (unsigned HOST_WIDE_INT, int) |
| static rtx | extract_high_half (enum machine_mode, rtx) |
| static rtx | expmed_mult_highpart (enum machine_mode, rtx, rtx, rtx, int, int) |
| static rtx | expmed_mult_highpart_optab (enum machine_mode, rtx, rtx, rtx, int, int) |
| rtx | expand_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, int unsignedp) |
| int | mult_by_coeff_cost () |
| rtx | expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, int unsignedp, optab this_optab) |
| unsigned HOST_WIDE_INT | choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision, unsigned HOST_WIDE_INT *multiplier_ptr, int *post_shift_ptr, int *lgup_ptr) |
| static unsigned HOST_WIDE_INT | invert_mod2n () |
| rtx | expand_mult_highpart_adjust (enum machine_mode mode, rtx adj_operand, rtx op0, rtx op1, rtx target, int unsignedp) |
| static rtx | extract_high_half () |
| static rtx | expand_smod_pow2 () |
| static rtx | expand_sdiv_pow2 () |
| rtx | expand_divmod (int rem_flag, enum tree_code code, enum machine_mode mode, rtx op0, rtx op1, rtx target, int unsignedp) |
| tree | make_tree () |
| rtx | expand_and () |
| static rtx | emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, enum machine_mode mode, enum machine_mode compare_mode, int unsignedp, rtx x, rtx y, int normalizep, enum machine_mode target_mode) |
| static rtx | emit_store_flag_1 (rtx target, enum rtx_code code, rtx op0, rtx op1, enum machine_mode mode, int unsignedp, int normalizep, enum machine_mode target_mode) |
| rtx | emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1, enum machine_mode mode, int unsignedp, int normalizep) |
| rtx | emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1, enum machine_mode mode, int unsignedp, int normalizep) |
Variables | |
| struct target_expmed | default_target_expmed |
Macro Definition Documentation
| #define EXACT_POWER_OF_2_OR_ZERO_P | ( | x | ) | (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0) |
Test whether a value is zero of a power of two.
Referenced by expand_mult().
Enumeration Type Documentation
| enum mult_variant |
Function Documentation
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The caller wants to perform insertion or extraction PATTERN on a bitfield of size BITSIZE at BITNUM bits into memory operand OP0. BITREGION_START and BITREGION_END are as for store_bit_field and FIELDMODE is the natural mode of the field.
Search for a mode that is compatible with the memory access restrictions and (where applicable) with a register insertion or extraction. Return the new memory on success, storing the adjusted bit position in *NEW_BITNUM. Return null otherwise.
We can use a memory in BEST_MODE. See whether this is true for any wider modes. All other things being equal, we prefer to use the widest mode possible because it tends to expose more CSE opportunities.
Limit the search to the mode required by the corresponding
register insertion or extraction instruction, if any.
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Find the cheapest way of multiplying a value of mode MODE by VAL. Try three variations:
- a shift/add sequence based on VAL itself - a shift/add sequence based on -VAL, followed by a negation - a shift/add sequence based on VAL - 1, followed by an addition.
Return true if the cheapest of these cost less than MULT_COST, describing the algorithm in *ALG and final fixup in *VARIANT.
Fail quickly for impossible bounds.
Ensure that mult_cost provides a reasonable upper bound. Any constant multiplication can be performed with less than 2 * bits additions.
This works only if the inverted value actually fits in an `unsigned int'
This proves very useful for division-by-constant.
Referenced by expand_mult().
| unsigned HOST_WIDE_INT choose_multiplier | ( | unsigned HOST_WIDE_INT | d, |
| int | n, | ||
| int | precision, | ||
| unsigned HOST_WIDE_INT * | multiplier_ptr, | ||
| int * | post_shift_ptr, | ||
| int * | lgup_ptr | ||
| ) |
Choose a minimal N + 1 bit approximation to 1/D that can be used to replace division by D, and put the least significant N bits of the result in *MULTIPLIER_PTR and return the most significant bit.
The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the needed precision is in PRECISION (should be <= N).
PRECISION should be as small as possible so this function can choose multiplier more freely.
The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that is to be used for a final right shift is placed in *POST_SHIFT_PTR.
Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR), where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier.
lgup = ceil(log2(divisor));
We could handle this with some effort, but this case is much better handled directly with a scc insn, so rely on caller using that.
mlow = 2^(N + lgup)/d
mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d
Assert that mlow < mhigh.
If precision == N, then mlow, mhigh exceed 2^N (but they do not exceed 2^(N+1)).
Reduce to lowest terms.
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A subroutine of extract_bit_field_1 that converts return value X to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments to extract_bit_field.
If the x mode is not a scalar integral, first convert to the integer mode of that size and then access it as a floating-point value via a SUBREG.
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Perform possibly multi-word comparison and conditional jump to LABEL if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is now a thin wrapper around do_compare_rtx_and_jump.
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Helper function for emit_store_flag.
If we are converting to a wider mode, first convert to TARGET_MODE, then normalize. This produces better combining opportunities on machines that have a SIGN_EXTRACT when we are testing a single bit. This mostly benefits the 68k. If STORE_FLAG_VALUE does not have the sign bit set when interpreted in MODE, we can do this conversion as unsigned, which is usually more efficient.
If we want to keep subexpressions around, don't reuse our last target.
Now normalize to the proper value in MODE. Sometimes we don't have to do anything.
STORE_FLAG_VALUE might be the most negative number, so write the comparison this way to avoid a compiler-time warning.
We don't want to use STORE_FLAG_VALUE < 0 below since this makes it hard to use a value of just the sign bit due to ANSI integer constant typing rules.
If we were converting to a smaller mode, do the conversion now.
References can_compare_p(), ccp_store_flag, delete_insns_since(), emit_store_flag_1(), expand_binop(), gcc_assert, GEN_INT, gen_int_mode(), get_last_insn(), GET_MODE, GET_MODE_CLASS, HONOR_NANS, HONOR_SNANS, last, NULL_RTX, OPTAB_WIDEN, optimize_insn_for_speed_p(), reverse_condition_maybe_unordered(), rtx_cost(), split_comparison(), STORE_FLAG_VALUE, and val_signbit_p().
| rtx emit_store_flag | ( | rtx | target, |
| enum rtx_code | code, | ||
| rtx | op0, | ||
| rtx | op1, | ||
| enum machine_mode | mode, | ||
| int | unsignedp, | ||
| int | normalizep | ||
| ) |
Emit a store-flags instruction for comparison CODE on OP0 and OP1 and storing in TARGET. Normally return TARGET. Return 0 if that cannot be done.
MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If it is VOIDmode, they cannot both be CONST_INT.
UNSIGNEDP is for the case where we have to widen the operands to perform the operation. It says to use zero-extension.
NORMALIZEP is 1 if we should convert the result to be either zero or one. Normalize is -1 if we should convert the result to be either zero or -1. If NORMALIZEP is zero, the result will be left "raw" out of the scc insn.
If we reached here, we can't do this with a scc insn, however there are some comparisons that can be done in other ways. Don't do any of these cases if branches are very cheap.
See what we need to return. We can only return a 1, -1, or the sign bit.
If optimizing, use different pseudo registers for each insn, instead of reusing the same pseudo. This leads to better CSE, but slows down the compiler, since there are more pseudos
For floating-point comparisons, try the reverse comparison or try changing the "orderedness" of the comparison.
For the reverse comparison, use either an addition or a XOR.
Cannot split ORDERED and UNORDERED, only try the above trick.
If there are no NaNs, the first comparison should always fall through.
Effectively change the comparison to the other one. The remaining tricks only apply to integer comparisons.
If this is an equality comparison of integers, we can try to exclusive-or (or subtract) the two operands and use a recursive call to try the comparison with zero. Don't do any of these cases if branches are very cheap.
For integer comparisons, try the reverse comparison. However, for small X and if we'd have anyway to extend, implementing "X != 0" as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0".
Again, for the reverse comparison, use either an addition or a XOR.
Some other cases we can do are EQ, NE, LE, and GT comparisons with the constant zero. Reject all other comparisons at this point. Only do LE and GT if branches are expensive since they are expensive on 2-operand machines.
Try to put the result of the comparison in the sign bit. Assume we can't do the necessary operation below.
To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has the sign bit set.
This is destructive, so SUBTARGET can't be OP0.
To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the number of bits in the mode of OP0, minus one.
For EQ or NE, one way to do the comparison is to apply an operation
that converts the operand into a positive number if it is nonzero
or zero if it was originally zero. Then, for EQ, we subtract 1 and
for NE we negate. This puts the result in the sign bit. Then we
normalize with a shift, if needed.
Two operations that can do the above actions are ABS and FFS, so try
them. If that doesn't work, and MODE is smaller than a full word,
we can use zero-extension to the wider mode (an unsigned conversion)
as the operation. Note that ABS doesn't yield a positive number for INT_MIN, but
that is compensated by the subsequent overflow when subtracting
one / negating. If we couldn't do it that way, for NE we can "or" the two's complement
of the value with itself. For EQ, we take the one's complement of
that "or", which is an extra insn, so we only handle EQ if branches
are expensive.
Referenced by expand_mult_highpart_adjust().
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A subroutine of emit_store_flag only including "tricks" that do not need a recursive call. These are kept separate to avoid infinite loops.
If one operand is constant, make it the second one. Only do this if the other operand is not constant as well.
For some comparisons with 1 and -1, we can convert this to comparisons with zero. This will often produce more opportunities for store-flag insns.
If we are comparing a double-word integer with zero or -1, we can convert the comparison into one involving a single word.
Do a logical OR or AND of the two words and compare the
result. If testing the sign bit, can just test on high word.
If this is A < 0 or A >= 0, we can do this by taking the ones complement of A (for GE) and shifting the sign bit to the low bit.
If the result is to be wider than OP0, it is best to convert it
first. If it is to be narrower, it is *incorrect* to convert it
first. If we are supposed to produce a 0/1 value, we want to do
a logical shift from the sign bit to the low-order bit; for
a -1/0 value, we do an arithmetic shift.
Referenced by emit_cstore().
| rtx emit_store_flag_force | ( | rtx | target, |
| enum rtx_code | code, | ||
| rtx | op0, | ||
| rtx | op1, | ||
| enum machine_mode | mode, | ||
| int | unsignedp, | ||
| int | normalizep | ||
| ) |
Like emit_store_flag, but always succeeds.
First see if emit_store_flag can do the job.
If this failed, we have to do this with set/compare/jump/set code. For foo != 0, if foo is in OP0, just replace it with 1 if nonzero.
Jump in the right direction if the target cannot implement CODE but can jump on its reverse condition.
Canonicalize to UNORDERED for the libcall.
| rtx expand_and | ( | ) |
Compute the logical-and of OP0 and OP1, storing it in TARGET and returning TARGET.
If TARGET is 0, a pseudo-register or constant is returned.
| void expand_dec | ( | ) |
Subtract DEC from TARGET.
| rtx expand_divmod | ( | int | rem_flag, |
| enum tree_code | code, | ||
| enum machine_mode | mode, | ||
| rtx | op0, | ||
| rtx | op1, | ||
| rtx | target, | ||
| int | unsignedp | ||
| ) |
Emit the code to divide OP0 by OP1, putting the result in TARGET if that is convenient, and returning where the result is. You may request either the quotient or the remainder as the result; specify REM_FLAG nonzero to get the remainder.
CODE is the expression code for which kind of division this is; it controls how rounding is done. MODE is the machine mode to use. UNSIGNEDP nonzero means do unsigned division. ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI and then correct it by or'ing in missing high bits if result of ANDI is nonzero. For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result. This could optimize to a bfexts instruction. But C doesn't use these operations, so their optimizations are left for later. ??? For modulo, we don't actually need the highpart of the first product, the low part will do nicely. And for small divisors, the second multiply can also be a low-part only multiply or even be completely left out. E.g. to calculate the remainder of a division by 3 with a 32 bit multiply, multiply with 0x55555556 and extract the upper two bits; the result is exact for inputs up to 0x1fffffff. The input range can be reduced by using cross-sum rules. For odd divisors >= 3, the following table gives right shift counts so that if a number is shifted by an integer multiple of the given amount, the remainder stays the same: 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20, 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0, 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0, 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33, 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
Cross-sum rules for even numbers can be derived by leaving as many bits to the right alone as the divisor has zeros to the right. E.g. if x is an unsigned 32 bit number: (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
We shouldn't be called with OP1 == const1_rtx, but some of the code below will malfunction if we are, so check here and handle the special case if so.
When dividing by -1, we could get an overflow. negv_optab can handle overflows.
Don't use the function value register as a target
since we have to read it as well as write it,
and function-inlining gets confused by this. Don't clobber an operand while doing a multi-step calculation.
Get the mode in which to perform this computation. Normally it will be MODE, but sometimes we can't do the desired operation in MODE. If so, pick a wider mode in which we can do the operation. Convert to that mode at the start to avoid repeated conversions. First see what operations we need. These depend on the expression we are evaluating. (We assume that divxx3 insns exist under the same conditions that modxx3 insns and that these insns don't normally fail. If these assumptions are not correct, we may generate less efficient code in some cases.) Then see if we find a mode in which we can open-code that operation (either a division, modulus, or shift). Finally, check for the smallest mode for which we can do the operation with a library call.
We might want to refine this now that we have division-by-constant optimization. Since expmed_mult_highpart tries so many variants, it is not straightforward to generalize this. Maybe we should make an array of possible modes in init_expmed? Save this for GCC 2.7.
If we still couldn't find a mode, use MODE, but expand_binop will probably die.
Only deduct something for a REM if the last divide done was for a different constant. Then set the constant of the last divide.
Now convert to the best mode to use.
convert_modes may have placed op1 into a register, so we
must recompute the following. If one of the operands is a volatile MEM, copy it into a register.
If we need the remainder or if OP1 is constant, we need to put OP0 in a register in case it has any queued subexpressions.
Promote floor rounding to trunc rounding for unsigned operations.
Most significant bit of divisor is set; emit an scc
insn. Find a suitable multiplier and right shift count
instead of multiplying with D. If the suggested multiplier is more than SIZE bits,
we can do better for even divisors, using an
initial right shift. Since d might be INT_MIN, we have to cast to
unsigned HOST_WIDE_INT before negating to avoid
undefined signed overflow. n rem d = n rem -d
This case is not handled correctly below.
We assume that cheap metric is true if the
optab has an expander for this mode. We have computed OP0 / abs(OP1). If OP1 is negative,
negate the quotient. We will come here only for signed operations.
We could just as easily deal with negative constants here,
but it does not seem worth the trouble for GCC 2.6. Try using an instruction that produces both the quotient and
remainder, using truncation. We can easily compensate the quotient
or remainder to get floor rounding, once we have the remainder.
Notice that we compute also the final remainder value here,
and return the result right away. This could be computed with a branch-less sequence.
Save that for later. No luck with division elimination or divmod. Have to do it
by conditionally adjusting op0 *and* the result. Try using an instruction that produces both the quotient and
remainder, using truncation. We can easily compensate the
quotient or remainder to get ceiling rounding, once we have the
remainder. Notice that we compute also the final remainder
value here, and return the result right away. This could be computed with a branch-less sequence.
Save that for later. No luck with division elimination or divmod. Have to do it
by conditionally adjusting op0 *and* the result. This is extremely similar to the code for the unsigned case
above. For 2.7 we should merge these variants, but for
2.6.1 I don't want to touch the code for unsigned since that
get used in C. The signed case will only be used by other
languages (Ada). Try using an instruction that produces both the quotient and
remainder, using truncation. We can easily compensate the
quotient or remainder to get ceiling rounding, once we have the
remainder. Notice that we compute also the final remainder
value here, and return the result right away. This could be computed with a branch-less sequence.
Save that for later. No luck with division elimination or divmod. Have to do it
by conditionally adjusting op0 *and* the result. Try to produce the remainder without producing the quotient.
If we seem to have a divmod pattern that does not require widening,
don't try widening here. We should really have a WIDEN argument
to expand_twoval_binop, since what we'd really like to do here is
1) try a mod insn in compute_mode
2) try a divmod insn in compute_mode
3) try a div insn in compute_mode and multiply-subtract to get
remainder
4) try the same things with widening allowed. No luck there. Can we do remainder and divide at once
without a library call? Produce the quotient. Try a quotient insn, but not a library call.
If we have a divmod in this mode, use it in preference to widening
the div (for this test we assume it will not fail). Note that optab2
is set to the one of the two optabs that the call below will use. No luck there. Try a quotient-and-remainder insn,
keeping the quotient alone. Still no luck. If we are not computing the remainder,
use a library call for the quotient. No divide instruction either. Use library for remainder.
No remainder function. Try a quotient-and-remainder
function, keeping the remainder. We divided. Now finish doing X - Y * (X / Y).
| void expand_inc | ( | ) |
Add INC into TARGET.
Perform a multiplication and return an rtx for the result. MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); TARGET is a suggestion for where to store the result (an rtx).
We check specially for a constant integer as OP1. If you want this check for OP0 as well, then before calling you should swap the two operands if OP0 would be constant.
For vectors, there are several simplifications that can be made if all elements of the vector constant are identical.
These are the operations that are potentially turned into
a sequence of shifts and additions. synth_mult does an `unsigned int' multiply. As long as the mode is
less than or equal in size to `unsigned int' this doesn't matter.
If the mode is larger than `unsigned int', then synth_mult works
only if the constant value exactly fits in an `unsigned int' without
any truncation. This means that multiplying by negative values does
not work; results are off by 2^32 on a 32 bit machine. If we are multiplying in DImode, it may still be a win
to try to work with shifts and adds. We used to test optimize here, on the grounds that it's better to
produce a smaller program when -O is not used. But this causes
such a terrible slowdown sometimes that it seems better to always
use synth_mult. Special case powers of two.
Attempt to handle multiplication of DImode values by negative
coefficients, by performing the multiplication by a positive
multiplier and then inverting the result. Its safe to use -coeff even for INT_MIN, as the
result is interpreted as an unsigned coefficient.
Exclude cost of op0 from max_cost to match the cost
calculation of the synth_mult. Special case powers of two.
Exclude cost of op0 from max_cost to match the cost
calculation of the synth_mult. Expand x*2.0 as x+x.
This used to use umul_optab if unsigned, but for non-widening multiply there is no difference between signed and unsigned.
References choose_mult_variant(), CONST_INT_P, convert_modes(), convert_to_mode(), EXACT_POWER_OF_2_OR_ZERO_P, expand_binop(), expand_mult_const(), expand_shift(), floor_log2(), GET_MODE, HWI_COMPUTABLE_MODE_P, INTVAL, mul_widen_cost(), OPTAB_LIB_WIDEN, and optimize_insn_for_speed_p().
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A subroutine of expand_mult, used for constant multiplications. Multiply OP0 by VAL in mode MODE, storing the result in TARGET if convenient. Use the shift/add sequence described by ALG and apply the final fixup specified by VARIANT.
Avoid referencing memory over and over and invalid sharing on SUBREGs.
ACCUM starts out either as OP0 or as a zero, depending on the first operation.
REG_EQUAL note will be attached to the following insn.
Write a REG_EQUAL note on the last insn so that we can cse
multiplication sequences. Note that if ACCUM is a SUBREG,
we've set the inner register and must properly indicate that. Compare only the bits of val and val_so_far that are significant in the result mode, to avoid sign-/zero-extension confusion.
Referenced by expand_mult().
| rtx expand_mult_highpart_adjust | ( | enum machine_mode | mode, |
| rtx | adj_operand, | ||
| rtx | op0, | ||
| rtx | op1, | ||
| rtx | target, | ||
| int | unsignedp | ||
| ) |
Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to become signed.
The result is put in TARGET if that is convenient.
MODE is the mode of operation.
References const0_rtx, emit_store_flag(), floor_log2(), force_reg(), GEN_INT, gen_reg_rtx(), GET_MODE_BITSIZE, HOST_WIDE_INT, optimize_insn_for_speed_p(), and shift.
Referenced by expand_widening_mult().
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Expand signed division of OP0 by a power of two D in mode MODE. This routine is only called for positive values of D.
| rtx expand_shift | ( | enum tree_code | code, |
| enum machine_mode | mode, | ||
| rtx | shifted, | ||
| int | amount, | ||
| rtx | target, | ||
| int | unsignedp | ||
| ) |
Output a shift instruction for expression code CODE, with SHIFTED being the rtx for the value to shift, and AMOUNT the amount to shift by. Store the result in the rtx TARGET, if that is convenient. If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. Return the rtx for where the value is.
References alg_add_t_m2, alg_shift, and alg_sub_t_m2.
Referenced by expand_mult(), and mem_overlaps_already_clobbered_arg_p().
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Output a shift instruction for expression code CODE, with SHIFTED being the rtx for the value to shift, and AMOUNT the rtx for the amount to shift by. Store the result in the rtx TARGET, if that is convenient. If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. Return the rtx for where the value is.
Determine whether the shift/rotate amount is a vector, or scalar. If the shift amount is a vector, use the vector/vector shift patterns.
Previously detected shift-counts computed by NEGATE_EXPR and shifted in the other direction; but that does not work on all machines.
Canonicalize rotates by constant amount. If op1 is bitsize / 2, prefer left rotation, if op1 is from bitsize / 2 + 1 to bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1 amount instead.
Check whether its cheaper to implement a left shift by a constant bit count by a sequence of additions.
Widening does not work for rotation.
If we have been unable to open-code this by a rotation,
do it as the IOR of two shifts. I.e., to rotate A
by N bits, compute
(A << N) | ((unsigned) A >> ((-N) & (C - 1)))
where C is the bitsize of A.
It is theoretically possible that the target machine might
not be able to perform either shift and hence we would
be making two libcalls rather than just the one for the
shift (similarly if IOR could not be done). We will allow
this extremely unlikely lossage to avoid complicating the
code below. Do arithmetic shifts.
Also, if we are going to widen the operand, we can just as well
use an arithmetic right-shift instead of a logical one. If trying to widen a log shift to an arithmetic shift,
don't accept an arithmetic shift of the same size. Arithmetic shift
We used to try extzv here for logical right shifts, but that was
only useful for one machine, the VAX, and caused poor code
generation there for lshrdi3, so the code was deleted and a
define_expand for lshrsi3 was added to vax.md.
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Expand signed modulus of OP0 by a power of two D in mode MODE.
Avoid conditional branches when they're expensive.
Use the rtx_cost of a LSHIFTRT instruction to determine
which instruction sequence to use. If logical right shifts
are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
use a LSHIFTRT, 1 ADD, 1 SUB and an AND. Mask contains the mode's signbit and the significant bits of the modulus. By including the signbit in the operation, many targets can avoid an explicit compare operation in the following comparison against zero.
| rtx expand_variable_shift | ( | enum tree_code | code, |
| enum machine_mode | mode, | ||
| rtx | shifted, | ||
| tree | amount, | ||
| rtx | target, | ||
| int | unsignedp | ||
| ) |
Output a shift instruction for expression code CODE, with SHIFTED being the rtx for the value to shift, and AMOUNT the tree for the amount to shift by. Store the result in the rtx TARGET, if that is convenient. If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. Return the rtx for where the value is.
| rtx expand_widening_mult | ( | enum machine_mode | mode, |
| rtx | op0, | ||
| rtx | op1, | ||
| rtx | target, | ||
| int | unsignedp, | ||
| optab | this_optab | ||
| ) |
Perform a widening multiplication and return an rtx for the result. MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); TARGET is a suggestion for where to store the result (an rtx). THIS_OPTAB is the optab we should use, it must be either umul_widen_optab or smul_widen_optab.
We check specially for a constant integer as OP1, comparing the cost of a widening multiply against the cost of a sequence of shifts and adds.
Special case powers of two.
Exclude cost of op0 from max_cost to match the cost
calculation of the synth_mult.
References BITS_PER_WORD, expand_binop(), expand_mult_highpart_adjust(), extract_high_half(), gcc_assert, gen_int_mode(), GET_MODE_BITSIZE, GET_MODE_WIDER_MODE, INTVAL, mul_cost(), mul_highpart_cost(), mul_widen_cost(), OPTAB_DIRECT, optab_handler(), OPTAB_WIDEN, optimize_insn_for_speed_p(), SCALAR_FLOAT_MODE_P, shift_cost(), and widening_optab_handler().
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Emit code to multiply OP0 and OP1 (where OP1 is an integer constant), putting the high half of the result in TARGET if that is convenient, and return where the result is. If the operation can not be performed, 0 is returned.
MODE is the mode of operation and result.
UNSIGNEDP nonzero means unsigned multiply.
MAX_COST is the total allowed cost for the expanded RTL.
We can't support modes wider than HOST_BITS_PER_INT.
We can't optimize modes wider than BITS_PER_WORD. ??? We might be able to perform double-word arithmetic if mode == word_mode, however all the cost calculations in synth_mult etc. assume single-word operations.
Check whether we try to multiply by a negative constant.
See whether shift/add multiplication is cheap enough.
See whether the specialized multiplication optabs are
cheaper than the shift/add version. Adjust result for signedness.
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Like expmed_mult_highpart, but only consider using a multiplication optab. OP1 is an rtx for the constant operand.
Firstly, try using a multiplication insn that only generates the needed high part of the product, and in the sign flavor of unsignedp.
Secondly, same as above, but use sign flavor opposite of unsignedp. Need to adjust the result after the multiplication.
We used the wrong signedness. Adjust the result.
Try widening multiplication.
Try widening the mode and perform a non-widening multiplication.
We need to widen the operands, for example to ensure the
constant multiplier is correctly sign or zero extended.
Use a sequence to clean-up any instructions emitted by
the conversions if things don't work out. Try widening multiplication of opposite signedness, and adjust.
We used the wrong signedness. Adjust the result.
| rtx extract_bit_field | ( | rtx | str_rtx, |
| unsigned HOST_WIDE_INT | bitsize, | ||
| unsigned HOST_WIDE_INT | bitnum, | ||
| int | unsignedp, | ||
| rtx | target, | ||
| enum machine_mode | mode, | ||
| enum machine_mode | tmode | ||
| ) |
Generate code to extract a byte-field from STR_RTX containing BITSIZE bits, starting at BITNUM, and put it in TARGET if possible (if TARGET is nonzero). Regardless of TARGET, we return the rtx for where the value is placed.
STR_RTX is the structure containing the byte (a REG or MEM). UNSIGNEDP is nonzero if this is an unsigned bit field. MODE is the natural mode of the field value once extracted. TMODE is the mode the caller would like the value to have; but the value may be returned with type MODE instead.
If a TARGET is specified and we can store in it at no extra cost, we do so, and return TARGET. Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred if they are equally easy.
Referenced by emit_group_load_1().
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A subroutine of extract_bit_field, with the same arguments. If FALLBACK_P is true, fall back to extract_fixed_bit_field if we can find no other means of implementing the operation. if FALLBACK_P is false, return NULL instead.
If we have an out-of-bounds access to a register, just return an uninitialized register of the required mode. This can occur if the source code contains an out-of-bounds access to a small array.
We're trying to extract a full register from itself.
See if we can get a better vector mode before extracting.
Use vec_extract patterns for extracting parts of vectors whenever available.
Make sure we are playing with integral modes. Pun with subregs if we aren't.
If we got a SUBREG, force it into a register since we
aren't going to be able to do another SUBREG on it. ??? We currently assume TARGET is at least as big as BITSIZE. If that's wrong, the solution is to test for it and set TARGET to 0 if needed.
If the bitfield is volatile, we need to make sure the access remains on a type-aligned boundary.
Only scalar integer modes can be converted via subregs. There is an additional problem for FP modes here in that they can have a precision which is different from the size. mode_for_size uses precision, but we want a mode based on the size, so we must avoid calling it for FP modes.
Extraction of a full MODE1 value can be done with a subreg as long as the least significant bit of the value is the least significant bit of either OP0 or a word of OP0.
Extraction of a full MODE1 value can be done with a load as long as the field is on a byte boundary and is sufficiently aligned.
Handle fields bigger than a word.
Here we transfer the words of the field
in the order least significant first.
This is because the most significant word is the one which may
be less than full. Indicate for flow that the entire target reg is being set.
If I is 0, use the low-order word in both field and target;
if I is 1, use the next to lowest word; and so on. Word number in TARGET to use.
Offset from start of field in OP0.
Unless we've filled TARGET, the upper regs in a multi-reg value
need to be zero'd out. Signed bit field: sign-extend with two arithmetic shifts.
If OP0 is a multi-word register, narrow it to the affected word. If the region spans two words, defer to extract_split_bit_field.
From here on we know the desired field is smaller than a word. If OP0 is a register, it too fits within a word.
??? We could limit the structure size to the part of OP0 that
contains the field, with appropriate checks for endianness
and TRULY_NOOP_TRUNCATION. If OP0 is a memory, try copying it to a register and seeing if a cheap register alternative is available.
Do not use extv/extzv for volatile bitfields when
-fstrict-volatile-bitfields is in effect. Try loading part of OP0 into a register and extracting the
bitfield from that. Find a correspondingly-sized integer field, so we can apply shifts and masks to it.
Should probably push op0 out to memory and then do a load.
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Try to use an ext(z)v pattern to extract a field from OP0. Return the extracted value on success, otherwise return null. EXT_MODE is the mode of the extraction and the other arguments are as for extract_bit_field.
Get a reference to the first byte of the field.
Convert from counting within OP0 to counting in EXT_MODE.
If op0 is a register, we need it in EXT_MODE to make it
acceptable to the format of ext(z)v. If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count "backwards" from the size of the unit we are extracting from. Otherwise, we count bits from the most significant on a BYTES/BITS_BIG_ENDIAN machine.
Don't use LHS paradoxical subreg if explicit truncation is needed
between the mode of the extraction (word_mode) and the target
mode. Instead, create a temporary and use convert_move to set
the target.
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Use shifts and boolean operations to extract a field of BITSIZE bits from bit BITNUM of OP0.
UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). If TARGET is nonzero, attempts to store the value there and return TARGET, but this is not guaranteed. If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
Get the proper mode to use for this field. We want a mode that
includes the entire field. If such a mode would be larger than
a word, we won't be doing the extraction the normal way.
The only way this should occur is if the field spans word
boundaries. If we're accessing a volatile MEM, we can't apply BIT_OFFSET
if it results in a multi-word access where we otherwise wouldn't
have one. So, check for that case here. If the target doesn't support unaligned access, give up and
split the access into two. Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode) for invalid input, such as extract equivalent of f5 from gcc.dg/pr48335-2.c.
BITNUM is the distance between our msb and that of OP0. Convert it to the distance from the lsb.
Now BITNUM is always the distance between the field's lsb and that of OP0. We have reduced the big-endian case to the little-endian case.
If the field does not already start at the lsb,
shift it so it does. Maybe propagate the target for the shift.
Convert the value to the desired mode.
Unless the msb of the field used to be the msb when we shifted,
mask out the upper bits. To extract a signed bit-field, first shift its msb to the msb of the word, then arithmetic-shift its lsb to the lsb of the word.
Find the narrowest integer mode that contains the field.
Maybe propagate the target for the shift.
Referenced by expand_widening_mult().
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Subroutine of expmed_mult_highpart. Return the MODE high part of OP.
References expand_binop(), gen_int_mode(), NULL_RTX, and OPTAB_LIB_WIDEN.
| rtx extract_low_bits | ( | ) |
Try to read the low bits of SRC as an rvalue of mode MODE, preserving the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than MODE, fill the upper bits with zeros. Fail if the layout of either mode is unknown (as for CC modes) or if the extraction would involve unprofitable mode punning. Return the value on success, otherwise return null.
This is different from gen_lowpart* in these respects:
- the returned value must always be considered an rvalue
- when MODE is wider than SRC_MODE, the extraction involves a zero extension
- when MODE is smaller than SRC_MODE, the extraction involves a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
In other words, this routine performs a computation, whereas the gen_lowpart* routines are conceptually lvalue or rvalue subreg operations.
simplify_gen_subreg can't be used here, as if simplify_subreg fails, it will happily create (subreg (symbol_ref)) or similar invalid SUBREGs.
References GEN_INT, GET_MODE_BITSIZE, and INTVAL.
Referenced by find_shift_sequence().
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Extract a bit field that is split across two words and return an RTX for the result.
OP0 is the REG, SUBREG or MEM rtx for the first of the two words. BITSIZE is the field width; BITPOS, position of its first bit, in the word. UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that much at a time.
THISSIZE must not overrun a word boundary. Otherwise,
extract_fixed_bit_field will call us again, and we will mutually
recurse forever. If OP0 is a register, then handle OFFSET here.
When handling multiword bitfields, extract_bit_field may pass
down a word_mode SUBREG of a larger REG for a bitfield that actually
crosses a word boundary. Thus, for a SUBREG, we must find
the current word starting from the base register. Extract the parts in bit-counting order,
whose meaning is determined by BYTES_PER_UNIT.
OFFSET is in UNITs, and UNIT is in bits. Shift this part into place for the result.
Combine the parts with bitwise or. This works
because we extracted each part as an unsigned bit field. Unsigned bit field: we are done.
Signed bit field: sign-extend with two arithmetic shifts.
References force_reg(), gen_rtx_SUBREG(), GET_MODE, NULL_RTX, simplify_subreg(), subreg_lowpart_offset(), and validate_subreg().
| void init_expmed | ( | void | ) |
In expmed.c
Avoid using hard regs in ways which may be unsupported.
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We're given no information about the true size of a partial integer, only the size of the "full" integer it requires for storage. For comparison purposes here, reduce the bit size by one in that case.
Assume cost of zero-extend and sign-extend is the same.
References GET_MODE_BITSIZE, GET_MODE_CLASS, PUT_MODE, init_expmed_rtl::reg, set_convert_cost(), set_src_cost(), init_expmed_rtl::trunc, and init_expmed_rtl::zext.
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Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is congruent to 1 (mod 2**N).
Solve x*y == 1 (mod 2^n), where x is odd. Return y.
The algorithm notes that the choice y = x satisfies x*y == 1 mod 2^3, since x is assumed odd. Each iteration doubles the number of bits of significance in y.
References add_cost().
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Return true if a bitfield of size BITSIZE at bit number BITNUM within a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg offset is then BITNUM / BITS_PER_UNIT.
References BITS_PER_UNIT, GET_MODE_ALIGNMENT, GET_MODE_BITSIZE, MEM_ALIGN, MEM_P, and SLOW_UNALIGNED_ACCESS.
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Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value VALUE << BITPOS.
| tree make_tree | ( | ) |
Return a tree node with data type TYPE, describing the value of X. Usually this is an VAR_DECL, if there is no obvious better choice. X may be an expression, however we only support those expressions generated by loop.c.
Build a tree with vector elements.
else fall through.
If TYPE is a POINTER_TYPE, we might need to convert X from
address mode to pointer mode. Note that we do *not* use SET_DECL_RTL here, because we do not
want set_decl_rtl to go adjusting REG_ATTRS for this temporary.
Referenced by count_type_elements(), and initialize_argument_information().
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Return a constant integer (CONST_INT or CONST_DOUBLE) mask value of mode MODE with BITSIZE ones followed by BITPOS zeros, or the complement of that if COMPLEMENT. The mask is truncated if necessary to the width of mode MODE. The mask is zero-extended if BITSIZE+BITPOS is too small for MODE.
| int mult_by_coeff_cost | ( | ) |
Return a cost estimate for multiplying a register by the given COEFFicient in the given MODE and SPEED.
Referenced by alloc_cand_and_find_basis(), and optimize_cands_for_speed_p().
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Adjust bitfield memory MEM so that it points to the first unit of mode MODE that contains a bitfield of size BITSIZE at bit position BITNUM. If MODE is BLKmode, return a reference to every byte in the bitfield. Set *NEW_BITNUM to the bit position of the field within the new memory.
| rtx negate_rtx | ( | ) |
Return an rtx representing minus the value of X. MODE is the intended mode of the result, useful if X is a CONST_INT.
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Return true if OP is a memory and if a bitfield of size BITSIZE at bit number BITNUM can be treated as a simple value of mode MODE.
References extraction_insn::field_mode, get_last_insn(), GET_MODE_BITSIZE, and last.
| void store_bit_field | ( | rtx | str_rtx, |
| unsigned HOST_WIDE_INT | bitsize, | ||
| unsigned HOST_WIDE_INT | bitnum, | ||
| unsigned HOST_WIDE_INT | bitregion_start, | ||
| unsigned HOST_WIDE_INT | bitregion_end, | ||
| enum machine_mode | fieldmode, | ||
| rtx | value | ||
| ) |
Generate code to store value from rtx VALUE into a bit-field within structure STR_RTX containing BITSIZE bits starting at bit BITNUM.
BITREGION_START is bitpos of the first bitfield in this region. BITREGION_END is the bitpos of the ending bitfield in this region. These two fields are 0, if the C++ memory model does not apply, or we are not interested in keeping track of bitfield regions.
FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
Under the C++0x memory model, we must not touch bits outside the bit region. Adjust the address to start at the beginning of the bit region.
References get_best_mode(), GET_MODE, GET_MODE_BITSIZE, HOST_WIDE_INT, MAX_FIXED_MODE_SIZE, MEM_ALIGN, MEM_VOLATILE_P, and word_mode.
Referenced by noce_emit_store_flag().
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A subroutine of store_bit_field, with the same arguments. Return true if the operation could be implemented.
If FALLBACK_P is true, fall back to store_fixed_bit_field if we have no other way of implementing the operation. If FALLBACK_P is false, return false instead.
The following line once was done only if WORDS_BIG_ENDIAN,
but I think that is a mistake. WORDS_BIG_ENDIAN is
meaningful at a much higher level; when structures are copied
between memory and regs, the higher-numbered regs
always get higher addresses.
Paradoxical subregs need special handling on big endian machines.
No action is needed if the target is a register and if the field lies completely outside that register. This can occur if the source code contains an out-of-bounds access to a small array.
Use vec_set patterns for inserting parts of vectors whenever available.
If the target is a register, overwriting the entire object, or storing a full-word or multi-word field can be done with just a SUBREG.
Use the subreg machinery either to narrow OP0 to the required
words or to cope with mode punning between equal-sized modes. If the target is memory, storing any naturally aligned field can be done with a simple store. For targets that support fast unaligned memory, any naturally sized, unit aligned field can be done directly.
Make sure we are playing with integral modes. Pun with subregs if we aren't. This must come after the entire register case above, since that case is valid for any mode. The following cases are only valid for integral modes.
Storing an lsb-aligned field in a register can be done with a movstrict instruction.
Else we've got some float mode source being extracted into
a different float mode destination – this combination of
subregs results in Severe Tire Damage. Shrink the source operand to FIELDMODE.
Handle fields bigger than a word.
Here we transfer the words of the field
in the order least significant first.
This is because the most significant word is the one which may
be less than full.
However, only do that if the value is not BLKmode. This is the mode we must force value to, so that there will be enough
subwords to extract. Note that fieldmode will often (always?) be
VOIDmode, because that is what store_field uses to indicate that this
is a bit field, but passing VOIDmode to operand_subword_force
is not allowed. If I is 0, use the low-order word in both field and target;
if I is 1, use the next to lowest word; and so on. If the remaining chunk doesn't have full wordsize we have
to make sure that for big endian machines the higher order
bits are used. If VALUE has a floating-point or complex mode, access it as an integer of the corresponding size. This can occur on a machine with 64 bit registers that uses SFmode for float. It can also occur for unaligned float or complex fields.
If OP0 is a multi-word register, narrow it to the affected word. If the region spans two words, defer to store_split_bit_field.
From here on we can assume that the field to be stored in fits within a word. If the destination is a register, it too fits in a word.
If OP0 is a memory, try copying it to a register and seeing if a cheap register alternative is available.
Do not use unaligned memory insvs for volatile bitfields when
-fstrict-volatile-bitfields is in effect. Try loading part of OP0 into a register, inserting the bitfield
into that, and then copying the result back to OP0.
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Try to use instruction INSV to store VALUE into a field of OP0. BITSIZE and BITNUM are as for store_bit_field.
Get a reference to the first byte of the field.
Convert from counting within OP0 to counting in OP_MODE.
If xop0 is a register, we need it in OP_MODE
to make it acceptable to the format of insv. We can't just change the mode, because this might clobber op0,
and we will need the original value of op0 if insv fails. If the destination is a paradoxical subreg such that we need a truncate to the inner mode, perform the insertion on a temporary and truncate the result to the original destination. Note that we can't just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N X) 0)) is (reg:N X).
If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count "backwards" from the size of the unit we are inserting into. Otherwise, we count bits from the most significant on a BYTES/BITS_BIG_ENDIAN machine.
Convert VALUE to op_mode (which insv insn wants) in VALUE1.
Optimization: Don't bother really extending VALUE
if it has all the bits we will actually use. However,
if we must narrow it, be sure we do it correctly. Parse phase is supposed to make VALUE's data type
match that of the component reference, which is a type
at least as wide as the field; so VALUE should have
a mode that corresponds to that type.
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Use shifts and boolean operations to store VALUE into a bit field of width BITSIZE in OP0, starting at bit BITNUM.
There is a case not handled here: a structure with a known alignment of just a halfword and a field split across two aligned halfwords within the structure. Or likewise a structure with a known alignment of just a byte and a field split across two bytes. Such cases are not supposed to be able to occur.
Get the proper mode to use for this field. We want a mode that
includes the entire field. If such a mode would be larger than
a word, we won't be doing the extraction the normal way.
We don't want a mode bigger than the destination. The only way this should occur is if the field spans word
boundaries. Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode) for invalid input, such as f5 from gcc.dg/pr48335-2.c.
BITNUM is the distance between our msb and that of the containing datum. Convert it to the distance from the lsb.
Now BITNUM is always the distance between our lsb and that of OP0.
Shift VALUE left by BITNUM bits. If VALUE is not constant, we must first convert its mode to MODE.
Now clear the chosen bits in OP0, except that if VALUE is -1 we need not bother.
We keep the intermediates in registers to allow CSE to combine consecutive bitfield assignments.
Now logical-or VALUE into OP0, unless it is zero.
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Store a bit field that is split across multiple accessible memory objects.
OP0 is the REG, SUBREG or MEM rtx for the first of the objects. BITSIZE is the field width; BITPOS the position of its first bit (within the word). VALUE is the value to store.
This does not yet handle fields wider than BITS_PER_WORD.
Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that much at a time.
If VALUE is a constant other than a CONST_INT, get it into a register in WORD_MODE. If we can do this using gen_lowpart_common, do so. Note that VALUE might be a floating-point constant.
When region of bytes we can touch is restricted, decrease
UNIT close to the end of the region as needed. If op0 is a REG
or SUBREG of REG, don't do this, as there can't be data races
on a register and we can expand shorter code in some cases. THISSIZE must not overrun a word boundary. Otherwise,
store_fixed_bit_field will call us again, and we will mutually
recurse forever. Fetch successively less significant portions.
The args are chosen so that the last part includes the
lsb. Give extract_bit_field the value it needs (with
endianness compensation) to fetch the piece we want. Fetch successively more significant portions.
If OP0 is a register, then handle OFFSET here.
When handling multiword bitfields, extract_bit_field may pass
down a word_mode SUBREG of a larger REG for a bitfield that actually
crosses a word boundary. Thus, for a SUBREG, we must find
the current word starting from the base register. OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
it is just an out-of-bounds access. Ignore it.
|
static |
Compute and return the best algorithm for multiplying by T. The algorithm must cost less than cost_limit If retval.cost >= COST_LIMIT, no algorithm was found and all other field of the returned struct are undefined. MODE is the machine mode of the multiplication.
Indicate that no algorithm is yet found. If no algorithm is found, this value will be returned and indicate failure.
Be prepared for vector modes.
Restrict the bits of "t" to the multiplication's mode.
t == 1 can be done in zero cost.
t == 0 sometimes has a cost. If it does and it exceeds our limit, fail now.
We'll be needing a couple extra algorithm structures now.
Compute the hash index.
See if we already know what to do for T.
The cache tells us that it's impossible to synthesize
multiplication by T within entry_ptr->cost. COST_LIMIT is at least as restrictive as the one
recorded in the hash table, in which case we have no
hope of synthesizing a multiplication. Just
return. If we get here, COST_LIMIT is less restrictive than the
one recorded in the hash table, so we may be able to
synthesize a multiplication. Proceed as if we didn't
have the cache entry. The cached algorithm shows that this multiplication
requires more cost than COST_LIMIT. Just return. This
way, we don't clobber this cache entry with
alg_impossible but retain useful information. If we have a group of zero bits at the low-order part of T, try multiplying by the remaining bits and then doing a shift.
The function expand_shift will choose between a shift and
a sequence of additions, so the observed cost is given as
MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). See if treating ORIG_T as a signed number yields a better
sequence. Try this sequence only for a negative ORIG_T
as it would be useless for a non-negative ORIG_T. Shift ORIG_T as follows because a right shift of a
negative-valued signed type is implementation
defined. The function expand_shift will choose between a shift
and a sequence of additions, so the observed cost is
given as MIN (m * add_cost(speed, mode),
shift_cost(speed, mode, m)). If we have an odd number, add or subtract one.
If T was -1, then W will be zero after the loop. This is another
case where T ends with ...111. Handling this with (T + 1) and
subtract 1 produces slightly better code and results in algorithm
selection much faster than treating it like the ...0111 case
below. Reject the case where t is 3.
Thus we prefer addition in that case. T ends with ...111. Multiply by (T + 1) and subtract 1.
T ends with ...01 or ...011. Multiply by (T - 1) and add 1.
We may be able to calculate a * -7, a * -15, a * -31, etc
quickly with a - a * n for some appropriate constant n. Look for factors of t of the form t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)). If we find such a factor, we can multiply by t using an algorithm that multiplies by q, shift the result by m and add/subtract it to itself. We search for large factors first and loop down, even if large factors are less probable than small; if we find a large factor we will find a good sequence quickly, and therefore be able to prune (by decreasing COST_LIMIT) the search.
If the target has a cheap shift-and-add instruction use
that in preference to a shift insn followed by an add insn.
Assume that the shift-and-add is "atomic" with a latency
equal to its cost, otherwise assume that on superscalar
hardware the shift may be executed concurrently with the
earlier steps in the algorithm. Other factors will have been taken care of in the recursion.
If the target has a cheap shift-and-subtract insn use
that in preference to a shift insn followed by a sub insn.
Assume that the shift-and-sub is "atomic" with a latency
equal to it's cost, otherwise assume that on superscalar
hardware the shift may be executed concurrently with the
earlier steps in the algorithm. Try shift-and-add (load effective address) instructions, i.e. do a*3, a*5, a*9.
If best_cost has not decreased, we have not found any algorithm.
We failed to find an algorithm. Record alg_impossible for
this case (that is, <T, MODE, COST_LIMIT>) so that next time
we are asked to find an algorithm for T within the same or
lower COST_LIMIT, we can immediately return to the
caller. Cache the result.
If we are getting a too long sequence for `struct algorithm' to record, make this search fail.
Copy the algorithm from temporary space to the space at alg_out. We avoid using structure assignment because the majority of best_alg is normally undefined, and this is a critical function.
Variable Documentation
| struct target_expmed default_target_expmed |
Medium-level subroutines: convert bit-field store and extract and shifts, multiplies and divides to rtl instructions. Copyright (C) 1987-2013 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see http://www.gnu.org/licenses/.
