#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "diagnostic-core.h"
#include "insn-config.h"
#include "rtl.h"
#include "tree.h"
#include "tm_p.h"
#include "flags.h"
#include "function.h"
#include "except.h"
#include "expr.h"
#include "optabs.h"
#include "libfuncs.h"
#include "recog.h"
#include "reload.h"
#include "ggc.h"
#include "basic-block.h"
#include "target.h"
#include "gt-optabs.h"

Include dependency graph for optabs.c:

Data Structures
struct	no_conflict_data
struct	atomic_op_functions

Macros
#define	libfunc_hash (this_target_libfuncs->x_libfunc_hash)
#define	DECIMAL_PREFIX "dpd_"
#define	HAVE_atomic_test_and_set 0
#define	CODE_FOR_atomic_test_and_set CODE_FOR_nothing
#define	HAVE_mem_thread_fence 0
#define	gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX)
#define	HAVE_memory_barrier 0
#define	gen_memory_barrier() (gcc_unreachable (), NULL_RTX)
#define	HAVE_mem_signal_fence 0
#define	gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX)
#define	HAVE_insv 0
#define	CODE_FOR_insv CODE_FOR_nothing
#define	HAVE_extv 0
#define	CODE_FOR_extv CODE_FOR_nothing
#define	HAVE_extzv 0
#define	CODE_FOR_extzv CODE_FOR_nothing

Enumerations
enum	extraction_type { ET_unaligned_mem, ET_reg }

Functions
static void	prepare_float_lib_cmp (rtx, rtx, enum rtx_code, rtx , enum machine_mode )
static rtx	expand_unop_direct (enum machine_mode, optab, rtx, rtx, int)
static void	emit_libcall_block_1 (rtx, rtx, rtx, rtx, bool)
void	debug_optab_libfuncs (void)
static hashval_t	hash_libfunc ()
static int	eq_libfunc ()
rtx	convert_optab_libfunc (convert_optab optab, enum machine_mode mode1, enum machine_mode mode2)
rtx	optab_libfunc ()
static int	add_equal_note ()
static enum machine_mode	widened_mode ()
enum insn_code	find_widening_optab_handler_and_mode (optab op, enum machine_mode to_mode, enum machine_mode from_mode, int permit_non_widening, enum machine_mode *found_mode)
static rtx	widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, int unsignedp, int no_extend)
optab	optab_for_tree_code (enum tree_code code, const_tree type, enum optab_subtype subtype)
rtx	expand_widen_pattern_expr (sepops ops, rtx op0, rtx op1, rtx wide_op, rtx target, int unsignedp)
rtx	expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, rtx op1, rtx op2, rtx target, int unsignedp)
rtx	simplify_expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, rtx target, int unsignedp, enum optab_methods methods)
bool	force_expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, rtx target, int unsignedp, enum optab_methods methods)
rtx	expand_vec_shift_expr ()
static rtx	expand_vector_broadcast ()
static bool	expand_superword_shift (optab binoptab, rtx outof_input, rtx superword_op1, rtx outof_target, rtx into_target, int unsignedp, enum optab_methods methods)
static bool	expand_subword_shift (enum machine_mode op1_mode, optab binoptab, rtx outof_input, rtx into_input, rtx op1, rtx outof_target, rtx into_target, int unsignedp, enum optab_methods methods, unsigned HOST_WIDE_INT shift_mask)
static bool	expand_doubleword_shift (enum machine_mode op1_mode, optab binoptab, rtx outof_input, rtx into_input, rtx op1, rtx outof_target, rtx into_target, int unsignedp, enum optab_methods methods, unsigned HOST_WIDE_INT shift_mask)
static rtx	expand_doubleword_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, bool umulp, enum optab_methods methods)
rtx	expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1, rtx target, int unsignedp, enum optab_methods methods)
static bool	swap_commutative_operands_with_target ()
static bool	shift_optab_p ()
static bool	commutative_optab_p ()
static rtx	avoid_expensive_constant (enum machine_mode mode, optab binoptab, int opn, rtx x, bool unsignedp)
static rtx	expand_binop_directly (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, rtx target, int unsignedp, enum optab_methods methods, rtx last)
rtx	expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, rtx target, int unsignedp, enum optab_methods methods)
rtx	sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, rtx op0, rtx op1, rtx target, int unsignedp, enum optab_methods methods)
int	expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1, int unsignedp)
int	expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, int unsignedp)
bool	expand_twoval_binop_libfunc (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, enum rtx_code code)
rtx	expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, rtx target, int unsignedp)
static rtx	widen_leading ()
static rtx	expand_doubleword_clz ()
static rtx	widen_bswap ()
static rtx	expand_doubleword_bswap ()
static rtx	expand_parity ()
static rtx	expand_ctz ()
static rtx	expand_ffs ()
static rtx	lowpart_subreg_maybe_copy (enum machine_mode omode, rtx val, enum machine_mode imode)
static rtx	expand_absneg_bit (enum rtx_code code, enum machine_mode mode, rtx op0, rtx target)
rtx	expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, int unsignedp)
rtx	expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, int result_unsignedp)
rtx	expand_abs (enum machine_mode mode, rtx op0, rtx target, int result_unsignedp, int safe)
rtx	expand_one_cmpl_abs_nojump ()
static rtx	expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target, int bitpos, bool op0_is_abs)
static rtx	expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target, int bitpos, bool op0_is_abs)
rtx	expand_copysign ()
bool	maybe_emit_unop_insn (enum insn_code icode, rtx target, rtx op0, enum rtx_code code)
void	emit_unop_insn ()
static void	no_conflict_move_test ()
void	emit_libcall_block ()
int	can_compare_p (enum rtx_code code, enum machine_mode mode, enum can_compare_purpose purpose)
static void	prepare_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, int unsignedp, enum optab_methods methods, rtx ptest, enum machine_mode pmode)
rtx	prepare_operand (enum insn_code icode, rtx x, int opnum, enum machine_mode mode, enum machine_mode wider_mode, int unsignedp)
static void	emit_cmp_and_jump_insn_1 ()
void	emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, enum machine_mode mode, int unsignedp, rtx label, int prob)
void	emit_indirect_jump ()
rtx	emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, enum machine_mode cmode, rtx op2, rtx op3, enum machine_mode mode, int unsignedp)
rtx	gen_add2_insn ()
rtx	gen_add3_insn ()
int	have_add2_insn ()
rtx	gen_sub2_insn ()
rtx	gen_sub3_insn ()
int	have_sub2_insn ()
rtx	gen_move_insn ()
enum insn_code	can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, int unsignedp)
rtx	gen_extend_insn (rtx x, rtx y, enum machine_mode mto, enum machine_mode mfrom, int unsignedp)
static enum insn_code	can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, int unsignedp, int *truncp_ptr)
enum insn_code	can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, int unsignedp)
bool	supportable_convert_operation (enum tree_code code, tree vectype_out, tree vectype_in, tree decl, enum tree_code code1)
void	expand_float ()
void	expand_fix ()
void	expand_fixed_convert ()
bool	expand_sfix_optab ()
int	have_insn_for ()
static void	gen_libfunc (optab optable, const char *opname, int suffix, enum machine_mode mode)
void	gen_int_libfunc (optab optable, const char *opname, char suffix, enum machine_mode mode)
void	gen_fp_libfunc (optab optable, const char *opname, char suffix, enum machine_mode mode)
void	gen_fixed_libfunc (optab optable, const char *opname, char suffix, enum machine_mode mode)
void	gen_signed_fixed_libfunc (optab optable, const char *opname, char suffix, enum machine_mode mode)
void	gen_unsigned_fixed_libfunc (optab optable, const char *opname, char suffix, enum machine_mode mode)
void	gen_int_fp_libfunc (optab optable, const char *name, char suffix, enum machine_mode mode)
void	gen_intv_fp_libfunc (optab optable, const char *name, char suffix, enum machine_mode mode)
void	gen_int_fp_fixed_libfunc (optab optable, const char *name, char suffix, enum machine_mode mode)
void	gen_int_fp_signed_fixed_libfunc (optab optable, const char *name, char suffix, enum machine_mode mode)
void	gen_int_fixed_libfunc (optab optable, const char *name, char suffix, enum machine_mode mode)
void	gen_int_signed_fixed_libfunc (optab optable, const char *name, char suffix, enum machine_mode mode)
void	gen_int_unsigned_fixed_libfunc (optab optable, const char *name, char suffix, enum machine_mode mode)
void	gen_interclass_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_int_to_fp_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_ufloat_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_fp_to_int_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_intraclass_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_trunc_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_extend_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_fract_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_fractuns_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_satfract_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
void	gen_satfractuns_conv_libfunc (convert_optab tab, const char *opname, enum machine_mode tmode, enum machine_mode fmode)
static hashval_t	libfunc_decl_hash ()
static int	libfunc_decl_eq ()
tree	build_libfunc_function ()
rtx	init_one_libfunc ()
rtx	set_user_assembler_libfunc ()
void	set_optab_libfunc ()
void	set_conv_libfunc (convert_optab optab, enum machine_mode tmode, enum machine_mode fmode, const char *name)
void	init_optabs ()
void	init_tree_optimization_optabs ()
static void	init_sync_libfuncs_1 ()
void	init_sync_libfuncs ()
rtx	gen_cond_trap ()
static enum rtx_code	get_rtx_code ()
static rtx	vector_compare_rtx (enum tree_code tcode, tree t_op0, tree t_op1, bool unsignedp, enum insn_code icode)
bool	can_vec_perm_p (enum machine_mode mode, bool variable, const unsigned char *sel)
static rtx	expand_vec_perm_1 (enum insn_code icode, rtx target, rtx v0, rtx v1, rtx sel)
rtx	expand_vec_perm ()
static enum insn_code	get_vcond_icode ()
bool	expand_vec_cond_expr_p ()
rtx	expand_vec_cond_expr (tree vec_cond_type, tree op0, tree op1, tree op2, rtx target)
int	can_mult_highpart_p ()
rtx	expand_mult_highpart (enum machine_mode mode, rtx op0, rtx op1, rtx target, bool uns_p)
bool	can_compare_and_swap_p ()
bool	can_atomic_exchange_p ()
static void	find_cc_set ()
static bool	expand_compare_and_swap_loop ()
static rtx	maybe_emit_atomic_exchange ()
static rtx	maybe_emit_sync_lock_test_and_set (rtx target, rtx mem, rtx val, enum memmodel model)
static rtx	maybe_emit_compare_and_swap_exchange_loop ()
static rtx	maybe_emit_atomic_test_and_set ()
rtx	expand_sync_lock_test_and_set ()
rtx	expand_atomic_test_and_set ()
rtx	expand_atomic_exchange ()
bool	expand_atomic_compare_and_swap (rtx ptarget_bool, rtx ptarget_oval, rtx mem, rtx expected, rtx desired, bool is_weak, enum memmodel succ_model, enum memmodel fail_model)
static void	expand_asm_memory_barrier ()
void	expand_mem_thread_fence ()
void	expand_mem_signal_fence ()
rtx	expand_atomic_load ()
rtx	expand_atomic_store ()
static void	get_atomic_op_for_code ()
static rtx	maybe_optimize_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code, enum memmodel model, bool after)
static rtx	maybe_emit_op (const struct atomic_op_functions *optab, rtx target, rtx mem, rtx val, bool use_memmodel, enum memmodel model, bool after)
static rtx	expand_atomic_fetch_op_no_fallback (rtx target, rtx mem, rtx val, enum rtx_code code, enum memmodel model, bool after)
rtx	expand_atomic_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code, enum memmodel model, bool after)
bool	insn_operand_matches ()
bool	valid_multiword_target_p ()
static bool	maybe_legitimize_operand_same_code (enum insn_code icode, unsigned int opno, struct expand_operand *op)
static bool	maybe_legitimize_operand (enum insn_code icode, unsigned int opno, struct expand_operand *op)
void	create_convert_operand_from_type (struct expand_operand *op, rtx value, tree type)
bool	maybe_legitimize_operands (enum insn_code icode, unsigned int opno, unsigned int nops, struct expand_operand *ops)
rtx	maybe_gen_insn (enum insn_code icode, unsigned int nops, struct expand_operand *ops)
bool	maybe_expand_insn (enum insn_code icode, unsigned int nops, struct expand_operand *ops)
bool	maybe_expand_jump_insn (enum insn_code icode, unsigned int nops, struct expand_operand *ops)
void	expand_insn (enum insn_code icode, unsigned int nops, struct expand_operand *ops)
void	expand_jump_insn (enum insn_code icode, unsigned int nops, struct expand_operand *ops)
static bool	get_traditional_extraction_insn (extraction_insn *insn, enum extraction_type type, enum machine_mode mode, enum insn_code icode, int struct_op, int field_op)
static bool	get_optab_extraction_insn (struct extraction_insn *insn, enum extraction_type type, enum machine_mode mode, direct_optab reg_optab, direct_optab misalign_optab, int pos_op)
static bool	get_extraction_insn (extraction_insn *insn, enum extraction_pattern pattern, enum extraction_type type, enum machine_mode mode)
static bool	get_best_extraction_insn (extraction_insn *insn, enum extraction_pattern pattern, enum extraction_type type, unsigned HOST_WIDE_INT struct_bits, enum machine_mode field_mode)
bool	get_best_reg_extraction_insn (extraction_insn *insn, enum extraction_pattern pattern, unsigned HOST_WIDE_INT struct_bits, enum machine_mode field_mode)
bool	get_best_mem_extraction_insn (extraction_insn *insn, enum extraction_pattern pattern, HOST_WIDE_INT bitsize, HOST_WIDE_INT bitnum, enum machine_mode field_mode)

Variables
struct target_optabs	default_target_optabs
struct target_libfuncs	default_target_libfuncs
struct target_optabs *	this_fn_optabs = &default_target_optabs
static htab_t	libfunc_decls

Macro Definition Documentation

#define CODE_FOR_atomic_test_and_set CODE_FOR_nothing

#define CODE_FOR_extv CODE_FOR_nothing

#define CODE_FOR_extzv CODE_FOR_nothing

#define CODE_FOR_insv CODE_FOR_nothing

#define DECIMAL_PREFIX "dpd_"

Prefixes for the current version of decimal floating point (BID vs. DPD)

Referenced by expand_sfix_optab().

#define gen_mem_signal_fence ( x ) (gcc_unreachable (), NULL_RTX)

#define gen_mem_thread_fence ( x ) (gcc_unreachable (), NULL_RTX)

Referenced by maybe_emit_sync_lock_test_and_set().

#define gen_memory_barrier ( ) (gcc_unreachable (), NULL_RTX)

Referenced by maybe_emit_sync_lock_test_and_set().

#define HAVE_atomic_test_and_set 0

This function tries to implement an atomic test-and-set operation using the atomic_test_and_set instruction pattern. A boolean value is returned from the operation, using TARGET if possible.

#define HAVE_extv 0

#define HAVE_extzv 0

#define HAVE_insv 0

Reduce conditional compilation elsewhere.

#define HAVE_mem_signal_fence 0

This routine will either emit the mem_signal_fence pattern or issue a sync_synchronize to generate a fence for memory model MEMMODEL.

#define HAVE_mem_thread_fence 0

This routine will either emit the mem_thread_fence pattern or issue a sync_synchronize to generate a fence for memory model MEMMODEL.

Referenced by maybe_emit_sync_lock_test_and_set().

#define HAVE_memory_barrier 0

Referenced by maybe_emit_sync_lock_test_and_set().

#define libfunc_hash (this_target_libfuncs->x_libfunc_hash)

Referenced by convert_optab_libfunc(), gen_fp_to_int_conv_libfunc(), and optab_libfunc().

Enumeration Type Documentation

enum extraction_type

Enumerates the possible types of structure operand to an extraction_insn.

Enumerator:

ET_unaligned_mem
ET_reg

Function Documentation

static int add_equal_note ( )

static

Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to the result of operation CODE applied to OP0 (and OP1 if it is a binary operation).

If the last insn does not set TARGET, don't do anything, but return 1.

If the last insn or a previous insn sets TARGET and TARGET is one of OP0 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then try again, ensuring that TARGET is not one of the operands.

 If TARGET is in OP0 or OP1, punt.  We'd end up with a note referencing
 a value changing in the insn, so the note would be invalid for CSE.

         For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
         over expanding it as temp = MEM op X, MEM = temp.  If the target
         supports MEM = MEM op X instructions, it is sometimes too hard
         to reconstruct that form later, especially if X is also a memory,
         and due to multiple occurrences of addresses the address might
         be forced into register unnecessarily.
         Note that not emitting the REG_EQUIV note might inhibit
         CSE in some cases.

     For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it.

       FALLTHRU

References GET_CODE, MEM_P, rtx_equal_p(), SET_DEST, SET_SRC, single_set, and XEXP.

static rtx avoid_expensive_constant	(	enum machine_mode	mode,
		optab	binoptab,
		int	opn,
		rtx	x,
		bool	unsignedp
	)

static

X is to be used in mode MODE as operand OPN to BINOPTAB. If we're optimizing, and if the operand is a constant that costs more than 1 instruction, force the constant into a register and return that register. Return X otherwise. UNSIGNEDP says whether X is unsigned.

References convert_modes().

tree build_libfunc_function ( )

Build a decl for a libfunc named NAME.

??? We don't have any type information except for this is a function. Pretend this is "int foo()".

 Zap the nonsensical SYMBOL_REF_DECL for this.  What we're left with
 are the flags assigned by targetm.encode_section_info.

References do_pending_stack_adjust(), GET_MODE, insn_operand_matches(), and optab_handler().

bool can_atomic_exchange_p ( )

Return true if an atomic exchange can be performed.

Check for __atomic_exchange.

 Don't check __sync_test_and_set, as on some platforms that
 has reduced functionality.  Targets that really do support
 a proper exchange should simply be updated to the __atomics.

References insn_data.

bool can_compare_and_swap_p ( )

Return true if there is a compare_and_swap pattern.

 Check for __atomic_compare_and_swap.

 Check for __sync_compare_and_swap.

 No inline compare and swap.

References copy_to_reg(), GET_MODE, MEM_P, and NULL_RTX.

Referenced by expand_omp_atomic_load().

int can_compare_p	(	enum rtx_code	code,
		enum machine_mode	mode,
		enum can_compare_purpose	purpose
	)

Nonzero if we can perform a comparison of mode MODE straightforwardly. PURPOSE describes how this comparison will be used. CODE is the rtx comparison code we will be using.

??? Actually, CODE is slightly weaker than that. A target is still required to implement all of the normal bcc operations, but not required to implement all (or any) of the unordered bcc operations.

Referenced by emit_cstore().

enum insn_code can_extend_p	(	enum machine_mode	to_mode,
		enum machine_mode	from_mode,
		int	unsignedp
	)

Return the insn code used to extend FROM_MODE to TO_MODE. UNSIGNEDP specifies zero-extension instead of sign-extension. If no such operation exists, CODE_FOR_nothing will be returned.

static enum insn_code can_fix_p	(	enum machine_mode	fixmode,
		enum machine_mode	fltmode,
		int	unsignedp,
		int *	truncp_ptr
	)

static

can_fix_p and can_float_p say whether the target machine can directly convert a given fixed point type to a given floating point type, or vice versa. The returned value is the CODE_FOR_... value to use, or CODE_FOR_nothing if these modes cannot be directly converted.

*TRUNCP_PTR is set to 1 if it is necessary to output an explicit FTRUNC insn before the fix insn; otherwise 0.

FIXME: This requires a port to define both FIX and FTRUNC pattern for this to work. We need to rework the fix* and ftrunc* patterns and documentation.

Referenced by supportable_convert_operation().

enum insn_code can_float_p	(	enum	machine_mode,
		enum	machine_mode,
		int
	)

Return the insn_code for a FLOAT_EXPR.

Referenced by have_add2_insn().

int can_mult_highpart_p ( )

Return non-zero if a highpart multiply is supported of can be synthisized. For the benefit of expand_mult_highpart, the return value is 1 for direct, 2 for even/odd widening, and 3 for hi/lo widening.

If the mode is an integral vector, synth from widening operations.

bool can_vec_perm_p	(	enum machine_mode	mode,
		bool	variable,
		const unsigned char *	sel
	)

Return true if VEC_PERM_EXPR can be expanded using SIMD extensions of the CPU. SEL may be NULL, which stands for an unknown constant.

 If the target doesn't implement a vector mode for the vector type,
 then no operations are supported.

 We allow fallback to a QI vector mode, and adjust the mask.

 ??? For completeness, we ought to check the QImode version of
  vec_perm_const_optab.  But all users of this implicit lowering
  feature implement the variable vec_perm_optab.

 In order to support the lowering of variable permutations,
 we need to support shifts and adds.

Referenced by vect_get_mask_element().

static bool commutative_optab_p ( )

static

Return true if BINOPTAB implements a commutative binary operation.

References swap().

Referenced by shift_optab_p().

rtx convert_optab_libfunc	(	convert_optab	optab,
		enum machine_mode	mode1,
		enum machine_mode	mode2
	)

Return libfunc corresponding operation defined by OPTAB converting from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL if no libfunc is available.

??? This ought to be an assert, but not all of the places that we expand optabs know about the optabs that got moved to being direct.

References convlib_def, convert_optab_libcall_d::libcall_basename, convert_optab_libcall_d::libcall_gen, libfunc_hash, and NULL.

void create_convert_operand_from_type	(	struct expand_operand *	op,
		rtx	value,
		tree	type
	)

Make OP describe an input operand that should have the same value as VALUE, after any mode conversion that the target might request. TYPE is the type of VALUE.

DEBUG_FUNCTION void debug_optab_libfuncs ( void )

Debug facility for use in GDB.

Print information about the current contents of the optabs on STDERR.

Dump the arithmetic optabs.

 Dump the conversion optabs.

static void emit_cmp_and_jump_insn_1 ( )

static

Subroutine of emit_cmp_and_jump_insns; this function is called when we know we can do the branch.

References const0_rtx, const1_rtx, constm1_rtx, GET_MODE, last, NULL, reversed_comparison_code_parts(), swap_commutative_operands_p(), and swap_condition().

void emit_cmp_and_jump_insns	(	rtx	x,
		rtx	y,
		enum rtx_code	comparison,
		rtx	size,
		enum machine_mode	mode,
		int	unsignedp,
		rtx	label,
		int	prob
	)

Generate code to compare X with Y so that the condition codes are set and to jump to LABEL if the condition is true. If X is a constant and Y is not a constant, then the comparison is swapped to ensure that the comparison RTL has the canonical form.

UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they need to be widened. UNSIGNEDP is also used to select the proper branch condition code.

If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.

MODE is the mode of the inputs (in case they are const_int).

COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). It will be potentially converted into an unsigned variant based on UNSIGNEDP to select a proper jump instruction.

PROB is the probability of jumping to LABEL.

Swap operands and condition to ensure canonical RTL.

 If OP0 is still a constant, then both X and Y must be constants
 or the opposite comparison is not supported.  Force X into a register
 to create canonical RTL.

Referenced by expand_float(), have_sub2_insn(), and node_has_low_bound().

rtx emit_conditional_add	(	rtx	target,
		enum rtx_code	code,
		rtx	op0,
		rtx	op1,
		enum machine_mode	cmode,
		rtx	op2,
		rtx	op3,
		enum machine_mode	mode,
		int	unsignedp
	)

Emit a conditional addition instruction if the machine supports one for that condition and machine mode.

OP0 and OP1 are the operands that should be compared using CODE. CMODE is the mode to use should they be constants. If it is VOIDmode, they cannot both be constants.

OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3 should be stored there. MODE is the mode to use should they be constants. If it is VOIDmode, they cannot both be constants.

The result is either TARGET (perhaps modified) or NULL_RTX if the operation is not supported.

 If one operand is constant, make it the second one.  Only do this
 if the other operand is not constant as well.

 get_condition will prefer to generate LT and GT even if the old
 comparison was against zero, so undo that canonicalization here since
 comparisons against zero are cheaper.

 We can get const0_rtx or const_true_rtx in some circumstances.  Just
 return NULL and let the caller figure out how best to deal with this
 situation.

void emit_indirect_jump ( )

Generate code to indirectly jump to a location given in the rtx LOC.

void emit_libcall_block ( )

static void emit_libcall_block_1	(	rtx	insns,
		rtx	target,
		rtx	result,
		rtx	equiv,
		bool	equiv_may_trap
	)

static

Emit code to make a call to a constant function or a library call.

INSNS is a list containing all insns emitted in the call. These insns leave the result in RESULT. Our block is to copy RESULT to TARGET, which is logically equivalent to EQUIV.

We first emit any insns that set a pseudo on the assumption that these are loading constants into registers; doing so allows them to be safely cse'ed between blocks. Then we emit all the other insns in the block, followed by an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL note with an operand of EQUIV.

 If this is a reg with REG_USERVAR_P set, then it could possibly turn
 into a MEM later.  Protect the libcall block from this change.

 If we're using non-call exceptions, a libcall corresponding to an
 operation that may trap may also trap.

 ??? See the comment in front of make_reg_eh_region_note.

     Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
     reg note to indicate that this call cannot throw or execute a nonlocal
     goto (unless there is already a REG_EH_REGION note, in which case
     we update it).

 First emit all insns that set pseudos.  Remove them from the list as
 we go.  Avoid insns that set pseudos which were referenced in previous
 insns.  These can be generated by move_by_pieces, for example,
 to update an address.  Similarly, avoid insns that reference things
 set in previous insns.

     Some ports use a loop to copy large arguments onto the stack.
     Don't move anything outside such a loop.

 Write the remaining insns followed by the final copy.

References insn_data.

void emit_unop_insn ( )

Generate an instruction whose insn-code is INSN_CODE, with two operands: an output TARGET and an input OP0. TARGET must be nonzero, and the output is always stored there. CODE is an rtx code such that (CODE OP0) is an rtx that describes the value that is stored into TARGET.

static int eq_libfunc ( )

static

Used for libfunc_hash.

rtx expand_abs	(	enum machine_mode	mode,
		rtx	op0,
		rtx	target,
		int	result_unsignedp,
		int	safe
	)

If that does not win, use conditional jump and negate.

 It is safe to use the target if it is the same
 as the source if this is also a pseudo register

References BITS_PER_WORD, double_int_zero, FLOAT_WORDS_BIG_ENDIAN, gen_reg_rtx(), GET_MODE_BITSIZE, GET_MODE_SIZE, int_mode_for_mode(), NULL_RTX, operand_subword(), operand_subword_force(), start_sequence(), valid_multiword_target_p(), and word_mode.

Referenced by expand_builtin_va_start().

rtx expand_abs_nojump	(	enum machine_mode	mode,
		rtx	op0,
		rtx	target,
		int	result_unsignedp
	)

Emit code to compute the absolute value of OP0, with result to TARGET if convenient. (TARGET may be 0.) The return value says where the result actually is to be found.

MODE is the mode of the operand; the mode of the result is different but can be deduced from MODE.

 First try to do it with a special abs instruction.

 For floating point modes, try clearing the sign bit.

 If we have a MAX insn, we can do this as MAX (x, -x).

 If this machine has expensive jumps, we can do integer absolute
 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
 where W is the width of MODE.

References insn_data.

static rtx expand_absneg_bit	(	enum rtx_code	code,
		enum machine_mode	mode,
		rtx	op0,
		rtx	target
	)

static

Expand a floating point absolute value or negation operation via a logical operation on the sign bit.

The format has to have a simple sign bit.

 Don't create negative zeros if the format doesn't support them.

References expand_doubleword_clz(), GET_MODE_SIZE, optab_handler(), widen_leading(), and word_mode.

static void expand_asm_memory_barrier ( )

static

Generate asm volatile("" : : : "memory") as the memory barrier.

Referenced by maybe_emit_sync_lock_test_and_set().

bool expand_atomic_compare_and_swap	(	rtx *	ptarget_bool,
		rtx *	ptarget_oval,
		rtx	mem,
		rtx	expected,
		rtx	desired,
		bool	is_weak,
		enum memmodel	succ_model,
		enum memmodel	fail_model
	)

This function expands the atomic compare exchange operation:

*PTARGET_BOOL is an optional place to store the boolean success/failure. *PTARGET_OVAL is an optional place to store the old value from memory. Both target parameters may be NULL to indicate that we do not care about that return value. Both target parameters are updated on success to the actual location of the corresponding result.

MEMMODEL is the memory model variant to use.

The return value of the function is true for success.

 Load expected into a register for the compare and swap.

 Make sure we always have some place to put the return oldval.
 Further, make sure that place is distinct from the input expected,
 just in case we need that path down below.

     Make sure we always have a place for the bool operand.

     Emit the compare_and_swap.

     Return success/failure.

 Otherwise fall back to the original __sync_val_compare_and_swap
 which is always seq-cst.

     If the caller isn't interested in the boolean return value,
     skip the computation of it.

     Otherwise, work out if the compare-and-swap succeeded.

 Also check for library support for __sync_val_compare_and_swap.

     Compute the boolean return value only if requested.

 Failure.

 Make sure that the oval output winds up where the caller asked.

References const0_rtx, constm1_rtx, gen_reg_rtx(), maybe_emit_atomic_exchange(), and NULL_RTX.

rtx expand_atomic_exchange ( )

This function expands the atomic exchange operation: atomically store VAL in MEM and return the previous value in MEM.

MEMMODEL is the memory model variant to use. TARGET is an optional place to stick the return value.

Next try a compare-and-swap loop for the exchange.

rtx expand_atomic_fetch_op	(	rtx	target,
		rtx	mem,
		rtx	val,
		enum rtx_code	code,
		enum memmodel	model,
		bool	after
	)

This function expands an atomic fetch_OP or OP_fetch operation: TARGET is an option place to stick the return value. const0_rtx indicates the result is unused. atomically fetch MEM, perform the operation with VAL and return it to MEM. CODE is the operation being performed (OP) MEMMODEL is the memory model variant to use. AFTER is true to return the result of the operation (OP_fetch). AFTER is false to return the value before the operation (fetch_OP).

 Add/sub can be implemented by doing the reverse operation with -(val).

         PLUS worked so emit the insns and return.

     PLUS did not work, so throw away the negation code and continue.

 Try the __sync libcalls only if we can't do compare-and-swap inline.

     We need the original code for any further attempts.

 If nothing else has succeeded, default to a compare and swap loop.

     If the result is used, get a register for it.

         If fetch_before, copy the value now.

     For after, copy the value now.

References insn_data.

static rtx expand_atomic_fetch_op_no_fallback	(	rtx	target,
		rtx	mem,
		rtx	val,
		enum rtx_code	code,
		enum memmodel	model,
		bool	after
	)

static

This function expands an atomic fetch_OP or OP_fetch operation: TARGET is an option place to stick the return value. const0_rtx indicates the result is unused. atomically fetch MEM, perform the operation with VAL and return it to MEM. CODE is the operation being performed (OP) MEMMODEL is the memory model variant to use. AFTER is true to return the result of the operation (OP_fetch). AFTER is false to return the value before the operation (fetch_OP).

This function will only generate instructions if there is a direct optab. No compare and swap loops or libcalls will be generated.

 Check to see if there are any better instructions.

 Check for the case where the result isn't used and try those patterns.

     Try the memory model variant first.

     Next try the old style withuot a memory model.

     There is no no-result pattern, so try patterns with a result.

 Try the __atomic version.

 Try the older __sync version.

 If the fetch value can be calculated from the other variation of fetch,
 try that operation.

     Try the __atomic version, then the older __sync version.

         If the result isn't used, no need to do compensation code.

         Issue compensation code.  Fetch_after  == fetch_before OP val.
         Fetch_before == after REVERSE_OP val.

 No direct opcode can be generated.

References emit_jump_insn(), and maybe_gen_insn().

Referenced by expand_atomic_load(), and expand_mem_signal_fence().

rtx expand_atomic_load ( )

This function expands the atomic load operation: return the atomically loaded value in MEM.

MEMMODEL is the memory model variant to use. TARGET is an option place to stick the return value.

 If the target supports the load directly, great.

 If the size of the object is greater than word size on this target,
 then we assume that a load will not be atomic.

     Issue val = compare_and_swap (mem, 0, 0).
     This may cause the occasional harmless store of 0 when the value is
     already 0, but it seems to be OK according to the standards guys.

     Otherwise there is no atomic load, leave the library call.

 Otherwise assume loads are atomic, and emit the proper barriers.

 For SEQ_CST, emit a barrier before the load.

 Emit the appropriate barrier after the load.

References emit_insn(), end_sequence(), expand_atomic_fetch_op_no_fallback(), expand_simple_unop(), get_insns(), NULL_RTX, and start_sequence().

rtx expand_atomic_store ( )

This function expands the atomic store operation: Atomically store VAL in MEM. MEMMODEL is the memory model variant to use. USE_RELEASE is true if __sync_lock_release can be used as a fall back. function returns const0_rtx if a pattern was emitted.

 If the target supports the store directly, great.

 If using __sync_lock_release is a viable alternative, try it.

             lock_release is only a release barrier.

 If the size of the object is greater than word size on this target,
 a default store will not be atomic, Try a mem_exchange and throw away
 the result.  If that doesn't work, don't do anything.

 Otherwise assume stores are atomic, and emit the proper barriers.

 For SEQ_CST, also emit a barrier after the store.

rtx expand_atomic_test_and_set ( )

This function expands the atomic test_and_set operation: atomically store a boolean TRUE into MEM and return the previous value.

MEMMODEL is the memory model variant to use. TARGET is an optional place to stick the return value.

 Be binary compatible with non-default settings of trueval, and different
 cpu revisions.  E.g. one revision may have atomic-test-and-set, but
 another only has atomic-exchange.

 Try the atomic-exchange optab...

 ... then an atomic-compare-and-swap loop ...

 ... before trying the vaguely defined legacy lock_test_and_set.

 Recall that the legacy lock_test_and_set optab was allowed to do magic
 things with the value 1.  Thus we try again without trueval.

 Failing all else, assume a single threaded environment and simply
 perform the operation.

 Recall that have to return a boolean value; rectify if trueval
 is not exactly one.

rtx expand_binop	(	enum machine_mode	mode,
		optab	binoptab,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	unsignedp,
		enum optab_methods	methods
	)

Generate code to perform an operation specified by BINOPTAB on operands OP0 and OP1, with result having machine-mode MODE.

UNSIGNEDP is for the case where we have to widen the operands to perform the operation. It says to use zero-extension.

If TARGET is nonzero, the value is generated there, if it is convenient to do so. In all cases an rtx is returned for the locus of the value; this may or may not be TARGET.

 If subtracting an integer constant, convert this into an addition of
 the negated constant.

 Record where to delete back to if we backtrack.

 If we can do it with a three-operand insn, do so.

 If we were trying to rotate, and that didn't work, try rotating
 the other direction before falling back to shifts and bitwise-or.

 If this is a multiply, see if we can do a widening operation that
 takes operands of this mode and makes a wider mode.

 If this is a vector shift by a scalar, see if we can do a vector
 shift by a vector.  If so, broadcast the scalar into a vector.

 Look for a wider mode of the same class for which we think we
 can open-code the operation.  Check for a widening multiply at the
 wider mode as well.

           For certain integer operations, we need not actually extend
           the narrow operands, as long as we will truncate
           the results to the same narrowness.

           The second operand of a shift must always be extended.

 If operation is commutative,
 try to make the first operand a register.
 Even better, try to make it the same as the target.
 Also try to make the last operand a constant.

 These can be done a word at a time.

     If TARGET is the same as one of the operands, the REG_EQUAL note
     won't be accurate, so use a new target.

     Do the actual arithmetic.

 Synthesize double word shifts from single word shifts.

     Apply the truncation to constant shifts.

     Make sure that this is a combination that expand_doubleword_shift
     can handle.  See the comments there for details.

         If TARGET is the same as one of the operands, the REG_EQUAL note
         won't be accurate, so use a new target.

         OUTOF_* is the word we are shifting bits away from, and
         INTO_* is the word that we are shifting bits towards, thus
         they differ depending on the direction of the shift and
         WORDS_BIG_ENDIAN.

 Synthesize double word rotates from single word shifts.

     If TARGET is the same as one of the operands, the REG_EQUAL note
     won't be accurate, so use a new target. Do this also if target is not
     a REG, first because having a register instead may open optimization
     opportunities, and second because if target and op0 happen to be MEMs
     designating the same location, we would risk clobbering it too early
     in the code sequence we generate below.

     OUTOF_* is the word we are shifting bits away from, and
     INTO_* is the word that we are shifting bits towards, thus
     they differ depending on the direction of the shift and
     WORDS_BIG_ENDIAN.

         This is just a word swap.

 These can be done a word at a time by propagating carries.

     We can handle either a 1 or -1 value for the carry.  If STORE_FLAG
     value is one of those, use it.  Otherwise, use 1 since it is the
     one easiest to get.

     Prepare the operands.

     Indicate for flow that the entire target reg is being set.

     Do the actual arithmetic.

         Main add/subtract of the input operands.

             Store carry from main add/subtract.

             Add/subtract previous carry to main result.

                 Get out carry from adding/subtracting carry in.

                 Logical-ior the two poss. carry together.

 Attempt to synthesize double word multiplies using a sequence of word
 mode multiplications.  We first attempt to generate a sequence using a
 more efficient unsigned widening multiply, and if that fails we then
 try using a signed widening multiply.

 It can't be open-coded in this mode.
 Use a library call if one is available and caller says that's ok.

         Specify unsigned here,
         since negative shift counts are meaningless.

     Pass 1 for NO_QUEUE so we don't lose any increments
     if the libcall is cse'd or moved.

 It can't be done in this mode.  Can we do it in a wider mode?

     Caller says, don't even try.

 Compute the value of METHODS to pass to recursive calls.
 Don't allow widening to be tried recursively.

 Look for a wider mode of the same class for which it appears we can do
 the operation.

             For certain integer operations, we need not actually extend
             the narrow operands, as long as we will truncate
             the results to the same narrowness.

             The second operand of a shift must always be extended.

References convert_to_mode(), expand_binop(), gen_lowpart, GET_MODE_2XWIDER_MODE, GET_MODE_CLASS, NULL_RTX, OPTAB_DIRECT, and TRULY_NOOP_TRUNCATION_MODES_P.

Referenced by emit_cstore(), expand_binop(), expand_doubleword_clz(), expand_ffs(), expand_float(), expand_mult(), expand_widening_mult(), extract_high_half(), and push_block().

static rtx expand_binop_directly	(	enum machine_mode	mode,
		optab	binoptab,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	unsignedp,
		enum optab_methods	methods,
		rtx	last
	)

static

Helper function for expand_binop: handle the case where there is an insn that directly implements the indicated operation. Returns null if this is not possible.

 If it is a commutative operator and the modes would match
 if we would swap the operands, we can save the conversions.

 If we are optimizing, force expensive constants into a register.

 In case the insn wants input operands in modes different from
 those of the actual operands, convert the operands.  It would
 seem that we don't need to convert CONST_INTs, but we do, so
 that they're properly zero-extended, sign-extended or truncated
 for their mode.

 If operation is commutative,
 try to make the first operand a register.
 Even better, try to make it the same as the target.
 Also try to make the last operand a constant.

 Now, if insn's predicates don't allow our operands, put them into
 pseudo regs.

     The mode of the result is different then the mode of the
     arguments.

     If PAT is composed of more than one insn, try to add an appropriate
     REG_EQUAL note to it.  If we can't because TEMP conflicts with an
     operand, call expand_binop again, this time without a target.

References delete_insns_since(), GET_MODE_NUNITS, insn_data, and NULL_RTX.

static bool expand_compare_and_swap_loop ( )

static

This is a helper function for the other atomic operations. This function emits a loop that contains SEQ that iterates until a compare-and-swap operation at the end succeeds. MEM is the memory to be modified. SEQ is a set of instructions that takes a value from OLD_REG as an input and produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be set to the current contents of MEM. After SEQ, a compare-and-swap will attempt to update MEM with NEW_REG. The function returns true when the loop was generated successfully.

The loop we want to generate looks like

cmp_reg = mem; label: old_reg = cmp_reg; seq; (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg) if (success) goto label;

Note that we only do the plain load from memory once. Subsequent iterations use the value loaded by the compare-and-swap pattern.

 Mark this jump predicted not taken.

rtx expand_copysign ( )

Expand the C99 copysign operation. OP0 and OP1 must be the same scalar floating point mode. Return NULL if we do not know how to expand the operation inline.

First try to do it with a special instruction.

References add_insn(), const0_rtx, no_conflict_data::first, no_conflict_data::insn, no_conflict_data::must_stay, NEXT_INSN, no_conflict_move_test(), note_stores(), PATTERN, PREV_INSN, and no_conflict_data::target.

Referenced by expand_builtin_va_end().

static rtx expand_copysign_absneg	(	enum machine_mode	mode,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	bitpos,
		bool	op0_is_abs
	)

static

A subroutine of expand_copysign, perform the copysign operation using the abs and neg primitives advertised to exist on the target. The assumption is that we have a split register file, and leaving op0 in fp registers, and not playing with subregs so much, will help the register allocator.

Check if the back end provides an insn that handles signbit for the argument's mode.

static rtx expand_copysign_bit	(	enum machine_mode	mode,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	bitpos,
		bool	op0_is_abs
	)

static

A subroutine of expand_copysign, perform the entire copysign operation with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS is true if op0 is known to have its sign bit clear.

References CALL_P, find_reg_fusage(), no_conflict_data::first, GET_CODE, no_conflict_data::insn, modified_between_p(), modified_in_p(), no_conflict_data::must_stay, PATTERN, reg_overlap_mentioned_p(), reg_used_between_p(), SET, SET_DEST, SET_SRC, and no_conflict_data::target.

static rtx expand_ctz ( )

static

Try calculating ctz(x) as K - clz(x & -x) , where K is GET_MODE_PRECISION(mode) - 1.

Both __builtin_ctz and __builtin_clz are undefined at zero, so we don't have to worry about what the hardware does in that case. (If the clz instruction produces the usual value at 0, which is K, the result of this code sequence will be -1; expand_ffs, below, relies on this. It might be nice to have it be K instead, for consistency with the (very few) processors that provide a ctz with a defined value, but that would take one more instruction, and it would be less convenient for expand_ffs anyway.

static rtx expand_doubleword_bswap ( )

static

Try calculating bswap as two bswaps of two word-sized operands.

static rtx expand_doubleword_clz ( )

static

Try calculating clz of a double-word quantity as two clz's of word-sized quantities, choosing which based on whether the high word is nonzero.

 If we were not given a target, use a word_mode register, not a
 'mode' register.  The result will fit, and nobody is expecting
 anything bigger (the return type of __builtin_clz* is int).

 In any case, write to a word_mode scratch in both branches of the
 conditional, so we can ensure there is a single move insn setting
 'target' to tag a REG_EQUAL note on.

 If the high word is not equal to zero,
 then clz of the full value is clz of the high word.

 Else clz of the full value is clz of the low word plus the number
 of bits in the high word.

References CLASS_HAS_WIDER_MODES_P, const1_rtx, delete_insns_since(), expand_binop(), expand_unop(), gen_reg_rtx(), get_last_insn(), GET_MODE_CLASS, GET_MODE_WIDER_MODE, last, NULL_RTX, OPTAB_DIRECT, optab_handler(), and widen_operand().

Referenced by expand_absneg_bit().

static rtx expand_doubleword_mult	(	enum machine_mode	mode,
		rtx	op0,
		rtx	op1,
		rtx	target,
		bool	umulp,
		enum optab_methods	methods
	)

static

Subroutine of expand_binop. Perform a double word multiplication of operands OP0 and OP1 both of mode MODE, which is exactly twice as wide as the target's word_mode. This function return NULL_RTX if anything goes wrong, in which case it may have already emitted instructions which need to be deleted.

If we want to multiply two two-word values and have normal and widening multiplies of single-word values, we can do this with three smaller multiplications.

The multiplication proceeds as follows:

[op0_high_|op0_low__]

[op1_high_|op1_low__]

(1) [op0_low*__op1_low__]

(2a) [op0_low*__op1_high_]

(2b) [op0_high_*op1_low__]

(3) [op0_high_*op1_high_]

This gives a 4-word result. Since we are only interested in the lower 2 words, partial result (3) and the upper words of (2a) and (2b) don't need to be calculated. Hence (2a) and (2b) can be calculated using non-widening multiplication.

(1), however, needs to be calculated with an unsigned widening multiplication. If this operation is not directly supported we try using a signed widening multiplication and adjust the result. This adjustment works as follows:

If both operands are positive then no adjustment is needed.

If the operands have different signs, for example op0_low < 0 and
op1_low >= 0, the instruction treats the most significant bit of
op0_low as a sign bit instead of a bit with significance
2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
with 2**BITS_PER_WORD - op0_low, and two's complements the
result.  Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
the result.

Similarly, if both operands are negative, we need to add
(op0_low + op1_low) * 2**BITS_PER_WORD.

We use a trick to adjust quickly.  We logically shift op0_low right
(op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
op0_high (op1_high) before it is used to calculate 2b (2a).  If no
logical shift exists, we do an arithmetic right shift and subtract
the 0 or -1.

 If we're using an unsigned multiply to directly compute the product
 of the low-order words of the operands and perform any required
 adjustments of the operands, we begin by trying two more multiplications
 and then computing the appropriate sum.

 We have checked above that the required addition is provided.
 Full-word addition will normally always succeed, especially if
 it is provided at all, so we don't worry about its failure.  The
 multiplication may well fail, however, so we do handle that.

     ??? This could be done with emit_store_flag where available.

 OP0_HIGH should now be dead.

     ??? This could be done with emit_store_flag where available.

 OP1_HIGH should now be dead.

static bool expand_doubleword_shift	(	enum machine_mode	op1_mode,
		optab	binoptab,
		rtx	outof_input,
		rtx	into_input,
		rtx	op1,
		rtx	outof_target,
		rtx	into_target,
		int	unsignedp,
		enum optab_methods	methods,
		unsigned HOST_WIDE_INT	shift_mask
	)

static

Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts. OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first input operand; the shift moves bits in the direction OUTOF_INPUT-> INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words of the target. OP1 is the shift count and OP1_MODE is its mode. If OP1 is constant, it will have been truncated as appropriate and is known to be nonzero.

If SHIFT_MASK is zero, the result of word shifts is undefined when the shift count is outside the range [0, BITS_PER_WORD). This routine must avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).

If SHIFT_MASK is nonzero, all word-mode shift counts are effectively masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will fill with zeros or sign bits as appropriate.

If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1. Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED. In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2) are undefined.

BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function may not use INTO_INPUT after modifying INTO_TARGET, and similarly for OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent function wants to calculate it itself.

Return true if the shift could be successfully synthesized.

 See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
 fill the result with sign or zero bits as appropriate.  If so, the value
 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1).   Recursively call
 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
 and INTO_INPUT), then emit code to set up OUTOF_TARGET.

 This isn't worthwhile for constant shifts since the optimizers will
 cope better with in-range shift counts.

 Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
 is true when the effective shift value is less than BITS_PER_WORD.
 Set SUPERWORD_OP1 to the shift count that should be used to shift
 OUTOF_INPUT into INTO_TARGET when the condition is false.

     Set CMP1 to OP1 & BITS_PER_WORD.  The result is zero iff OP1
     is a subword shift count.

     Set CMP1 to OP1 - BITS_PER_WORD.

 If we can compute the condition at compile time, pick the
 appropriate subroutine.

 As a last resort, use branches to select the correct alternative.

References CONST0_RTX, and simplify_expand_binop().

static rtx expand_ffs ( )

static

Try calculating ffs(x) using ctz(x) if we have that instruction, or else with the sequence used by expand_clz.

The ffs builtin promises to return zero for a zero value and ctz/clz may have an undefined value in that case. If they do not give us a convenient value, we have to generate a test and branch.

   No correction needed at zero.

     We don't try to do anything clever with the situation found
     on some processors (eg Alpha) where ctz(0:mode) ==
     bitsize(mode).  If someone can think of a way to send N to -1
     and leave alone all values in the range 0..N-1 (where N is a
     power of two), cheaper than this test-and-branch, please add it.

     The test-and-branch is done after the operation itself, in case
     the operation sets condition codes that can be recycled for this.
     (This is true on i386, for instance.)

 temp now has a value in the range -1..bitsize-1.  ffs is supposed
 to produce a value in the range 0..bitsize.

References emit_insn(), emit_move_insn(), end_sequence(), expand_binop(), get_insns(), immed_double_int_const(), operand_subword(), operand_subword_force(), OPTAB_LIB_WIDEN, and start_sequence().

void expand_fix ( )

Generate code to convert FROM to fixed point and store in TO. FROM must be floating point.

 We first try to find a pair of modes, one real and one integer, at
 least as wide as FROM and TO, respectively, in which we can open-code
 this conversion.  If the integer mode is wider than the mode of TO,
 we can do the conversion either signed or unsigned.

 For an unsigned conversion, there is one more way to do it.
 If we have a signed conversion, we generate code that compares
 the real value to the largest representable positive number.  If if
 is smaller, the conversion is done normally.  Otherwise, subtract
 one plus the highest signed number, convert, and add it back.

 We only need to check all real modes, since we know we didn't find
 anything with a wider integer mode.

 This code used to extend FP value into mode wider than the destination.
 This is needed for decimal float modes which cannot accurately
 represent one plus the highest signed number of the same size, but
 not for binary modes.  Consider, for instance conversion from SFmode
 into DImode.

 The hot path through the code is dealing with inputs smaller than 2^63
 and doing just the conversion, so there is no bits to lose.

 In the other path we know the value is positive in the range 2^63..2^64-1
 inclusive.  (as for other input overflow happens and result is undefined)
 So we know that the most important bit set in mantissa corresponds to
 2^63.  The subtraction of 2^63 should not generate any rounding as it
 simply clears out that bit.  The rest is trivial.

         See if we need to do the subtraction.

         If not, do the signed "fix" and branch around fixup code.

         Otherwise, subtract 2**(N-1), convert to signed number,
         then add 2**(N-1).  Do the addition using XOR since this
         will often generate better code.

             Make a place for a REG_NOTE and add it.

 We can't do it with an insn, so use a library call.  But first ensure
 that the mode of TO is at least as wide as SImode, since those are the
 only library calls we know about.

References code_to_optab(), and optab_handler().

Referenced by expand_float().

void expand_fixed_convert ( )

Generate code to convert FROM or TO a fixed-point. If UINTP is true, either TO or FROM is an unsigned integer. If SATP is true, we need to saturate the result.

void expand_float ( )

Generate code to convert FROM to floating point and store in TO. FROM must be fixed point and not VOIDmode. UNSIGNEDP nonzero means regard FROM as unsigned. Normally this is done by correcting the final value if it is negative.

 Crash now, because we won't be able to decide which mode to use.

 Look for an insn to do the conversion.  Do it in the specified
 modes if possible; otherwise convert either input, output or both to
 wider mode.  If the integer mode is wider than the mode of FROM,
 we can do the conversion signed even if the input is unsigned.

 Unsigned integer, and no way to convert directly.  Convert as signed,
 then unconditionally adjust the result.

     Look for a usable floating mode FMODE wider than the source and at
     least as wide as the target.  Using FMODE will avoid rounding woes
     with unsigned values greater than the signed maximum value.

         There is no such mode.  Pretend the target is wide enough.

         Avoid double-rounding when TO is narrower than FROM.

             Don't use TARGET if it isn't a register, is a hard register,
             or is the wrong mode.

             Test whether the sign bit is set.

             The sign bit is not set.  Convert as signed.

             The sign bit is set.
             Convert to a usable (positive signed) value by shifting right
             one bit, while remembering if a nonzero bit was shifted
             out; i.e., compute  (from & 1) | (from >> 1).

             Multiply by 2 to undo the shift above.

     If we are about to do some arithmetic to correct for an
     unsigned operand, do it in a pseudo-register.

     Convert as signed integer to floating.

     If FROM is negative (and therefore TO is negative),
     correct its value by 2**bitwidth.

 No hardware instruction available; call a library routine.

 Copy result to requested destination
 if we have been computing in a temp location.

References CONST_DOUBLE_FROM_REAL_VALUE, convert_to_mode(), copy_rtx(), do_pending_stack_adjust(), emit_barrier(), emit_cmp_and_jump_insns(), emit_jump_insn(), emit_label(), emit_move_insn(), expand_binop(), expand_fix(), gen_int_mode(), gen_label_rtx(), GET_MODE_PRECISION, HOST_WIDE_INT, limit, NULL_RTX, offset, optab_handler(), OPTAB_LIB_WIDEN, real_2expN(), REAL_VALUE_TYPE, and set_dst_reg_note().

void expand_insn	(	enum insn_code	icode,
		unsigned int	nops,
		struct expand_operand *	ops
	)

Emit instruction ICODE, using operands [OPS, OPS + NOPS) as its operands.

void expand_jump_insn	(	enum insn_code	icode,
		unsigned int	nops,
		struct expand_operand *	ops
	)

Like expand_insn, but for jumps.

void expand_mem_signal_fence ( )

By default targets are coherent between a thread and the signal handler running on the same thread. Thus this really becomes a compiler barrier, in that stores must not be sunk past (or raised above) a given point.

References const0_rtx, expand_atomic_fetch_op_no_fallback(), and GET_MODE.

void expand_mem_thread_fence ( )

References expand_simple_binop(), expand_simple_unop(), NULL_RTX, and OPTAB_LIB_WIDEN.

Referenced by expand_builtin_atomic_compare_exchange(), and expand_sync_lock_test_and_set().

rtx expand_mult_highpart	(	enum machine_mode	mode,
		rtx	op0,
		rtx	op1,
		rtx	target,
		bool	uns_p
	)

Expand a highpart multiply.

References targetm.

rtx expand_one_cmpl_abs_nojump ( )

Emit code to compute the one's complement absolute value of OP0 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient. (TARGET may be NULL_RTX.) The return value says where the result actually is to be found.

MODE is the mode of the operand; the mode of the result is different but can be deduced from MODE.

 Not applicable for floating point modes.

 If we have a MAX insn, we can do this as MAX (x, ~x).

 If this machine has expensive jumps, we can do one's complement
 absolute value of X as (((signed) x >> (W-1)) ^ x).

static rtx expand_parity ( )

static

Try calculating (parity x) as (and (popcount x) 1), where popcount can also be done in a wider mode.

bool expand_sfix_optab ( )

Generate code to convert FROM to fixed point and store in TO. FROM must be floating point, TO must be signed. Use the conversion optab TAB to do the conversion.

We first try to find a pair of modes, one real and one integer, at least as wide as FROM and TO, respectively, in which we can open-code this conversion. If the integer mode is wider than the mode of TO, we can do the conversion either signed or unsigned.

References DECIMAL_FLOAT_MODE_P, DECIMAL_PREFIX, GET_MODE_NAME, and targetm.

Referenced by expand_builtin_sincos().

rtx expand_simple_binop	(	enum machine_mode	mode,
		enum rtx_code	code,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	unsignedp,
		enum optab_methods	methods
	)

Wrapper around expand_binop which takes an rtx code to specify the operation to perform, not an optab pointer. All other arguments are the same.

Referenced by expand_builtin_sync_operation(), expand_mem_thread_fence(), noce_try_addcc(), noce_try_store_flag_constants(), and split_edge_and_insert().

rtx expand_simple_unop	(	enum machine_mode	mode,
		enum rtx_code	code,
		rtx	op0,
		rtx	target,
		int	unsignedp
	)

Wrapper around expand_unop which takes an rtx code to specify the operation to perform, not an optab pointer. All other arguments are the same.

Referenced by expand_atomic_load(), expand_builtin_sync_operation(), and expand_mem_thread_fence().

static bool expand_subword_shift	(	enum machine_mode	op1_mode,
		optab	binoptab,
		rtx	outof_input,
		rtx	into_input,
		rtx	op1,
		rtx	outof_target,
		rtx	into_target,
		int	unsignedp,
		enum optab_methods	methods,
		unsigned HOST_WIDE_INT	shift_mask
	)

static

This subroutine of expand_doubleword_shift handles the cases in which the effective shift value is < BITS_PER_WORD. The arguments and return value are the same as for the parent routine.

 The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
 the opposite direction to BINOPTAB.

     We must avoid shifting by BITS_PER_WORD bits since that is either
     the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
     has unknown behavior.  Do a single shift first, then shift by the
     remainder.  It's OK to use ~OP1 as the remainder if shift counts
     are truncated to the mode size.

 Shift INTO_INPUT logically by OP1.  This is the last use of INTO_INPUT
 so the result can go directly into INTO_TARGET if convenient.

 Now OR in the bits carried over from OUTOF_INPUT.

 Use a standard word_mode shift for the out-of half.

References BITS_PER_WORD, immed_double_const(), and simplify_expand_binop().

static bool expand_superword_shift	(	optab	binoptab,
		rtx	outof_input,
		rtx	superword_op1,
		rtx	outof_target,
		rtx	into_target,
		int	unsignedp,
		enum optab_methods	methods
	)

static

This subroutine of expand_doubleword_shift handles the cases in which the effective shift value is >= BITS_PER_WORD. The arguments and return value are the same as for the parent routine, except that SUPERWORD_OP1 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET. INTO_TARGET may be null if the caller has decided to calculate it.

For a signed right shift, we must fill OUTOF_TARGET with copies of the sign bit, otherwise we must fill it with zeros.

References BITS_PER_WORD, immed_double_const(), and simplify_expand_binop().

rtx expand_sync_lock_test_and_set ( )

This function expands the legacy _sync_lock test_and_set operation which is generally an atomic exchange. Some limited targets only allow the constant 1 to be stored. This is an ACQUIRE operation.

TARGET is an optional place to stick the return value. MEM is where VAL is stored.

Try an atomic_exchange first.

 If there are no other options, try atomic_test_and_set if the value
 being stored is 1.

References const0_rtx, create_fixed_operand(), create_input_operand(), expand_mem_thread_fence(), maybe_expand_insn(), and MEMMODEL_SEQ_CST.

rtx expand_ternary_op	(	enum machine_mode	mode,
		optab	ternary_optab,
		rtx	op0,
		rtx	op1,
		rtx	op2,
		rtx	target,
		int	unsignedp
	)

Generate code to perform an operation specified by TERNARY_OPTAB on operands OP0, OP1 and OP2, with result having machine-mode MODE.

UNSIGNEDP is for the case where we have to widen the operands to perform the operation. It says to use zero-extension.

If TARGET is nonzero, the value is generated there, if it is convenient to do so. In all cases an rtx is returned for the locus of the value; this may or may not be TARGET.

int expand_twoval_binop	(	optab	binoptab,
		rtx	op0,
		rtx	op1,
		rtx	targ0,
		rtx	targ1,
		int	unsignedp
	)

Generate code to perform an operation specified by BINOPTAB on operands OP0 and OP1, with two results to TARG1 and TARG2. We assume that the order of the operands for the instruction is TARG0, OP0, OP1, TARG1, which would fit a pattern like [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].

Either TARG0 or TARG1 may be zero, but what that means is that the result is not actually wanted. We will generate it into a dummy pseudo-reg and discard it. They may not both be zero.

Returns 1 if this operation can be performed; 0 if not.

 Record where to go back to if we fail.

     If we are optimizing, force expensive constants into a register.

 It can't be done in this mode.  Can we do it in a wider mode?

bool expand_twoval_binop_libfunc	(	optab	binoptab,
		rtx	op0,
		rtx	op1,
		rtx	targ0,
		rtx	targ1,
		enum rtx_code	code
	)

Expand the two-valued library call indicated by BINOPTAB, but preserve only one of the values. If TARG0 is non-NULL, the first value is placed into TARG0; otherwise the second value is placed into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1). This routine assumes that the value returned by the library call is as if the return value was of an integral mode twice as wide as the mode of OP0. Returns 1 if the call was successful.

 Exactly one of TARG0 or TARG1 should be non-NULL.

 The value returned by the library function will have twice as
 many bits as the nominal MODE.

 Get the part of VAL containing the value that we want.

 Move the into the desired location.

int expand_twoval_unop	(	optab	unoptab,
		rtx	op0,
		rtx	targ0,
		rtx	targ1,
		int	unsignedp
	)

Generate code to perform an operation specified by UNOPPTAB on operand OP0, with two results to TARG0 and TARG1. We assume that the order of the operands for the instruction is TARG0, TARG1, OP0.

Either TARG0 or TARG1 may be zero, but what that means is that the result is not actually wanted. We will generate it into a dummy pseudo-reg and discard it. They may not both be zero.

Returns 1 if this operation can be performed; 0 if not.

Record where to go back to if we fail.

 It can't be done in this mode.  Can we do it in a wider mode?

rtx expand_unop	(	enum machine_mode	mode,
		optab	unoptab,
		rtx	op0,
		rtx	target,
		int	unsignedp
	)

Generate code to perform an operation specified by UNOPTAB on operand OP0, with result having machine-mode MODE.

UNSIGNEDP is for the case where we have to widen the operands to perform the operation. It says to use zero-extension.

If TARGET is nonzero, the value is generated there, if it is convenient to do so. In all cases an rtx is returned for the locus of the value; this may or may not be TARGET.

 It can't be done in this mode.  Can we open-code it in a wider mode?

 Widening (or narrowing) clz needs special treatment.

 Widening (or narrowing) bswap needs special treatment.

     HImode is special because in this mode BSWAP is equivalent to ROTATE
     or ROTATERT.  First try these directly; if this fails, then try the
     obvious pair of shifts with allowed widening, as this will probably
     be always more efficient than the other fallback methods.

           For certain operations, we need not actually extend
           the narrow operand, as long as we will truncate the
           results to the same narrowness.

 These can be done a word at a time.

     Do the actual arithmetic.

     Try negating floating point values by flipping the sign bit.

     If there is no negation pattern, and we have no negative zero,
     try subtracting from zero.

 Try calculating parity (x) as popcount (x) % 2.

 Try implementing ffs (x) in terms of clz (x).

 Try implementing ctz (x) in terms of clz (x).

 Now try a library call in this mode.

     All of these functions return small values.  Thus we choose to
     have them return something that isn't a double-word.

     Pass 1 for NO_QUEUE so we don't lose any increments
     if the libcall is cse'd or moved.

 It can't be done in this mode.  Can we do it in a wider mode?

             For certain operations, we need not actually extend
             the narrow operand, as long as we will truncate the
             results to the same narrowness.

             If we are generating clz using wider mode, adjust the
             result.  Similarly for clrsb.

             Likewise for bswap.

 One final attempt at implementing negation via subtraction,
 this time allowing widening of the operand.

Referenced by expand_doubleword_clz(), noce_emit_store_flag(), stabilize_va_list_loc(), and supportable_convert_operation().

static rtx expand_unop_direct	(	enum machine_mode	mode,
		optab	unoptab,
		rtx	op0,
		rtx	target,
		int	unsignedp
	)

static

As expand_unop, but will fail rather than attempt the operation in a different mode or with a libcall.

Referenced by lowpart_subreg_maybe_copy().

rtx expand_vec_cond_expr	(	tree	vec_cond_type,
		tree	op0,
		tree	op1,
		tree	op2,
		rtx	target
	)

Generate insns for a VEC_COND_EXPR, given its TYPE and its three operands.

Fake op0 < 0.

bool expand_vec_cond_expr_p ( )

Return TRUE iff, appropriate vector insns are available for vector cond expr with vector type VALUE_TYPE and a comparison with operand vector types in CMP_OP_TYPE.

rtx expand_vec_perm ( )

Generate instructions for vec_perm optab given its mode and three operands.

 Set QIMODE to a different vector mode with byte elements.
 If no such mode, or if MODE already has byte elements, use VOIDmode.

 If the input is a constant, expand it specially.

     Fall back to a constant byte-based permutation.

 Otherwise expand as a fully variable permuation.

 As a special case to aid several targets, lower the element-based
 permutation to a byte-based permutation and try again.

     Multiply each element by its byte size.

     Broadcast the low byte each element into each of its bytes.

     Add the byte offset to each byte element.

     Note that the definition of the indicies here is memory ordering,
     so there should be no difference between big and little endian.

static rtx expand_vec_perm_1	(	enum insn_code	icode,
		rtx	target,
		rtx	v0,
		rtx	v1,
		rtx	sel
	)

static

A subroutine of expand_vec_perm for expanding one vec_perm insn.

Make an effort to preserve v0 == v1. The target expander is able to rely on this to determine if we're permuting a single input operand.

rtx expand_vec_shift_expr ( )

Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR.

static rtx expand_vector_broadcast ( )

static

Create a new vector value in VMODE with all elements set to OP. The mode of OP must be the element mode of VMODE. If OP is a constant, then the return value will be a constant.

??? If the target doesn't have a vec_init, then we have no easy way of performing this operation. Most of this sort of generic support is hidden away in the vector lowering support in gimple.

References BITS_PER_WORD, CONST0_RTX, emit_move_insn(), force_expand_binop(), GEN_INT, and word_mode.

rtx expand_widen_pattern_expr	(	sepops	ops,
		rtx	op0,
		rtx	op1,
		rtx	wide_op,
		rtx	target,
		int	unsignedp
	)

Expand vector widening operations.

There are two different classes of operations handled here: 1) Operations whose result is wider than all the arguments to the operation. Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR In this case OP0 and optionally OP1 would be initialized, but WIDE_OP wouldn't (not relevant for this case). 2) Operations whose result is of the same size as the last argument to the operation, but wider than all the other arguments to the operation. Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR. In the case WIDE_OP, OP0 and optionally OP1 would be initialized.

E.g, when called to expand the following operations, this is how the arguments will be initialized: nops OP0 OP1 WIDE_OP widening-sum 2 oprnd0 - oprnd1 widening-dot-product 3 oprnd0 oprnd1 oprnd2 widening-mult 2 oprnd0 oprnd1 - type-promotion (vec-unpack) 1 oprnd0 - -

The last operand is of a wider mode than the rest of the operands.

static void find_cc_set ( )

static

Helper function to find the MODE_CC set in a sync_compare_and_swap pattern.

enum insn_code find_widening_optab_handler_and_mode	(	optab	op,
		enum machine_mode	to_mode,
		enum machine_mode	from_mode,
		int	permit_non_widening,
		enum machine_mode *	found_mode
	)

Find a widening optab even if it doesn't widen as much as we want. E.g. if from_mode is HImode, and to_mode is DImode, and there is no direct HI->SI insn, then return SI->DI, if that exists. If PERMIT_NON_WIDENING is non-zero then this can be used with non-widening optabs also.

bool force_expand_binop	(	enum machine_mode	mode,
		optab	binoptab,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	unsignedp,
		enum optab_methods	methods
	)

Like simplify_expand_binop, but always put the result in TARGET. Return true if the expansion succeeded.

Referenced by expand_vector_broadcast().

rtx gen_add2_insn ( )

These functions attempt to generate an insn body, rather than emitting the insn, but if the gen function already emits them, we make no attempt to turn them back into naked patterns. Generate and return an insn body to add Y to X.

rtx gen_add3_insn ( )

Generate and return an insn body to add r1 and c, storing the result in r0.

rtx gen_cond_trap ( )

Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition CODE. Return 0 on failure.

Some targets only accept a zero trap code.

 If that failed, then give up.

void gen_extend_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Pick proper libcall for extend_optab. We need to chose if we do truncation or extension and interclass or intraclass.

rtx gen_extend_insn	(	rtx	x,
		rtx	y,
		enum machine_mode	mto,
		enum machine_mode	mfrom,
		int	unsignedp
	)

Generate the body of an insn to extend Y (with mode MFROM) into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero.

void gen_fixed_libfunc	(	optab	optable,
		const char *	opname,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that fixed-point operation is involved.

References targetm.

void gen_fp_libfunc	(	optab	optable,
		const char *	opname,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that FP and set decimal prefix if needed.

For BID support, change the name to have either a bid_ or dpd_ prefix depending on the low level floating format used.

void gen_fp_to_int_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Same as gen_interclass_conv_libfunc but verify that we are producing fp->int conversion with no decimal floating point involved.

References init_one_libfunc(), libfunc_hash, libfunc_entry::mode1, libfunc_entry::mode2, NULL, and libfunc_entry::op.

void gen_fract_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Pick proper libcall for fract_optab. We need to chose if we do interclass or intraclass.

void gen_fractuns_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Pick proper libcall for fractuns_optab.

One mode must be a fixed-point mode, and the other must be an integer mode.

References GET_MODE_2XWIDER_MODE, and set_optab_libfunc().

void gen_int_fixed_libfunc	(	optab	optable,
		const char *	name,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that INT or FIXED operation is involved.

void gen_int_fp_fixed_libfunc	(	optab	optable,
		const char *	name,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that FP or INT or FIXED operation is involved.

void gen_int_fp_libfunc	(	optab	optable,
		const char *	name,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that FP or INT operation is involved.

void gen_int_fp_signed_fixed_libfunc	(	optab	optable,
		const char *	name,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that FP or INT or signed FIXED operation is involved.

References DECIMAL_FLOAT_MODE_P, gen_interclass_conv_libfunc(), GET_MODE_CLASS, and GET_MODE_PRECISION.

void gen_int_libfunc	(	optab	optable,
		const char *	opname,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that integer operation is involved.

References gen_interclass_conv_libfunc(), and GET_MODE_CLASS.

void gen_int_signed_fixed_libfunc	(	optab	optable,
		const char *	name,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that INT or signed FIXED operation is involved.

References ALL_FIXED_POINT_MODE_P, gen_interclass_conv_libfunc(), gen_intraclass_conv_libfunc(), and GET_MODE_CLASS.

void gen_int_to_fp_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Same as gen_interclass_conv_libfunc but verify that we are producing int->fp conversion.

void gen_int_to_fp_nondecimal_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Same as gen_interclass_conv_libfunc but verify that we are producing fp->int conversion.

References DECL_RTL, gcc_assert, get_identifier(), IDENTIFIER_HASH_VALUE, set_user_assembler_name(), and XEXP.

void gen_int_unsigned_fixed_libfunc	(	optab	optable,
		const char *	name,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that INT or unsigned FIXED operation is involved.

References ALL_FIXED_POINT_MODE_P, gen_interclass_conv_libfunc(), and GET_MODE_CLASS.

void gen_interclass_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Initialize the libfunc fields of an entire group of entries of an inter-mode-class conversion optab. The string formation rules are similar to the ones for init_libfuncs, above, but instead of having a mode name and an operand count these functions have two mode names and no operand count.

If this is a decimal conversion, add the current BID vs. DPD prefix that depends on which underlying decimal floating point format is used.

Referenced by gen_int_fp_signed_fixed_libfunc(), gen_int_libfunc(), gen_int_signed_fixed_libfunc(), gen_int_unsigned_fixed_libfunc(), and gen_libfunc().

void gen_intraclass_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Initialize the libfunc fields of an of an intra-mode-class conversion optab. The string formation rules are similar to the ones for init_libfunc, above.

If this is a decimal conversion, add the current BID vs. DPD prefix that depends on which underlying decimal floating point format is used.

Referenced by gen_int_signed_fixed_libfunc().

void gen_intv_fp_libfunc	(	optab	optable,
		const char *	name,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that FP or INT operation is involved and add 'v' suffix for integer operation.

static void gen_libfunc	(	optab	optable,
		const char *	opname,
		int	suffix,
		enum machine_mode	mode
	)

static

Initialize the libfunc fields of an entire group of entries in some optab. Each entry is set equal to a string consisting of a leading pair of underscores followed by a generic operation name followed by a mode name (downshifted to lowercase) followed by a single character representing the number of operands for the given operation (which is usually one of the characters '2', '3', or '4').

OPTABLE is the table in which libfunc fields are to be initialized. OPNAME is the generic (string) name of the operation. SUFFIX is the character which specifies the number of operands for the given generic operation. MODE is the mode to generate for.

References DECIMAL_FLOAT_MODE_P, gen_interclass_conv_libfunc(), and GET_MODE_CLASS.

rtx gen_move_insn ( )

Generate the body of an instruction to copy Y into X. It may be a list of insns, if one insn isn't enough.

void gen_satfract_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Pick proper libcall for satfract_optab. We need to chose if we do interclass or intraclass.

TMODE must be a fixed-point mode.

void gen_satfractuns_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Pick proper libcall for satfractuns_optab.

TMODE must be a fixed-point mode, and FMODE must be an integer mode.

References gcc_assert, GET_CODE, GET_MODE_NAME, GET_RTX_NAME, optab_libfunc(), optab_to_code(), and XSTR.

void gen_signed_fixed_libfunc	(	optab	optable,
		const char *	opname,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that signed fixed-point operation is involved.

rtx gen_sub2_insn ( )

Generate and return an insn body to subtract Y from X.

rtx gen_sub3_insn ( )

Generate and return an insn body to subtract r1 and c, storing the result in r0.

void gen_trunc_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

Pick proper libcall for trunc_optab. We need to chose if we do truncation or extension and interclass or intraclass.

References targetm.

void gen_ufloat_conv_libfunc	(	convert_optab	tab,
		const char *	opname,
		enum machine_mode	tmode,
		enum machine_mode	fmode
	)

ufloat_optab is special by using floatun for FP and floatuns decimal fp naming scheme.

void gen_unsigned_fixed_libfunc	(	optab	optable,
		const char *	opname,
		char	suffix,
		enum machine_mode	mode
	)

Like gen_libfunc, but verify that unsigned fixed-point operation is involved.

static void get_atomic_op_for_code ( )

static

Fill in structure pointed to by OP with the various optab entries for an operation of type CODE.

If SWITCHABLE_TARGET is defined, then subtargets can be switched in the source code during compilation, and the optab entries are not computable until runtime. Fill in the values at runtime.

References copy_to_mode_reg(), delete_insns_since(), get_address_mode(), get_last_insn(), insn_operand_matches(), last, replace_equiv_address(), and expand_operand::value.

static bool get_best_extraction_insn	(	extraction_insn *	insn,
		enum extraction_pattern	pattern,
		enum extraction_type	type,
		unsigned HOST_WIDE_INT	struct_bits,
		enum machine_mode	field_mode
	)

static

Return true if an instruction exists to access a field of mode FIELDMODE in a structure that has STRUCT_BITS significant bits. Describe the "best" such instruction in *INSN if so. PATTERN and TYPE describe the type of insertion or extraction we want to perform.

For an insertion, the number of significant structure bits includes all bits of the target. For an extraction, it need only include the most significant bit of the field. Larger widths are acceptable in both cases.

bool get_best_mem_extraction_insn	(	extraction_insn *	insn,
		enum extraction_pattern	pattern,
		HOST_WIDE_INT	bitsize,
		HOST_WIDE_INT	bitnum,
		enum machine_mode	field_mode
	)

Return true if an instruction exists to access a field of BITSIZE bits starting BITNUM bits into a memory structure. Describe the "best" such instruction in *INSN if so. PATTERN describes the type of insertion or extraction we want to perform and FIELDMODE is the natural mode of the extracted field.

The instructions considered here only access bytes that overlap the bitfield; they do not touch any surrounding bytes.

bool get_best_reg_extraction_insn	(	extraction_insn *	insn,
		enum extraction_pattern	pattern,
		unsigned HOST_WIDE_INT	struct_bits,
		enum machine_mode	field_mode
	)

Return true if an instruction exists to access a field of mode FIELDMODE in a register structure that has STRUCT_BITS significant bits. Describe the "best" such instruction in *INSN if so. PATTERN describes the type of insertion or extraction we want to perform.

For an insertion, the number of significant structure bits includes all bits of the target. For an extraction, it need only include the most significant bit of the field. Larger widths are acceptable in both cases.

static bool get_extraction_insn	(	extraction_insn *	insn,
		enum extraction_pattern	pattern,
		enum extraction_type	type,
		enum machine_mode	mode
	)

static

Return true if an instruction exists to perform an insertion or extraction (PATTERN says which) of type TYPE in mode MODE. Describe the instruction in *INSN if so.

static bool get_optab_extraction_insn	(	struct extraction_insn *	insn,
		enum extraction_type	type,
		enum machine_mode	mode,
		direct_optab	reg_optab,
		direct_optab	misalign_optab,
		int	pos_op
	)

static

Return true if an optab exists to perform an insertion or extraction of type TYPE in mode MODE. Describe the instruction in *INSN if so.

REG_OPTAB is the optab to use for register structures and MISALIGN_OPTAB is the optab to use for misaligned memory structures. POS_OP is the operand number of the bit position.

static enum rtx_code get_rtx_code ( )

static

Return rtx code for TCODE. Use UNSIGNEDP to select signed or unsigned operation code.

static bool get_traditional_extraction_insn	(	extraction_insn *	insn,
		enum extraction_type	type,
		enum machine_mode	mode,
		enum insn_code	icode,
		int	struct_op,
		int	field_op
	)

static

Check whether insv, extv or extzv pattern ICODE can be used for an insertion or extraction of type TYPE on a structure of mode MODE. Return true if so and fill in *INSN accordingly. STRUCT_OP is the operand number of the structure (the first sign_extract or zero_extract operand) and FIELD_OP is the operand number of the field (the other side of the set from the sign_extract or zero_extract).

static enum insn_code get_vcond_icode ( )

inlinestatic

Return insn code for a conditional operator with a comparison in mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE.

static hashval_t hash_libfunc ( )

static

Used for libfunc_hash.

References libfunc_entry::mode1, libfunc_entry::mode2, and libfunc_entry::op.

int have_add2_insn ( )

References can_float_p(), convert_to_mode(), GET_MODE_PRECISION, and significand_size().

int have_insn_for ( )

Report whether we have an instruction to perform the operation specified by CODE on operands of mode MODE.

int have_sub2_insn ( )

References const0_rtx, do_pending_stack_adjust(), emit_cmp_and_jump_insns(), gen_label_rtx(), gen_reg_rtx(), GET_MODE, GET_MODE_PRECISION, NULL_RTX, REG_P, REGNO, and significand_size().

rtx init_one_libfunc ( )

See if we have already created a libfunc decl for this function.

     Create a new decl, so that it can be passed to
     targetm.encode_section_info.

void init_optabs ( void )

Call this to initialize the contents of the optabs appropriately for the current target machine.

 Fill in the optabs with the insns we support.

 The ffs function operates on `int'.  Fall back on it if we do not
 have a libgcc2 function for that width.

 Explicitly initialize the bswap libfuncs since we need them to be
 valid for things other than word_mode.

 Use cabs for double complex abs, since systems generally have cabs.
 Don't define any libcall for float complex, so that cabs will be used.

 For function entry/exit instrumentation.

 Allow the target to add more libcalls or rename some, etc.

References direct_optab_handler(), GET_MODE_INNER, GET_MODE_SIZE, GET_MODE_UNIT_SIZE, mode_for_vector(), NULL, optab_handler(), targetm, and VECTOR_MODE_P.

void init_sync_libfuncs ( )

static void init_sync_libfuncs_1 ( )

static

A helper function for init_sync_libfuncs. Using the basename BASE, install libfuncs into TAB for BASE_N for 1 <= N <= MAX.

void init_tree_optimization_optabs ( )

Use the current target and options to initialize TREE_OPTIMIZATION_OPTABS (OPTNODE).

 Quick exit if we have already computed optabs for this target.

 Forget any previous information and set up for the current target.

 Generate a new set of optabs into tmp_optabs.

 If the optabs changed, record it.

Referenced by blocks_nreverse_all().

bool insn_operand_matches ( )

Return true if OPERAND is suitable for operand number OPNO of instruction ICODE.

Referenced by build_libfunc_function(), do_output_reload(), get_atomic_op_for_code(), and maybe_emit_unop_insn().

static int libfunc_decl_eq ( )

static

static hashval_t libfunc_decl_hash ( )

static

Hashtable callbacks for libfunc_decls.

static rtx lowpart_subreg_maybe_copy	(	enum machine_mode	omode,
		rtx	val,
		enum machine_mode	imode
	)

static

Extract the OMODE lowpart from VAL, which has IMODE. Under certain conditions, VAL may already be a SUBREG against which we cannot generate a further SUBREG. In this case, we expect forcing the value into a register will work around the situation.

References expand_unop_direct(), and GET_MODE_CLASS.

static rtx maybe_emit_atomic_exchange ( )

static

This function tries to emit an atomic_exchange intruction. VAL is written to *MEM using memory model MODEL. The previous contents of *MEM are returned, using TARGET if possible.

If the target supports the exchange directly, great.

References emit_insn(), empty_string, gen_rtvec(), gen_rtx_MEM(), MEM_VOLATILE_P, rtvec_alloc(), and UNKNOWN_LOCATION.

Referenced by expand_atomic_compare_and_swap().

static rtx maybe_emit_atomic_test_and_set ( )

static

While we always get QImode from __atomic_test_and_set, we get other memory modes from __sync_lock_test_and_set. Note that we use no endian adjustment here. This matches the 4.6 behavior in the Sparc backend.

static rtx maybe_emit_compare_and_swap_exchange_loop ( )

static

This function tries to implement an atomic exchange operation using a compare_and_swap loop. VAL is written to *MEM. The previous contents of *MEM are returned, using TARGET if possible. No memory model is required since a compare_and_swap loop is seq-cst.

static rtx maybe_emit_op	(	const struct atomic_op_functions *	optab,
		rtx	target,
		rtx	mem,
		rtx	val,
		bool	use_memmodel,
		enum memmodel	model,
		bool	after
	)

static

Try to emit an instruction for a specific operation varaition. OPTAB contains the OP functions. TARGET is an optional place to return the result. const0_rtx means unused. MEM is the memory location to operate on. VAL is the value to use in the operation. USE_MEMMODEL is TRUE if the variation with a memory model should be tried. MODEL is the memory model, if used. AFTER is true if the returned result is the value after the operation.

 Check to see if there is a result returned.

 Otherwise, we need to generate a result.

 VAL may have been promoted to a wider mode.  Shrink it if so.

static rtx maybe_emit_sync_lock_test_and_set	(	rtx	target,
		rtx	mem,
		rtx	val,
		enum memmodel	model
	)

static

This function tries to implement an atomic exchange operation using __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL. The previous contents of *MEM are returned, using TARGET if possible. Since this instructionn is an acquire barrier only, stronger memory models may require additional barriers to be emitted.

 Legacy sync_lock_test_and_set is an acquire barrier.  If the pattern
 exists, and the memory model is stronger than acquire, add a release 
 barrier before the instruction.

 If an external test-and-set libcall is provided, use that instead of
 any external compare-and-swap that we might get from the compare-and-
 swap-loop expansion later.

 If the test_and_set can't be emitted, eliminate any barrier that might
 have been emitted.

References emit_insn(), emit_library_call(), expand_asm_memory_barrier(), GEN_INT, gen_mem_thread_fence, gen_memory_barrier, HAVE_mem_thread_fence, HAVE_memory_barrier, LCT_NORMAL, MEMMODEL_RELAXED, NULL_RTX, and synchronize_libfunc.

bool maybe_emit_unop_insn	(	enum insn_code	icode,
		rtx	target,
		rtx	op0,
		enum rtx_code	code
	)

Generate an instruction whose insn-code is INSN_CODE, with two operands: an output TARGET and an input OP0. TARGET must be nonzero, and the output is always stored there. CODE is an rtx code such that (CODE OP0) is an rtx that describes the value that is stored into TARGET.

Return false if expansion failed.

References ccp_cmov, ccp_jump, ccp_store_flag, const0_rtx, GET_MODE_WIDER_MODE, insn_operand_matches(), optab_handler(), and PUT_MODE.

Referenced by supportable_convert_operation().

bool maybe_expand_insn	(	enum insn_code	icode,
		unsigned int	nops,
		struct expand_operand *	ops
	)

Try to emit instruction ICODE, using operands [OPS, OPS + NOPS) as its operands. Return true on success and emit no code on failure.

Referenced by block_move_libcall_safe_for_call_parm(), clear_storage_hints(), expand_builtin_update_setjmp_buf(), expand_sync_lock_test_and_set(), and push_block().

bool maybe_expand_jump_insn	(	enum insn_code	icode,
		unsigned int	nops,
		struct expand_operand *	ops
	)

Like maybe_expand_insn, but for jumps.

rtx maybe_gen_insn	(	enum insn_code	icode,
		unsigned int	nops,
		struct expand_operand *	ops
	)

Try to generate instruction ICODE, using operands [OPS, OPS + NOPS) as its operands. Return the instruction pattern on success, and emit any necessary set-up code. Return null and emit no code on failure.

Referenced by expand_atomic_fetch_op_no_fallback().

static bool maybe_legitimize_operand	(	enum insn_code	icode,
		unsigned int	opno,
		struct expand_operand *	op
	)

static

Try to make OP match operand OPNO of instruction ICODE. Return true on success, storing the new operand value back in OP.

The caller must tell us what mode this value has.

static bool maybe_legitimize_operand_same_code	(	enum insn_code	icode,
		unsigned int	opno,
		struct expand_operand *	op
	)

static

Like maybe_legitimize_operand, but do not change the code of the current rtx value.

See if the operand matches in its current form.

 If the operand is a memory whose address has no side effects,
 try forcing the address into a non-virtual pseudo register.
 The check for side effects is important because copy_to_mode_reg
 cannot handle things like auto-modified addresses.

bool maybe_legitimize_operands	(	enum insn_code	icode,
		unsigned int	opno,
		unsigned int	nops,
		struct expand_operand *	ops
	)

Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS) of instruction ICODE. Return true on success, leaving the new operand values in the OPS themselves. Emit no code on failure.

static rtx maybe_optimize_fetch_op	(	rtx	target,
		rtx	mem,
		rtx	val,
		enum rtx_code	code,
		enum memmodel	model,
		bool	after
	)

static

See if there is a more optimal way to implement the operation "*MEM CODE VAL" using memory order MODEL. If AFTER is true the operation needs to return the value of *MEM after the operation, otherwise the previous value. TARGET is an optional place to place the result. The result is unused if it is const0_rtx. Return the result if there is a better sequence, otherwise NULL_RTX.

 If the value is prefetched, or not used, it may be possible to replace
 the sequence with a native exchange operation.

     fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m).

     fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m).

static void no_conflict_move_test ( )

static

Called via note_stores by emit_libcall_block. Set P->must_stay if the currently examined clobber / store has to stay in the list of insns that constitute the actual libcall block.

 If this inns directly contributes to setting the target, it must stay.

 If we haven't committed to keeping any other insns in the list yet,
 there is nothing more to check.

 If this insn sets / clobbers a register that feeds one of the insns
 already in the list, this insn has to stay too.

          Likewise if this insn depends on a register set by a previous
          insn in the list, or if it sets a result (presumably a hard
          register) that is set or clobbered by a previous insn.
          N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
          SET_DEST perform the former check on the address, and the latter
          check on the MEM.

References CONSTANT_P, COSTS_N_INSNS, force_reg(), gcc_assert, GET_MODE, OPTAB_DIRECT, OPTAB_LIB_WIDEN, OPTAB_WIDEN, optimize_insn_for_speed_p(), and rtx_cost().

Referenced by expand_copysign().

optab optab_for_tree_code	(	enum tree_code	code,
		const_tree	type,
		enum optab_subtype	subtype
	)

Return the optab used for computing the operation given by the tree code, CODE and the tree EXP. This function is not always usable (for example, it cannot give complete results for multiplication or division) but probably ought to be relied on more widely throughout the expander.

     The signedness is determined from input operand.

     The signedness is determined from input operand.

     The signedness is determined from output operand.

References gcc_assert, optab_scalar, optab_vector, TYPE_SATURATING, and unknown_optab.

Referenced by add_rshift(), supportable_widening_operation(), vect_build_slp_tree_1(), and vect_recog_rotate_pattern().

rtx optab_libfunc ( )

Return libfunc corresponding operation defined by OPTAB in MODE. Trigger lazy initialization if needed, return NULL if no libfunc is available.

??? This ought to be an assert, but not all of the places that we expand optabs know about the optabs that got moved to being direct.

References optab_libcall_d::libcall_basename, optab_libcall_d::libcall_gen, optab_libcall_d::libcall_suffix, libfunc_hash, normlib_def, and NULL.

Referenced by gen_satfractuns_conv_libfunc().

static void prepare_cmp_insn	(	rtx	x,
		rtx	y,
		enum rtx_code	comparison,
		rtx	size,
		int	unsignedp,
		enum optab_methods	methods,
		rtx *	ptest,
		enum machine_mode *	pmode
	)

static

This function is called when we are going to emit a compare instruction that compares the values found in *PX and *PY, using the rtl operator COMPARISON.

*PMODE is the mode of the inputs (in case they are const_int). *PUNSIGNEDP nonzero says that the operands are unsigned; this matters if they need to be widened (as given by METHODS).

If they have mode BLKmode, then SIZE specifies the size of both operands.

This function performs all the setup necessary so that the caller only has to emit a single comparison insn. This setup can involve doing a BLKmode comparison or emitting a library call to perform the comparison if no insn is available to handle it. The values which are passed in through pointers can be modified; the caller should perform the comparison on the modified values. Constant comparisons must have already been folded.

 The other methods are not needed.

 If we are optimizing, force expensive constants into a register.

 Don't let both operands fail to indicate the mode.

 Handle all BLKmode compares.

     Try to use a memory block compare insn - either cmpstr
     or cmpmem will do.

         Must make sure the size fits the insn's mode.

     Otherwise call a library function, memcmp.

 Don't allow operands to the compare to trap, as that can put the
 compare and branch in different basic blocks.

     Handle a libcall just for the mode we are using.

     If we want unsigned, and this mode has a distinct unsigned
     comparison routine, use that.

     There are two kinds of comparison routines. Biased routines
     return 0/1/2, and unbiased routines return -1/0/1. Other parts
     of gcc expect that the comparison operation is equivalent
     to the modified comparison. For signed comparisons compare the
     result against 1 in the biased case, and zero in the unbiased
     case. For unsigned comparisons always compare against 1 after
     biasing the unbiased result by adding 1. This gives us a way to
     represent LTU.
     The comparisons in the fixed-point helper library are always
     biased.

static void prepare_float_lib_cmp	(	rtx	x,
		rtx	y,
		enum rtx_code	comparison,
		rtx *	ptest,
		enum machine_mode *	pmode
	)

static

Emit a library call comparison between floating point X and Y. COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).

Attach a REG_EQUAL note describing the semantics of the libcall to the RTL. The allows the RTL optimizers to delete the libcall if the condition can be determined at compile-time.

rtx prepare_operand	(	enum insn_code	icode,
		rtx	x,
		int	opnum,
		enum machine_mode	mode,
		enum machine_mode	wider_mode,
		int	unsignedp
	)

Before emitting an insn with code ICODE, make sure that X, which is going to be used for operand OPNUM of the insn, is converted from mode MODE to WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and that it is accepted by the operand predicate. Return the new value.

void set_conv_libfunc	(	convert_optab	optab,
		enum machine_mode	tmode,
		enum machine_mode	fmode,
		const char *	name
	)

Call this to reset the function entry for one conversion optab (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be either 0 or a string constant.

void set_optab_libfunc ( )

Call this to reset the function entry for one optab (OPTABLE) in mode MODE to NAME, which should be either 0 or a string constant.

Referenced by gen_fractuns_conv_libfunc().

rtx set_user_assembler_libfunc ( )

Adjust the assembler name of libfunc NAME to ASMSPEC.

static bool shift_optab_p ( )

static

Return true if BINOPTAB implements a shift operation.

References commutative_optab_p(), find_widening_optab_handler, GET_MODE, insn_data, swap(), and widened_mode().

rtx sign_expand_binop	(	enum machine_mode	mode,
		optab	uoptab,
		optab	soptab,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	unsignedp,
		enum optab_methods	methods
	)

Expand a binary operator which has both signed and unsigned forms. UOPTAB is the optab for unsigned operations, and SOPTAB is for signed operations.

If we widen unsigned operands, we may use a signed wider operation instead of an unsigned wider operation, since the result would be the same.

 Do it without widening, if possible.

 Try widening to a signed int.  Disable any direct use of any
 signed insn in the current mode.

 For unsigned operands, try widening to an unsigned int.

 Use the right width libcall if that exists.

 Must widen and use a libcall, use either signed or unsigned.

 Undo the fiddling above.

rtx simplify_expand_binop	(	enum machine_mode	mode,
		optab	binoptab,
		rtx	op0,
		rtx	op1,
		rtx	target,
		int	unsignedp,
		enum optab_methods	methods
	)

Like expand_binop, but return a constant rtx if the result can be calculated at compile time. The arguments and return value are otherwise the same as for expand_binop.

Referenced by expand_doubleword_shift(), expand_subword_shift(), and expand_superword_shift().

bool supportable_convert_operation	(	enum tree_code	code,
		tree	vectype_out,
		tree	vectype_in,
		tree *	decl,
		enum tree_code *	code1
	)

Function supportable_convert_operation

Check whether an operation represented by the code CODE is a convert operation that is supported by the target platform in vector form (i.e., when operating on arguments of type VECTYPE_IN producing a result of type VECTYPE_OUT).

Convert operations we currently support directly are FIX_TRUNC and FLOAT. This function checks if these operations are supported by the target platform either directly (via vector tree-codes), or via target builtins.

Output:

CODE1 is code of vector operation to be used when vectorizing the operation, if available.
DECL is decl of target builtin functions to be used when vectorizing the operation, if available. In this case, CODE1 is CALL_EXPR.

First check if we can done conversion directly.

 Now check for builtin.

References can_fix_p(), convert_move(), convert_to_mode(), delete_insns_since(), expand_unop(), gen_reg_rtx(), get_last_insn(), and maybe_emit_unop_insn().

static bool swap_commutative_operands_with_target ( )

static

Return whether OP0 and OP1 should be swapped when expanding a commutative binop. Order them according to commutative_operand_precedence and, if possible, try to put TARGET or a pseudo first.

With equal precedence, both orders are ok, but it is better if the first operand is TARGET, or if both TARGET and OP0 are pseudos.

References CONST_INT_P, convert_modes(), force_reg(), GEN_INT, HOST_WIDE_INT, INTVAL, and trunc_int_for_mode().

bool valid_multiword_target_p ( )

TARGET is a target of a multiword operation that we are going to implement as a series of word-mode operations. Return true if TARGET is suitable for this purpose.

Referenced by expand_abs().

static rtx vector_compare_rtx	(	enum tree_code	tcode,
		tree	t_op0,
		tree	t_op1,
		bool	unsignedp,
		enum insn_code	icode
	)

static

Return comparison rtx for COND. Use UNSIGNEDP to select signed or unsigned operators. Do not generate compare instruction.

Expand operands.

static rtx widen_bswap ( )

static

Try calculating (bswap:narrow x) as (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))).

static rtx widen_leading ( )

static

Try calculating (clz:narrow x) as (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).

A similar operation can be used for clrsb. UNOPTAB says which operation we are trying to expand.

Referenced by expand_absneg_bit().

static rtx widen_operand	(	rtx	op,
		enum machine_mode	mode,
		enum machine_mode	oldmode,
		int	unsignedp,
		int	no_extend
	)

static

Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need not actually do a sign-extend or zero-extend, but can leave the higher-order bits of the result rtx undefined, for example, in the case of logical operations, but not right shifts.

 If we don't have to extend and this is a constant, return it.

 If we must extend do so.  If OP is a SUBREG for a promoted object, also
 extend since it will be more efficient to do so unless the signedness of
 a promoted object differs from our extension.

 If MODE is no wider than a single word, we return a lowpart or paradoxical
 SUBREG.

 Otherwise, get an object of MODE, clobber it, and set the low-order
 part to OP.

Referenced by expand_doubleword_clz().

static enum machine_mode widened_mode ( )

static

Given two input operands, OP0 and OP1, determine what the correct from_mode for a widening operation would be. In most cases this would be OP0, but if that's a constant it'll be VOIDmode, which isn't useful.

Referenced by shift_optab_p().

Variable Documentation

struct target_libfuncs default_target_libfuncs

struct target_optabs default_target_optabs

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.

GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see http://www.gnu.org/licenses/. Include insn-config.h before expr.h so that HAVE_conditional_move is properly defined.

htab_t libfunc_decls

static

A table of previously-created libfuncs, hashed by name.

struct target_optabs* this_fn_optabs = &default_target_optabs

Referenced by blocks_nreverse_all().

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation