- Generated by
1.8.1.1
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GCC Middle and Back End API Reference
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Data Structures | |
| struct | equivalence |
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In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the equivalent replacement.
References bitmap_bit_p(), simplify_replace_fn_rtx(), and equivalence::src_p.
Referenced by update_equiv_regs().
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If the backend knows where to allocate pseudos for hard register initial values, register these allocations now.
References df_get_live_in(), df_get_live_out(), initial_value_entry(), REG_N_SETS(), reg_renumber, and targetm.
Referenced by ira().
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Walk the insns of the current function and build reload_insn_chain, and record register life information.
References bitmap_and_compl_into(), bitmap_bit_p(), bitmap_clear(), bitmap_clear_bit(), bitmap_copy(), bitmap_empty_p(), bitmap_set_bit(), insn_chain::block, insn_chain::dead_or_set, df_get_live_out(), DF_REF_CONDITIONAL, DF_REF_MAY_CLOBBER, DF_REF_PARTIAL, DF_REF_READ_WRITE, DF_REF_SIGN_EXTRACT, DF_REF_STRICT_LOW_PART, DF_REF_SUBREG, DF_REF_ZERO_EXTRACT, dump_file, eliminable_regset, free(), basic_block_def::index, init_live_subregs(), insn_chain::insn, ira_conflicts_p, last, insn_chain::live_throughout, max_regno, new_insn_chain(), insn_chain::next, insn_chain::prev, print_insn_chains(), pseudo_for_reload_consideration_p(), reg_renumber, reload_insn_chain, and sbitmap_free().
Referenced by do_reload().
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Evaluate overall allocation cost and the costs for using hard registers and memory for allocnos.
References internal_flag_ira_verbose, ira_additional_jumps_num, ira_dump_file, ira_hard_reg_in_set_p(), ira_load_cost, ira_mem_cost, ira_move_loops_num, ira_overall_cost, ira_reg_cost, ira_shuffle_cost, and ira_store_cost.
Referenced by ira().
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Check the correctness of the allocation. We do need this because of complicated code to transform more one region internal representation into one region representation.
Referenced by ira().
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Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers spanning from one register pressure class to another one. It is called after defining the pressure classes.
References add_to_hard_reg_set().
Referenced by ira_init().
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The function used to sort the important classes.
References allocno_class_order.
Referenced by reorder_important_classes().
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Add register clobbers from asm statements.
References add_to_hard_reg_set(), and insn_contains_asm().
Referenced by ira_setup_eliminable_regset().
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TRUE if X uses any registers for which reg_equiv[REGNO].replace is true.
References equivalence::replace.
Referenced by update_equiv_regs().
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References bitmap_obstack_release(), build_insn_chain(), CDI_DOMINATORS, cleanup_cfg(), df_analyze(), df_finish_pass(), df_live_add_problem(), df_live_set_all_dirty(), DF_NO_INSN_RESCAN, df_scan_alloc(), df_scan_blocks(), df_set_flags(), dump_file, finish_reg_equiv(), free_dominance_info(), get_insns(), internal_flag_ira_verbose, ira_bitmap_obstack, ira_conflicts_p, ira_destroy(), ira_dump_file, ira_finish_assign(), ira_free(), ira_obstack, ira_overall_cost, ira_use_lra_p, basic_block_def::loop_father, loop_optimizer_finalize(), lra(), need_dce, overall_cost_before, reg_equivs, regstat_free_n_sets_and_refs(), regstat_free_ri(), reload(), run_fast_dce(), saved_flag_ira_share_spill_slots, timevar_pop(), timevar_push(), and vec_free().
Referenced by rest_of_handle_reload().
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Returns nonzero if X (used to initialize register REGNO) is movable. X is only movable if the registers it uses have equivalent initializations which appear to be within the same loop (or in an inner loop) and movable or if they are not candidates for local_alloc and don't vary.
References loop_depth(), equivalence::replace, rtx_varies_p(), and SET.
Referenced by update_equiv_regs().
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Returns zero if X is known to be invariant.
References equivalence::replace, and rtx_varies_p().
Referenced by update_equiv_regs().
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Regional allocation can create new pseudo-registers. This function expands some arrays for pseudo-registers.
References allocated_reg_info_size, max_reg_num(), resize_reg_info(), setup_preferred_alternate_classes_for_new_pseudos(), and setup_reg_classes().
Referenced by find_moveable_pseudos(), and ira().
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Look for instances where we have an instruction that is known to increase register pressure, and whose result is not used immediately. If it is possible to move the instruction downwards to just before its first use, split its lifetime into two ranges. We create a new pseudo to compute the value, and emit a move instruction just before the first use. If, after register allocation, the new pseudo remains unallocated, the function move_unallocated_pseudos then deletes the move instruction and places the computation just before the first use. Such a move is safe and profitable if all the input registers remain live and unchanged between the original computation and its first use. In such a situation, the computation is known to increase register pressure, and moving it is known to at least not worsen it. We restrict moves to only those cases where a register remains unallocated, in order to avoid interfering too much with the instruction schedule. As an exception, we may move insns which only modify their input register (typically induction variables), as this increases the freedom for our intended transformation, and does not limit the second instruction scheduler pass.
References bitmap_and_into(), bitmap_bit_p(), bitmap_clear(), bitmap_clear_bit(), bitmap_copy(), bitmap_set_bit(), calculate_dominance_info(), cc0_rtx, CDI_DOMINATORS, control_flow_insn_p(), dbg_cnt(), df_analyze(), df_get_live_in(), df_get_live_out(), dump_file, emit_insn_after(), emit_insn_before(), expand_reg_info(), first_moveable_pseudo, fix_reg_equiv_init(), free(), free_dominance_info(), gen_move_insn(), get_max_uid(), basic_block_def::index, insn_chain::insn, insn_dominated_by_p(), ira_create_new_reg(), last_moveable_pseudo, live, max_reg_num(), max_uid, modified_between_p(), modified_in_p(), next_nonnote_nondebug_insn(), OP_IN, reg_referenced_p(), regstat_compute_ri(), regstat_free_n_sets_and_refs(), regstat_free_ri(), regstat_init_n_sets_and_refs(), rtx_moveable_p(), set_insn_deleted(), sets_cc0_p(), transp, and validate_change().
Referenced by ira().
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Set up different arrays concerning class subsets, allocno and important classes.
References reorder_important_classes(), setup_allocno_and_important_classes(), setup_class_translate(), and setup_reg_class_relations().
Referenced by ira_init().
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References free().
Referenced by do_reload().
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Fix values of array REG_EQUIV_INIT after live range splitting done by IRA.
References grow_reg_equivs(), max_reg_num(), max_regno, max_regno_before_ira, reg_equivs, and vec_safe_length().
Referenced by find_moveable_pseudos(), and ira().
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Free ira_max_register_move_cost, ira_may_move_in_cost and ira_may_move_out_cost for each mode.
References free(), and memset().
Referenced by ira_finish_once(), and ira_init().
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Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using REG to the number of nregs, and INIT_VALUE to get the initialization. ALLOCNUM need not be the regno of REG.
References bitmap_bit_p(), bitmap_clear(), bitmap_ones(), bitmap_set_bit(), regno_reg_rtx, and sbitmap_alloc().
Referenced by build_insn_chain().
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References ira_expand_reg_equiv(), and ira_reg_equiv_len.
Referenced by ira().
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Return TRUE if INSN contains an ASM.
References for_each_rtx(), and insn_contains_asm_1().
Referenced by compute_regs_asm_clobbered().
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Return TRUE if *LOC contains an asm.
Referenced by insn_contains_asm().
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A wrapper around dominated_by_p, which uses the information in UID_LUID to give dominance relationships between two insns I1 and I2.
References CDI_DOMINATORS, and dominated_by_p().
Referenced by find_moveable_pseudos().
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This is the main entry of IRA.
References allocate_initial_values(), allocated_reg_info_size, bitmap_obstack_initialize(), calculate_allocation_cost(), function::calls_setjmp, CDI_DOMINATORS, cfun, df_d::changeable_flags, check_allocation(), delete_trivially_dead_insns(), delete_unreachable_blocks(), df, df_analyze(), df_clear_flags(), DF_NO_INSN_RESCAN, df_note_add_problem(), df_remove_problem(), DF_VERIFY_SCHEDULED, expand_reg_info(), find_moveable_pseudos(), fix_reg_equiv_init(), free_dominance_info(), generate_setjmp_warnings(), get_insns(), grow_reg_equivs(), init_caller_save(), init_reg_equiv(), internal_flag_ira_verbose, ira_additional_jumps_num, ira_allocate(), ira_bitmap_obstack, ira_build(), ira_color(), ira_conflicts_p, ira_dump_file, ira_emit(), ira_finish_emit_data(), ira_flattening(), ira_initiate_assign(), ira_initiate_emit_data(), ira_load_cost, ira_max_point, ira_mem_cost, ira_move_loops_num, ira_obstack, ira_overall_cost, ira_reassign_conflict_allocnos(), ira_reg_cost, IRA_REGION_ALL, IRA_REGION_MIXED, IRA_REGION_ONE, ira_set_pseudo_classes(), ira_setup_eliminable_regset(), ira_shuffle_cost, ira_spilled_reg_stack_slots_num, ira_store_cost, ira_use_lra_p, leaf_function_p(), loop_optimizer_finalize(), loop_optimizer_init(), LOOPS_HAVE_RECORDED_EXITS, lra_simple_p, max_reg_num(), max_regno, max_regno_before_ira, memset(), move_unallocated_pseudos(), overall_cost_before, print_redundant_copies(), purge_all_dead_edges(), rebuild_jump_labels(), regstat_compute_ri(), regstat_free_n_sets_and_refs(), regstat_free_ri(), regstat_init_n_sets_and_refs(), resize_reg_info(), saved_flag_ira_share_spill_slots, setup_allocno_assignment_flags(), setup_prohibited_mode_move_regs(), setup_reg_equiv(), setup_reg_equiv_init(), setup_reg_renumber(), targetm, timevar_pop(), timevar_push(), too_high_register_pressure_p(), and update_equiv_regs().
Referenced by rest_of_handle_ira().
| void* ira_allocate | ( | ) |
Allocate memory of size LEN for IRA data.
References ira_obstack.
| bitmap ira_allocate_bitmap | ( | void | ) |
Allocate and returns bitmap for IRA.
References ira_bitmap_obstack.
Referenced by add_ranges_and_copies(), do_coloring(), init_loop_tree_node(), ira_emit(), ira_initiate_assign(), ira_reassign_conflict_allocnos(), and ira_sort_regnos_for_alter_reg().
| bool ira_bad_reload_regno | ( | ) |
Return nonzero if REGNO is a particularly bad choice for reloading IN or OUT.
References ira_bad_reload_regno_1().
Referenced by allocate_reload_reg().
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Return nonzero if REGNO is a particularly bad choice for reloading X.
References ira_regno_allocno_map, pref, and reg_preferred_class().
Referenced by ira_bad_reload_regno().
| void ira_debug_allocno_classes | ( | void | ) |
Output all possible allocno and translation classes and the translation maps into stderr.
References print_translated_classes(), and print_unform_and_important_classes().
| void ira_debug_disposition | ( | void | ) |
Outputs information about allocation of all allocnos into stderr.
References ira_print_disposition().
| void ira_expand_reg_equiv | ( | void | ) |
Expand ira_reg_equiv if necessary.
References ira_reg_equiv_len, max_reg_num(), and memset().
Referenced by expand_reg_data(), init_reg_equiv(), and ira_create_new_reg().
| void ira_finish_once | ( | void | ) |
Function called once at the end of compiler work.
References free_register_move_costs(), ira_finish_costs_once(), and lra_finish_once().
Referenced by finalize().
| void ira_free | ( | ) |
Free memory ADDR allocated for IRA data.
References free().
| void ira_free_bitmap | ( | ) |
Free bitmap B allocated for IRA.
| void ira_init | ( | void | ) |
This is called every time when register related information is changed.
References clarify_prohibited_class_mode_regs(), find_reg_classes(), free_register_move_costs(), ira_init_costs(), lra_init(), setup_alloc_regs(), setup_class_subset_and_memory_move_costs(), setup_hard_regno_aclass(), setup_prohibited_class_mode_regs(), setup_reg_class_nregs(), and setup_reg_mode_hard_regset().
Referenced by lang_dependent_init_target(), and reinit_regs().
| void ira_init_once | ( | void | ) |
This is called once during compiler work. It sets up different arrays whose values don't depend on the compiled function.
References ira_init_costs_once(), and lra_init_once().
Referenced by backend_init().
| void ira_init_register_move_cost | ( | ) |
Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST and IRA_MAY_MOVE_OUT_COST for MODE.
References register_move_cost().
| void ira_print_disposition | ( | ) |
Output information about allocation of all allocnos (except for caps) into file F.
References basic_block_def::index, ira_regno_allocno_map, max_reg_num(), and max_regno.
| void ira_setup_eliminable_regset | ( | ) |
Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. If the function is called from IRA (not from the insn scheduler or RTL loop invariant motion), FROM_IRA_P is true.
References function::calls_alloca, cfun, compute_regs_asm_clobbered(), df_set_regs_ever_live(), eliminable_regset, error(), ira_use_lra_p, lra_init_elimination(), and targetm.
Referenced by calculate_bb_reg_pressure(), calculate_loop_reg_pressure(), ira(), and sched_init().
| void ira_update_equiv_info_by_shuffle_insn | ( | ) |
Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS are insns which were generated for such movement. It is assumed that FROM_REGNO and TO_REGNO always have the same value at the point of any move containing such registers. This function is used to update equiv info for register shuffles on the region borders and for caller save/restore insns.
References ira_reg_equiv::constant, ira_reg_equiv::defined_p, dump_value_slim(), find_reg_note(), ira_reg_equiv::init_insns, internal_flag_ira_verbose, ira_reg_equiv::invariant, ira_dump_file, ira_reg_equiv::memory, rtx_equal_p(), and set_unique_reg_note().
Referenced by emit_move_list().
| rtl_opt_pass* make_pass_ira | ( | ) |
| rtl_opt_pass* make_pass_reload | ( | ) |
| void mark_elimination | ( | ) |
Indicate that hard register number FROM was eliminated and replaced with an offset from hard register number TO. The status of hard registers live at the start of a basic block is updated by replacing a use of FROM with a use of TO.
References bitmap_bit_p(), bitmap_clear_bit(), and bitmap_set_bit().
Referenced by reload().
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TRUE if X references a memory location that would be affected by a store to MEMREF.
References SET, and true_dependence().
Referenced by memref_used_between_p().
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TRUE if some insn in the range (START, END] references a memory location that would be affected by a store to MEMREF.
References memref_referenced_p().
Referenced by update_equiv_regs().
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Perform the second half of the transformation started in find_moveable_pseudos. We look for instances where the newly introduced pseudo remains unallocated, and remove it by moving the definition to just before its use, replacing the move instruction generated by find_moveable_pseudos.
References delete_insn(), dump_file, emit_insn_after(), first_moveable_pseudo, last_moveable_pseudo, move_insn(), reg_renumber, and validate_change().
Referenced by ira().
Mark REG as having no known equivalence. Some instructions might have been processed before and furnished with REG_EQUIV notes for this register; these notes will have to be removed. STORE is the piece of RTL that does the non-constant / conflicting assignment - a SET, CLOBBER or REG_INC note. It is currently not used, but needs to be there because this function is called from note_stores.
References ira_reg_equiv::defined_p, find_reg_note(), ira_reg_equiv::init_insns, equivalence::init_insns, equivalence::is_arg_equivalence, remove_note(), and equivalence::replacement.
Referenced by update_equiv_regs().
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Print chain C to FILE.
References bitmap_print(), insn_chain::dead_or_set, insn_chain::insn, and insn_chain::live_throughout.
Referenced by print_insn_chains().
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Print all reload_insn_chains to FILE.
References insn_chain::next, print_insn_chain(), and reload_insn_chain.
Referenced by build_insn_chain().
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Print redundant memory-memory copies.
References ira_allocno_copy::first, ira_allocno_copy::freq, ira_allocno_copy::insn, internal_flag_ira_verbose, ira_dump_file, ira_allocno_copy::next_first_allocno_copy, and ira_allocno_copy::next_second_allocno_copy.
Referenced by ira().
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Output all possible allocno or pressure classes and their translation map into file F.
References reg_class_names.
Referenced by ira_debug_allocno_classes().
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Output all unifrom and important classes into file F.
References reg_class_names.
Referenced by ira_debug_allocno_classes().
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Return true if pseudo REGNO should be added to set live_throughout or dead_or_set of the insn chains for reload consideration.
References ira_conflicts_p, and reg_renumber.
Referenced by build_insn_chain().
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For correct work of function setup_reg_class_relation we need to reorder important classes according to the order of their allocno classes. It places important classes containing the same allocatable hard register set adjacent to each other and allocno class with the allocatable hard register set right after the other important classes with the same set. In example from comments of function setup_allocno_and_important_classes, it places LEGACY_REGS and GENERAL_REGS close to each other and GENERAL_REGS is after LEGACY_REGS.
References allocno_class_order, and comp_reg_classes_func().
Referenced by find_reg_classes().
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References do_reload().
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Examine the rtx found in *LOC, which is read or written to as determined by TYPE. Return false if we find a reason why an insn containing this rtx should not be moved (such as accesses to non-constant memory), true otherwise.
References OP_IN, OP_OUT, and SET.
Referenced by find_moveable_pseudos().
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Check whether the SUBREG is a paradoxical subreg and set the result in PDX_SUBREGS.
References paradoxical_subreg_p().
Referenced by update_equiv_regs().
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Set up global variables defining info about hard registers for the allocation. These depend on USE_HARD_FRAME_P whose TRUE value means that we can use the hard frame pointer for the allocation.
References setup_class_hard_regs().
Referenced by ira_init().
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Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. Target may have many subtargets and not all target hard regiters can be used for allocation, e.g. x86 port in 32-bit mode can not use hard registers introduced in x86-64 like r8-r15). Some classes might have the same allocatable hard registers, e.g. INDEX_REGS and GENERAL_REGS in x86 port in 32-bit mode. To decrease different calculations efforts we introduce allocno classes which contain unique non-empty sets of allocatable hard-registers. Pseudo class cost calculation in ira-costs.c is very expensive. Therefore we are trying to decrease number of classes involved in such calculation. Register classes used in the cost calculation are called important classes. They are allocno classes and other non-empty classes whose allocatable hard register sets are inside of an allocno class hard register set. From the first sight, it looks like that they are just allocno classes. It is not true. In example of x86-port in 32-bit mode, allocno classes will contain GENERAL_REGS but not LEGACY_REGS (because allocatable hard registers are the same for the both classes). The important classes will contain GENERAL_REGS and LEGACY_REGS. It is done because a machine description insn constraint may refers for LEGACY_REGS and code in ira-costs.c is mostly base on investigation of the insn constraints.
References hard_reg_set_equal_p(), hard_reg_set_subset_p(), setup_pressure_classes(), setup_uniform_class_p(), and temp_hard_regset.
Referenced by find_reg_classes().
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Set up allocno assignment flags for further allocation improvements.
References ira_free_allocno_updated_costs(), and ira_hard_reg_in_set_p().
Referenced by ira().
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The function sets up the three arrays declared above.
References temp_hard_regset.
Referenced by setup_alloc_regs().
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Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST.
References hard_reg_set_empty_p(), hard_reg_set_subset_p(), memory_move_cost(), setup_reg_subclasses(), and temp_hard_regset.
Referenced by ira_init().
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Set up array IRA_ALLOCNO_CLASS_TRANSLATE and IRA_PRESSURE_CLASS_TRANSLATE.
References setup_class_translate_array().
Referenced by find_reg_classes().
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Setup translation in CLASS_TRANSLATE of all classes into a class given by array CLASSES of length CLASSES_NUM. The function is used make translation any reg class to an allocno class or to an pressure class. This translation is necessary for some calculations when we can use only allocno or pressure classes and such translation represents an approximate representation of all classes. The translation in case when allocatable hard register set of a given class is subset of allocatable hard register set of a class in CLASSES is pretty simple. We use smallest classes from CLASSES containing a given class. If allocatable hard register set of a given class is not a subset of any corresponding set of a class from CLASSES, we use the cheapest (with load/store point of view) class from CLASSES whose set intersects with given class set
References hard_reg_set_empty_p(), and temp_hard_regset.
Referenced by setup_class_translate().
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Set up the array above.
Referenced by ira_init().
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Setup preferred and alternative classes for new pseudo-registers created by IRA starting with START.
References internal_flag_ira_verbose, ira_dump_file, max_reg_num(), max_regno, reg_allocno_class(), reg_alternate_class(), reg_class_names, reg_preferred_class(), regno_reg_rtx, and setup_reg_classes().
Referenced by expand_reg_info().
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Find pressure classes which are register classes for which we calculate register pressure in IRA, register pressure sensitive insn scheduling, and register pressure sensitive loop invariant motion. To make register pressure calculation easy, we always use non-intersected register pressure classes. A move of hard registers from one register pressure class is not more expensive than load and store of the hard registers. Most likely an allocno class will be a subset of a register pressure class and in many cases a register pressure class. That makes usage of register pressure classes a good approximation to find a high register pressure.
References hard_reg_set_empty_p(), hard_reg_set_equal_p(), hard_reg_set_subset_p(), ira_init_register_move_cost_if_necessary(), setup_stack_reg_pressure_class(), and temp_hard_regset.
Referenced by setup_allocno_and_important_classes().
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Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON. This function is called once IRA_CLASS_HARD_REGS has been initialized.
References count, in_hard_reg_set_p(), and temp_hard_regset.
Referenced by ira_init().
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Set up IRA_PROHIBITED_MODE_MOVE_REGS.
References constrain_operands(), extract_insn(), gen_rtx_REG(), move_insn(), and recog_memoized().
Referenced by ira().
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Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps.
References targetm.
Referenced by ira_init().
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Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, please see corresponding comments in ira-int.h.
References hard_reg_set_empty_p(), hard_reg_set_equal_p(), hard_reg_set_intersect_p(), hard_reg_set_subset_p(), memset(), reg_class_subset_p(), and temp_hard_regset.
Referenced by find_reg_classes().
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Set up fields memory, constant, and invariant from init_insns in the structures of array ira_reg_equiv.
References ira_reg_equiv::defined_p, find_reg_note(), force_const_mem(), function_invariant_p(), ira_reg_equiv::init_insns, equivalence::init_insns, ira_reg_equiv::invariant, ira_reg_equiv_len, ira_reg_equiv::memory, memory_operand(), rtx_equal_p(), and targetm.
Referenced by ira().
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Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should be already calculated.
References ira_reg_equiv::init_insns, max_reg_num(), and max_regno.
Referenced by ira().
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The function sets up the map IRA_REG_MODE_HARD_REGSET.
Referenced by ira_init().
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Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from the allocation found by IRA.
References caller_save_needed, ira_equiv_no_lvalue_p(), ira_free_allocno_updated_costs(), ira_hard_reg_set_intersection_p(), ira_reg_equiv_len, ira_use_lra_p, and reg_renumber.
Referenced by ira().
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Initialize the table of subclasses of each reg class.
References hard_reg_set_empty_p(), hard_reg_set_subset_p(), and temp_hard_regset.
Referenced by setup_class_subset_and_memory_move_costs().
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Set up ira_stack_reg_pressure_class which is the biggest pressure register class containing stack registers or NO_REGS if there are no stack registers. To find this class, we iterate through all register pressure classes and choose the first register pressure class containing all the stack registers and having the biggest size.
References hard_reg_set_size(), and temp_hard_regset.
Referenced by setup_pressure_classes().
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Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class whose register move cost between any registers of the class is the same as for all its subclasses. We use the data to speed up the 2nd pass of calculations of allocno costs.
References ira_init_register_move_cost_if_necessary().
Referenced by setup_allocno_and_important_classes().
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Return TRUE if there is too high register pressure in the function. It is used to decide when stack slot sharing is worth to do.
References ira_loop_tree_root, and ira_loop_tree_node::reg_pressure.
Referenced by ira().
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Find registers that are equivalent to a single value throughout the compilation (either because they can be referenced in memory or are set once from a single constant). Lower their priority for a register. If such a register is only referenced once, try substituting its value into the using insn. If it succeeds, we can eliminate the register completely. Initialize init_insns in ira_reg_equiv array. Return non-zero if jump label rebuilding should be done.
References adjust_cleared_regs(), asm_noperands(), bb_loop_depth(), bitmap_and_compl_into(), bitmap_empty_p(), bitmap_set_bit(), can_throw_internal(), contains_replace_regs(), copy_rtx(), delete_insn(), df_insn_rescan(), df_notes_rescan(), emit_insn_before(), end_alias_analysis(), equiv_init_movable_p(), equiv_init_varies_p(), find_reg_note(), for_each_rtx(), free(), get_insns(), grow_reg_equivs(), basic_block_def::index, init_alias_analysis(), ira_reg_equiv::init_insns, equivalence::init_insns, equivalence::is_arg_equivalence, loop_depth(), equivalence::loop_depth, max_regno, memref_used_between_p(), no_equiv(), note_stores(), prev_nondebug_insn(), recorded_label_ref, reg_mentioned_p(), REG_N_REFS(), reg_preferred_class(), regno_reg_rtx, remove_death(), remove_note(), equivalence::replace, equivalence::replacement, rtx_equal_p(), rtx_varies_p(), set_paradoxical_subreg(), set_unique_reg_note(), simplify_replace_fn_rtx(), equivalence::src_p, targetm, validate_equiv_mem(), and validate_replace_rtx().
Referenced by ira().
|
static |
Verify that no store between START and the death of REG invalidates MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, by storing into an overlapping memory location, or with a non-const CALL_INSN. Return 1 if MEMREF remains valid.
References equiv_mem, equiv_mem_modified, find_reg_note(), note_stores(), reg_overlap_mentioned_p(), side_effects_p(), and validate_equiv_mem_from_store().
Referenced by update_equiv_regs().
If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. Called via note_stores.
References anti_dependence(), equiv_mem, equiv_mem_modified, and reg_overlap_mentioned_p().
Referenced by validate_equiv_mem().
|
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The number of entries allocated in teg_info.
Referenced by expand_reg_info(), and ira().
|
static |
Order numbers of allocno classes in original target allocno class array, -1 for non-allocno classes.
Referenced by comp_reg_classes_func(), and reorder_important_classes().
| struct target_ira default_target_ira |
@verbatim Integrated Register Allocator (IRA) entry point.
Copyright (C) 2006-2013 Free Software Foundation, Inc. Contributed by Vladimir Makarov vmakarov@redhat.com.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see http://www.gnu.org/licenses/.
The integrated register allocator (IRA) is a
regional register allocator performing graph coloring on a top-down
traversal of nested regions. Graph coloring in a region is based
on Chaitin-Briggs algorithm. It is called integrated because
register coalescing, register live range splitting, and choosing a
better hard register are done on-the-fly during coloring. Register
coalescing and choosing a cheaper hard register is done by hard
register preferencing during hard register assigning. The live
range splitting is a byproduct of the regional register allocation.
Major IRA notions are:
o *Region* is a part of CFG where graph coloring based on
Chaitin-Briggs algorithm is done. IRA can work on any set of
nested CFG regions forming a tree. Currently the regions are
the entire function for the root region and natural loops for
the other regions. Therefore data structure representing a
region is called loop_tree_node.
o *Allocno class* is a register class used for allocation of
given allocno. It means that only hard register of given
register class can be assigned to given allocno. In reality,
even smaller subset of (*profitable*) hard registers can be
assigned. In rare cases, the subset can be even smaller
because our modification of Chaitin-Briggs algorithm requires
that sets of hard registers can be assigned to allocnos forms a
forest, i.e. the sets can be ordered in a way where any
previous set is not intersected with given set or is a superset
of given set.
o *Pressure class* is a register class belonging to a set of
register classes containing all of the hard-registers available
for register allocation. The set of all pressure classes for a
target is defined in the corresponding machine-description file
according some criteria. Register pressure is calculated only
for pressure classes and it affects some IRA decisions as
forming allocation regions.
o *Allocno* represents the live range of a pseudo-register in a
region. Besides the obvious attributes like the corresponding
pseudo-register number, allocno class, conflicting allocnos and
conflicting hard-registers, there are a few allocno attributes
which are important for understanding the allocation algorithm:
- *Live ranges*. This is a list of ranges of *program points*
where the allocno lives. Program points represent places
where a pseudo can be born or become dead (there are
approximately two times more program points than the insns)
and they are represented by integers starting with 0. The
live ranges are used to find conflicts between allocnos.
They also play very important role for the transformation of
the IRA internal representation of several regions into a one
region representation. The later is used during the reload
pass work because each allocno represents all of the
corresponding pseudo-registers.
- *Hard-register costs*. This is a vector of size equal to the
number of available hard-registers of the allocno class. The
cost of a callee-clobbered hard-register for an allocno is
increased by the cost of save/restore code around the calls
through the given allocno's life. If the allocno is a move
instruction operand and another operand is a hard-register of
the allocno class, the cost of the hard-register is decreased
by the move cost.
When an allocno is assigned, the hard-register with minimal
full cost is used. Initially, a hard-register's full cost is
the corresponding value from the hard-register's cost vector.
If the allocno is connected by a *copy* (see below) to
another allocno which has just received a hard-register, the
cost of the hard-register is decreased. Before choosing a
hard-register for an allocno, the allocno's current costs of
the hard-registers are modified by the conflict hard-register
costs of all of the conflicting allocnos which are not
assigned yet.
- *Conflict hard-register costs*. This is a vector of the same
size as the hard-register costs vector. To permit an
unassigned allocno to get a better hard-register, IRA uses
this vector to calculate the final full cost of the
available hard-registers. Conflict hard-register costs of an
unassigned allocno are also changed with a change of the
hard-register cost of the allocno when a copy involving the
allocno is processed as described above. This is done to
show other unassigned allocnos that a given allocno prefers
some hard-registers in order to remove the move instruction
corresponding to the copy.
o *Cap*. If a pseudo-register does not live in a region but
lives in a nested region, IRA creates a special allocno called
a cap in the outer region. A region cap is also created for a
subregion cap.
o *Copy*. Allocnos can be connected by copies. Copies are used
to modify hard-register costs for allocnos during coloring.
Such modifications reflects a preference to use the same
hard-register for the allocnos connected by copies. Usually
copies are created for move insns (in this case it results in
register coalescing). But IRA also creates copies for operands
of an insn which should be assigned to the same hard-register
due to constraints in the machine description (it usually
results in removing a move generated in reload to satisfy
the constraints) and copies referring to the allocno which is
the output operand of an instruction and the allocno which is
an input operand dying in the instruction (creation of such
copies results in less register shuffling). IRA *does not*
create copies between the same register allocnos from different
regions because we use another technique for propagating
hard-register preference on the borders of regions.
Allocnos (including caps) for the upper region in the region tree
*accumulate* information important for coloring from allocnos with
the same pseudo-register from nested regions. This includes
hard-register and memory costs, conflicts with hard-registers,
allocno conflicts, allocno copies and more. *Thus, attributes for
allocnos in a region have the same values as if the region had no
subregions*. It means that attributes for allocnos in the
outermost region corresponding to the function have the same values
as though the allocation used only one region which is the entire
function. It also means that we can look at IRA work as if the
first IRA did allocation for all function then it improved the
allocation for loops then their subloops and so on.
IRA major passes are:
o Building IRA internal representation which consists of the
following subpasses:
* First, IRA builds regions and creates allocnos (file
ira-build.c) and initializes most of their attributes.
* Then IRA finds an allocno class for each allocno and
calculates its initial (non-accumulated) cost of memory and
each hard-register of its allocno class (file ira-cost.c).
* IRA creates live ranges of each allocno, calulates register
pressure for each pressure class in each region, sets up
conflict hard registers for each allocno and info about calls
the allocno lives through (file ira-lives.c).
* IRA removes low register pressure loops from the regions
mostly to speed IRA up (file ira-build.c).
* IRA propagates accumulated allocno info from lower region
allocnos to corresponding upper region allocnos (file
ira-build.c).
* IRA creates all caps (file ira-build.c).
* Having live-ranges of allocnos and their classes, IRA creates
conflicting allocnos for each allocno. Conflicting allocnos
are stored as a bit vector or array of pointers to the
conflicting allocnos whatever is more profitable (file
ira-conflicts.c). At this point IRA creates allocno copies.
o Coloring. Now IRA has all necessary info to start graph coloring
process. It is done in each region on top-down traverse of the
region tree (file ira-color.c). There are following subpasses:
* Finding profitable hard registers of corresponding allocno
class for each allocno. For example, only callee-saved hard
registers are frequently profitable for allocnos living
through colors. If the profitable hard register set of
allocno does not form a tree based on subset relation, we use
some approximation to form the tree. This approximation is
used to figure out trivial colorability of allocnos. The
approximation is a pretty rare case.
* Putting allocnos onto the coloring stack. IRA uses Briggs
optimistic coloring which is a major improvement over
Chaitin's coloring. Therefore IRA does not spill allocnos at
this point. There is some freedom in the order of putting
allocnos on the stack which can affect the final result of
the allocation. IRA uses some heuristics to improve the
order.
We also use a modification of Chaitin-Briggs algorithm which
works for intersected register classes of allocnos. To
figure out trivial colorability of allocnos, the mentioned
above tree of hard register sets is used. To get an idea how
the algorithm works in i386 example, let us consider an
allocno to which any general hard register can be assigned.
If the allocno conflicts with eight allocnos to which only
EAX register can be assigned, given allocno is still
trivially colorable because all conflicting allocnos might be
assigned only to EAX and all other general hard registers are
still free.
To get an idea of the used trivial colorability criterion, it
is also useful to read article "Graph-Coloring Register
Allocation for Irregular Architectures" by Michael D. Smith
and Glen Holloway. Major difference between the article
approach and approach used in IRA is that Smith's approach
takes register classes only from machine description and IRA
calculate register classes from intermediate code too
(e.g. an explicit usage of hard registers in RTL code for
parameter passing can result in creation of additional
register classes which contain or exclude the hard
registers). That makes IRA approach useful for improving
coloring even for architectures with regular register files
and in fact some benchmarking shows the improvement for
regular class architectures is even bigger than for irregular
ones. Another difference is that Smith's approach chooses
intersection of classes of all insn operands in which a given
pseudo occurs. IRA can use bigger classes if it is still
more profitable than memory usage.
* Popping the allocnos from the stack and assigning them hard
registers. If IRA can not assign a hard register to an
allocno and the allocno is coalesced, IRA undoes the
coalescing and puts the uncoalesced allocnos onto the stack in
the hope that some such allocnos will get a hard register
separately. If IRA fails to assign hard register or memory
is more profitable for it, IRA spills the allocno. IRA
assigns the allocno the hard-register with minimal full
allocation cost which reflects the cost of usage of the
hard-register for the allocno and cost of usage of the
hard-register for allocnos conflicting with given allocno.
* Chaitin-Briggs coloring assigns as many pseudos as possible
to hard registers. After coloringh we try to improve
allocation with cost point of view. We improve the
allocation by spilling some allocnos and assigning the freed
hard registers to other allocnos if it decreases the overall
allocation cost.
* After allono assigning in the region, IRA modifies the hard
register and memory costs for the corresponding allocnos in
the subregions to reflect the cost of possible loads, stores,
or moves on the border of the region and its subregions.
When default regional allocation algorithm is used
(-fira-algorithm=mixed), IRA just propagates the assignment
for allocnos if the register pressure in the region for the
corresponding pressure class is less than number of available
hard registers for given pressure class.
o Spill/restore code moving. When IRA performs an allocation
by traversing regions in top-down order, it does not know what
happens below in the region tree. Therefore, sometimes IRA
misses opportunities to perform a better allocation. A simple
optimization tries to improve allocation in a region having
subregions and containing in another region. If the
corresponding allocnos in the subregion are spilled, it spills
the region allocno if it is profitable. The optimization
implements a simple iterative algorithm performing profitable
transformations while they are still possible. It is fast in
practice, so there is no real need for a better time complexity
algorithm.
o Code change. After coloring, two allocnos representing the
same pseudo-register outside and inside a region respectively
may be assigned to different locations (hard-registers or
memory). In this case IRA creates and uses a new
pseudo-register inside the region and adds code to move allocno
values on the region's borders. This is done during top-down
traversal of the regions (file ira-emit.c). In some
complicated cases IRA can create a new allocno to move allocno
values (e.g. when a swap of values stored in two hard-registers
is needed). At this stage, the new allocno is marked as
spilled. IRA still creates the pseudo-register and the moves
on the region borders even when both allocnos were assigned to
the same hard-register. If the reload pass spills a
pseudo-register for some reason, the effect will be smaller
because another allocno will still be in the hard-register. In
most cases, this is better then spilling both allocnos. If
reload does not change the allocation for the two
pseudo-registers, the trivial move will be removed by
post-reload optimizations. IRA does not generate moves for
allocnos assigned to the same hard register when the default
regional allocation algorithm is used and the register pressure
in the region for the corresponding pressure class is less than
number of available hard registers for given pressure class.
IRA also does some optimizations to remove redundant stores and
to reduce code duplication on the region borders.
o Flattening internal representation. After changing code, IRA
transforms its internal representation for several regions into
one region representation (file ira-build.c). This process is
called IR flattening. Such process is more complicated than IR
rebuilding would be, but is much faster.
o After IR flattening, IRA tries to assign hard registers to all
spilled allocnos. This is impelemented by a simple and fast
priority coloring algorithm (see function
ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
created during the code change pass can be assigned to hard
registers.
o At the end IRA calls the reload pass. The reload pass
communicates with IRA through several functions in file
ira-color.c to improve its decisions in
* sharing stack slots for the spilled pseudos based on IRA info
about pseudo-register conflicts.
* reassigning hard-registers to all spilled pseudos at the end
of each reload iteration.
* choosing a better hard-register to spill based on IRA info
about pseudo-register live ranges and the register pressure
in places where the pseudo-register lives.
IRA uses a lot of data representing the target processors. These
data are initilized in file ira.c.
If function has no loops (or the loops are ignored when
-fira-algorithm=CB is used), we have classic Chaitin-Briggs
coloring (only instead of separate pass of coalescing, we use hard
register preferencing). In such case, IRA works much faster
because many things are not made (like IR flattening, the
spill/restore optimization, and the code change).
Literature is worth to read for better understanding the code:
o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
Graph Coloring Register Allocation.
o David Callahan, Brian Koblenz. Register allocation via
hierarchical graph coloring.
o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
Coloring Register Allocation: A Study of the Chaitin-Briggs and
Callahan-Koblenz Algorithms.
o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
Register Allocation Based on Graph Fusion.
o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
Allocation for Irregular Architectures
o Vladimir Makarov. The Integrated Register Allocator for GCC.
o Vladimir Makarov. The top-down register allocator for irregular
register file architectures.
| struct target_ira_int default_target_ira_int |
| HARD_REG_SET eliminable_regset |
All registers that can be eliminated.
Referenced by add_regs_to_insn_regno_info(), build_insn_chain(), collect_non_operand_hard_regs(), get_regno_pressure_class(), inherit_in_ebb(), ira_setup_eliminable_regset(), mark_hard_reg_live(), need_for_split_p(), process_bb_lives(), process_bb_node_lives(), and update_reg_eliminate().
|
static |
Used for communication between the following two functions: contains a MEM that we wish to ensure remains unchanged.
Referenced by validate_equiv_mem(), and validate_equiv_mem_from_store().
|
static |
Set nonzero if EQUIV_MEM is modified.
Referenced by validate_equiv_mem(), and validate_equiv_mem_from_store().
| int first_moveable_pseudo |
Record the range of register numbers added by find_moveable_pseudos.
Referenced by find_costs_and_classes(), find_moveable_pseudos(), and move_unallocated_pseudos().
| int internal_flag_ira_verbose |
A modified value of flag `-fira-verbose' used internally.
Referenced by add_range_and_copies_from_move_list(), allocno_reload_assign(), assign_hard_reg(), build_conflict_bit_table(), calculate_allocation_cost(), change_loop(), coalesce_allocnos(), coalesce_spill_slots(), color_allocnos(), color_pass(), copy_allocno_live_ranges(), create_cap_allocno(), do_coloring(), do_reload(), fast_allocation(), find_costs_and_classes(), generate_edge_moves(), improve_allocation(), ira(), ira_build(), ira_build_conflicts(), ira_compress_allocno_live_ranges(), ira_create_allocno_live_ranges(), ira_create_new_reg(), ira_flattening(), ira_mark_new_stack_slot(), ira_reassign_conflict_allocnos(), ira_reassign_pseudos(), ira_rebuild_regno_allocno_list(), ira_reuse_stack_slot(), ira_set_pseudo_classes(), ira_sort_regnos_for_alter_reg(), ira_update_equiv_info_by_shuffle_insn(), mark_all_loops_for_removal(), mark_loops_for_removal(), modify_move_list(), move_allocno_live_ranges(), move_spill_restore(), pop_allocnos_from_stack(), print_redundant_copies(), process_bb_node_lives(), push_allocno_to_stack(), remove_allocno_from_bucket_and_push(), remove_some_program_points_and_update_live_ranges(), setup_allocno_available_regs_num(), and setup_preferred_alternate_classes_for_new_pseudos().
| int ira_additional_jumps_num |
Referenced by calculate_allocation_cost(), emit_moves(), and ira().
|
static |
Obstack used for storing all bitmaps of the IRA.
Referenced by do_reload(), ira(), and ira_allocate_bitmap().
| bool ira_conflicts_p |
True if we have allocno conflicts. It is false for non-optimized mode or when the conflict table is too big.
Referenced by alter_reg(), build_insn_chain(), calculate_needs_all_insns(), compute_use_by_pseudos(), count_pseudo(), count_spilled_pseudo(), delete_output_reload(), do_reload(), emit_input_reload_insns(), find_reg(), finish_spills(), ira(), ira_build(), ira_build_conflicts(), ira_color(), pseudo_for_reload_consideration_p(), and reload().
| FILE* ira_dump_file |
Dump file of the allocator if it is not NULL.
Referenced by add_range_and_copies_from_move_list(), allocno_reload_assign(), assign_hard_reg(), build_conflict_bit_table(), calculate_allocation_cost(), change_loop(), coalesce_allocnos(), coalesce_spill_slots(), color_allocnos(), color_pass(), copy_allocno_live_ranges(), create_cap_allocno(), do_coloring(), do_reload(), fast_allocation(), generate_edge_moves(), improve_allocation(), ira(), ira_build(), ira_build_conflicts(), ira_compress_allocno_live_ranges(), ira_costs(), ira_create_allocno_live_ranges(), ira_create_new_reg(), ira_flattening(), ira_mark_new_stack_slot(), ira_print_expanded_allocno(), ira_reassign_conflict_allocnos(), ira_reassign_pseudos(), ira_rebuild_regno_allocno_list(), ira_reuse_stack_slot(), ira_sort_regnos_for_alter_reg(), ira_update_equiv_info_by_shuffle_insn(), mark_all_loops_for_removal(), mark_loops_for_removal(), modify_move_list(), move_allocno_live_ranges(), move_spill_restore(), pop_allocnos_from_stack(), print_loop_title(), print_redundant_copies(), process_bb_node_lives(), push_allocno_to_stack(), remove_allocno_from_bucket_and_push(), remove_some_program_points_and_update_live_ranges(), setup_allocno_available_regs_num(), and setup_preferred_alternate_classes_for_new_pseudos().
| int ira_load_cost |
Referenced by calculate_allocation_cost(), emit_move_list(), and ira().
| int ira_mem_cost |
Referenced by calculate_allocation_cost(), and ira().
| int ira_move_loops_num |
Referenced by calculate_allocation_cost(), ira(), and modify_move_list().
|
static |
Obstack used for storing all dynamic data (except bitmaps) of the IRA.
Referenced by do_reload(), ira(), and ira_allocate().
| int ira_overall_cost |
Correspondingly overall cost of the allocation, overall cost before reload, cost of the allocnos assigned to hard-registers, cost of the allocnos assigned to memory, cost of loads, stores and register move insns generated for pseudo-register live range splitting (see ira-emit.c).
Referenced by allocno_reload_assign(), calculate_allocation_cost(), do_reload(), emit_move_list(), ira(), and ira_mark_allocation_change().
| int ira_reg_cost |
Referenced by calculate_allocation_cost(), and ira().
| struct ira_reg_equiv* ira_reg_equiv |
Info about equiv. info for each register.
| int ira_reg_equiv_len |
The length of the following array.
Referenced by change_loop(), color_pass(), emit_move_list(), init_reg_equiv(), ira_equiv_no_lvalue_p(), ira_expand_reg_equiv(), setup_reg_equiv(), and setup_reg_renumber().
| int ira_shuffle_cost |
Referenced by calculate_allocation_cost(), emit_move_list(), and ira().
| struct ira_spilled_reg_stack_slot* ira_spilled_reg_stack_slots |
The following array contains info about spilled pseudo-registers stack slots used in current function so far.
Referenced by ira_mark_new_stack_slot(), and ira_reuse_stack_slot().
| int ira_spilled_reg_stack_slots_num |
The number of elements in the following array.
Referenced by ira(), ira_mark_new_stack_slot(), ira_reuse_stack_slot(), and ira_sort_regnos_for_alter_reg().
| int ira_store_cost |
Referenced by calculate_allocation_cost(), emit_move_list(), and ira().
| bool ira_use_lra_p |
True when we use LRA instead of reload pass for the current function.
Referenced by based_loc_descr(), compute_frame_pointer_to_fb_displacement(), do_reload(), emit_move_list(), ira(), ira_setup_eliminable_regset(), and setup_reg_renumber().
| int last_moveable_pseudo |
Referenced by find_costs_and_classes(), find_moveable_pseudos(), and move_unallocated_pseudos().
|
static |
Value of max_reg_num () before IRA work start. This value helps us to recognize a situation when new pseudos were created during IRA work.
Referenced by fix_reg_equiv_init(), and ira().
| int overall_cost_before |
Referenced by do_reload(), and ira().
These two vectors hold data for every register added by find_movable_pseudos, with index 0 holding data for the first_moveable_pseudo.
The original home register.
|
static |
Nonzero if we recorded an equivalence for a LABEL_REF.
Referenced by update_equiv_regs().
|
static |
reg_equiv[N] (where N is a pseudo reg number) is the equivalence structure for that register.
| short* reg_renumber |
Vector of substitutions of register numbers, used to map pseudo regs into hardware regs. This is set up as a result of register allocation. Element N is the hard reg assigned to pseudo reg N, or is -1 if no hard reg was assigned. If N is a hard reg number, element N is N.
Referenced by add_used_regs_1(), allocate_initial_values(), allocate_reg_info(), allocno_reload_assign(), alter_reg(), assign_by_spills(), assign_mem_slot(), build_insn_chain(), calculate_elim_costs_all_insns(), calculate_needs_all_insns(), calculate_spill_cost(), check_and_process_move(), compute_use_by_pseudos(), constrain_operands(), count_pseudo(), count_spilled_pseudo(), create_live_range_start_chains(), cselib_invalidate_regno(), curr_insn_transform(), delete_output_reload(), eliminate_regs_1(), elimination_effects(), emit_input_reload_insns(), find_reloads(), find_reloads_address_1(), find_reloads_toplev(), finish_spills(), free_reg_info(), gimple_expand_cfg(), improve_inheritance(), inherit_in_ebb(), init_regno_assign_info(), ira_mark_allocation_change(), ira_reassign_pseudos(), lra_assign(), lra_create_live_ranges(), lra_get_regno_hard_regno(), lra_setup_reg_renumber(), lra_undo_inheritance(), mark_home_live(), mark_home_live_1(), mark_referenced_regs(), mem_move_p(), move_unallocated_pseudos(), need_for_call_save_p(), need_for_split_p(), prepare_function_start(), process_bb_lives(), pseudo_for_reload_consideration_p(), push_reload(), regno_ok_for_base_p(), reload(), resize_reg_info(), rtx_renumbered_equal_p(), save_call_clobbered_regs(), setup_live_pseudos_and_spill_after_risky_transforms(), setup_reg_renumber(), setup_save_areas(), spill_for(), spill_hard_reg(), spill_pseudos(), split_reg(), subst_indexed_address(), true_regnum(), undo_optional_reloads(), update_hard_regno_preference(), and update_lives().
|
static |
Saved between IRA and reload.
Referenced by do_reload(), and ira().
|
static |
Temporary hard reg set used for a different calculation.
Referenced by setup_allocno_and_important_classes(), setup_class_hard_regs(), setup_class_subset_and_memory_move_costs(), setup_class_translate_array(), setup_pressure_classes(), setup_prohibited_class_mode_regs(), setup_reg_class_relations(), setup_reg_subclasses(), and setup_stack_reg_pressure_class().
| struct target_ira* this_target_ira = &default_target_ira |
| struct target_ira_int* this_target_ira_int = &default_target_ira_int |
1.8.1.1