- Generated by
1.8.1.1
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GCC Middle and Back End API Reference
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Data Structures | |
| struct | rtx_search_arg |
| struct | hard_regs_data |
| struct | reg_rename |
| struct | cmpd_local_params |
| struct | moveop_static_params |
| struct | fur_static_params |
| struct | code_motion_path_driver_info_def |
Typedefs | |
| typedef struct rtx_search_arg * | rtx_search_arg_p |
| typedef struct fur_static_params * | fur_static_params_p |
| typedef struct cmpd_local_params * | cmpd_local_params_p |
| typedef struct moveop_static_params * | moveop_static_params_p |
| typedef vec< vinsn_t > | vinsn_vec_t |
Enumerations | |
| enum | MOVEUP_EXPR_CODE { MOVEUP_EXPR_SAME, MOVEUP_EXPR_AS_RHS, MOVEUP_EXPR_NULL, MOVEUP_EXPR_CHANGED } |
| typedef struct cmpd_local_params* cmpd_local_params_p |
| typedef struct fur_static_params* fur_static_params_p |
| typedef struct moveop_static_params* moveop_static_params_p |
| typedef struct rtx_search_arg* rtx_search_arg_p |
| typedef vec<vinsn_t> vinsn_vec_t |
A vector of vinsns is used to hold temporary lists of vinsns.
| enum MOVEUP_EXPR_CODE |
Definitions of local types and macros.
Represents possible outcomes of moving an expression through an insn.
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Functions that work with fences.
Advance one cycle on FENCE.
References move_fence_to_fences(), sched_verbose, and sel_print().
Referenced by compute_av_set_on_boundaries().
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Advance state on FENCE with INSN. Return true if INSN is an ASM, and we should advance state once more.
We should never issue more than issue_rate insns.
This could be an ASM insn which we'd like to schedule
on the next cycle.
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Return true if either of expressions from ORIG_OPS can be blocked by previously created bookkeeping code. STATIC_PARAMS points to static parameters of move_op.
This checks that expressions in ORIG_OPS are not blocked by bookkeeping
created while scheduling on another fence. Expressions can be also blocked by bookkeeping created during current
move_op. Expressions in ORIG_OPS may have wrong destination register due to
renaming. Check with the right register instead.
References ready_list::first, max_issue_size, ready_list::n_ready, ready, ready_try, sched_extend_ready_list(), and ready_list::vec.
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Return TRUE if BB can hold bookkeeping code.
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Calculate new fences from FENCES.
This fence doesn't have any successors.
Nothing was scheduled on this fence.
Referenced by sel_region_init().
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Calculate the number of privileged insns and return it.
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Return true if dependence described by DS can be overcomed.
Leave only speculative data.
FIXME: make sched-deps.c produce only those non-hard dependencies,
that we can overcome.
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Functions to support substitution.
Returns whether INSN with dependence status DS is eligible for substitution, i.e. it's a copy operation x := y, and RHS that is moved up through this insn should be substituted.
We can substitute only true dependencies.
Now we just need to make sure the INSN_RHS consists of only one
simple REG rtx.
References rtx_search_arg::n, and rtx_search_arg::x.
Referenced by create_speculation_check().
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Find the best insn for scheduling, either via max_issue or just take the most prioritized available.
TODO: pass equivalent of first_cycle_insn_p to max_issue ().
We can't use max_issue; just return the first available element.
References get_seqno_by_preds(), and pipelining_p.
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Choose the pseudo register for storing rhs value. As this is supposed to work before reload, we return either the original register or make the new one. The parameters are the same that in choose_nest_reg_1 functions, except that USED_REGS may contain pseudos. If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS. TODO: take into account register pressure while doing this. Up to this moment, this function would never return NULL for pseudos, but we should not rely on this.
We should not use this after reload.
If original register is available, return it.
Check that all original operations have the same mode.
For hard registers, we have to check hardware imposed
limitations (frame/stack registers, calls crossed). Don't let register cross a call if it doesn't already
cross one. This condition is written in accordance with
that in sched-deps.c sched_analyze_reg(). We had some original hard registers that couldn't be used.
Those were likely special. Don't try to create a pseudo. We haven't found a register from original operations. Get a new one.
FIXME: control register pressure somehow.
References expr_dest_regno(), replace_dest_with_reg_in_expr(), replace_dest_with_reg_ok_p(), and replace_src_with_reg_ok_p().
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A wrapper around choose_best_reg_1 () to verify that we make correct assumptions about available registers in the function.
FIXME loop over hard_regno_nregs here.
References av_set_clear(), av_set_is_in_p(), find_sequential_best_exprs(), and find_used_regs().
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Choose the register among free, that is suitable for storing
the rhs value.
ORIGINAL_INSNS is the list of insns where the operation (rhs)
originally appears. There could be multiple original operations
for single rhs since we moving it up and merging along different
paths.
Some code is adapted from regrename.c (regrename_optimize).
If original register is available, function returns it.
Otherwise it performs the checks, so the new register should
comply with the following:
- it should not violate any live ranges (such registers are in
REG_RENAME_P->available_for_renaming set);
- it should not be in the HARD_REGS_USED regset;
- it should be in the class compatible with original uses;
- it should not be clobbered through reference with different mode;
- if we're in the leaf function, then the new register should
not be in the LEAF_REGISTERS;
- etc.
If several registers meet the conditions, the register with smallest
tick is returned to achieve more even register allocation.
If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
If no register satisfies the above conditions, NULL_RTX is returned. If original register is available, return it.
Check that all original operations have the same mode.
This is done for the next loop; if we'd return from this
loop, we'd check only part of them, but in this case
it doesn't matter. All hard registers are available.
Hard registers should not be shared.
Among all available regs choose the register that was
allocated earliest. Check that all hard regs for mode are available.
All hard registers are available.
Return immediately when we know there's no better reg.
Use the check from the above loop.
References reg_rename::crosses_call, and gen_rtx_REG().
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The driver function that implements move_op or find_used_regs functionality dependent whether code_motion_path_driver_INFO is set to &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts of code (CFG traversal etc) that are shared among both functions. INSN is the insn we're starting the search from, ORIG_OPS are the expressions we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local parameters of the driver, and STATIC_PARAMS are static parameters of the caller. Returns whether original instructions were found. Note that top-level code_motion_path_driver always returns true.
If no original operations exist below this insn, return immediately.
The block can have invalid av set, in which case it was created earlier
during move_op. Return immediately. We have already found an original operation on this branch, do not
go any further and just return TRUE here. If we don't stop here,
function can have exponential behaviour even on the small code
with many different paths (e.g. with data speculation and
recovery blocks). Filter the orig_ops set.
If no more original ops, return immediately.
For non-speculative insns we have to leave only one form of the
original operation, because if we don't, we may end up with
different C_EXPRes and, consequently, with bookkeepings for different
expression forms along the same code motion path. That may lead to
generation of incorrect code. So for each code motion we stick to
the single form of the instruction, except for speculative insns
which we need to keep in different forms with all speculation
types. It is not possible that all ORIG_OPS are filtered out.
It is enough to place only heads and tails of visited basic blocks into
the PATH. Descend the basic block in search of the original expr; this part
corresponds to the part of the original move_op procedure executed
before the recursive call. Look at the insn and decide if it could be an ancestor of currently
scheduling operation. If it is so, then the insn "dest = op" could
either be replaced with "dest = reg", because REG now holds the result
of OP, or just removed, if we've scheduled the insn as a whole.
If this insn doesn't contain currently scheduling OP, then proceed
with searching and look at its successors. Operations we're searching
for could have changed when moving up through this insn via
substituting. In this case, perform unsubstitution on them first.
When traversing the DAG below this insn is finished, insert
bookkeeping code, if the insn is a joint point, and remove
leftovers. We have found the original operation.
Step back, so on the way back we'll start traversing from the
previous insn (or we'll see that it's bb_note and skip that
loop). We haven't found the original expr, continue descending the basic
block. Av set ops could have been changed when moving through this
insn. To find them below it, we have to un-substitute them. Clean up and return, if the hook tells us to do so. It may
happen if we've encountered the previously created
bookkeeping. Stop at insn if we got to the end of BB.
Here INSN either points to the insn before the original insn (may be
bb_note, if original insn was a bb_head) or to the bb_end. Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
it's already in PATH then). Process_successors should be able to find at least one
successor for which code_motion_path_driver returns TRUE. Jump in the end of basic block could have been removed or replaced
during code_motion_process_successors, so recompute insn as the
last insn in bb. Remove bb tail from path.
This is the case when one of the original expr is no longer available
due to bookkeeping created on this branch with the same register.
In the original algorithm, which doesn't have update_data_sets call
on a bookkeeping block, it would simply result in returning
FALSE when we've encountered a previously generated bookkeeping
insn in moveop_orig_expr_not_found. Don't need it any more.
Backward pass: now, when we have C_EXPR computed, we'll drag it to
the beginning of the basic block. Now we're at the bb head.
This should be the very last operation as at bb head we could change
the numbering by creating bookkeeping blocks.
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Perform a cleanup when the driver is about to terminate. ORIG_OPS_P is the pointer to the av set with expressions we were looking for, PATH_P is the pointer to the traversed path.
References bb_ends_ebb_p(), bb_next_bb(), bitmap_set_bit(), basic_block_def::index, sched_verbose, and sel_print().
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Traverse all successors of INSN. For each successor that is SUCCS_NORMAL code_motion_path_driver is called recursively. Original operation was found at least on one path that is starting with one of INSN's successors (this fact is asserted). ORIG_OPS is expressions we're looking for, PATH is the path we've traversed, STATIC_PARAMS is the parameters of either move_op or find_used_regs depending on the caller. Return 0 if we haven't found expression, 1 if we found it, -1 if we don't know for sure at this point.
We need to process only NORMAL succs for move_op, and collect live
registers from ALL branches (including those leading out of the
region) for find_used_regs.
In move_op, there can be a case when insn's bb number has changed
due to created bookkeeping. This happens very rare, as we need to
move expression from the beginning to the end of the same block.
Rescan successors in this case. Go deep into recursion only for NORMAL edges (non-backedges within the
current region). Merge c_expres found or unify live register sets from different
successors. We have simplified the control flow below this point. In this case,
the iterator becomes invalid. We need to try again.
If we have removed the insn itself, it could be only an
unconditional jump. Thus, do not rescan but break immediately --
we have already visited the only successor block. Here, RES==1 if original expr was found at least for one of the
successors. After the loop, RES may happen to have zero value
only if at some point the expr searched is present in av_set, but is
not found below. In most cases, this situation is an error.
The exception is when the original operation is blocked by
bookkeeping generated for another fence or for another path in current
move_op. Merge data, clean up, etc.
References bitmap_clear(), current_loop_nest, current_nr_blocks, current_region_empty_p(), first_emitted_uid, get_max_uid(), haifa_init_h_i_d(), init_deps_global(), memset(), preheader_removed, rgn_setup_region(), rgn_setup_sched_infos(), sched_deps_init(), sched_dump, sched_init_luids(), sched_verbose, sel_bb_head(), sel_compute_priorities(), sel_init_bbs(), sel_init_global_and_expr(), sel_is_loop_preheader_p(), sel_register_cfg_hooks(), sel_set_sched_flags(), sel_setup_region_sched_flags(), sel_setup_sched_infos(), setup_current_loop_nest(), setup_nop_vinsn(), targetm, and update_liveness_on_insn().
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Collect unavailable registers due to liveness for EXPR from BNDS into USED_REGS. Save additional information about available registers and unavailable due to hardware restriction registers into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS list.
If the chosen best expr doesn't belong to current boundary,
skip it. Put in ORIG_OPS all exprs from this boundary that became
RES on top. Compute used regs and OR it into the USED_REGS.
FIXME: the assert is true until we'd have several boundaries.
References spec_info_def::mask, and spec_info.
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Compute av set before INSN. INSN - the current operation (actual rtx INSN) P - the current path, which is list of insns visited so far WS - software lookahead window size. UNIQUE_P - TRUE, if returned av_set will be changed, hence if we want to save computed av_set in s_i_d, we should make a copy of it. In the resulting set we will have only expressions that don't have delay stalls and nonsubstitutable dependences.
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Computes the av_set below the last bb insn INSN, doing all the 'dirty work' of handling multiple successors and properly merging its av_sets. P is the current path traversed. WS is the size of lookahead window. Return the av set computed.
Find different kind of successors needed for correct computing of
SPEC and TARGET_AVAILABLE attributes. Debug output.
Add insn to the tail of current path.
We will edit SUCC_SET and EXPR_SPEC field of its elements.
Find EXPR'es that came from *all* successors and save them
into expr_in_all_succ_branches. This set will be used later
for calculating speculation attributes of EXPR'es. Remember the first successor for later.
Union the av_sets. Check liveness restrictions on target registers
in special case of two successors. Check liveness restrictions via hard way when there are more than
two successors. Finally, check liveness restrictions on paths leaving the region.
Increase the spec attribute of all EXPR'es that didn't come
from all successors. Do not move conditional branches through other
conditional branches. So, remove all conditional
branches from av_set if current operator is a conditional
branch.
References dump_av_set(), and sel_print().
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This function computes av_set for the FIRST_INSN by dragging valid av_set through all basic block insns either from the end of basic block (computed using compute_av_set_at_bb_end) or from the insn on which MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set below the basic block and handling conditional branches. FIRST_INSN - the basic block head, P - path consisting of the insns traversed on the way to the FIRST_INSN (the path is sparse, only bb heads and bb ends are added to the path), WS - current window size, NEED_COPY_P - true if we'll make a copy of av_set before returning it.
Return NULL if insn is not on the legitimate downward path.
If insn already has valid av(insn) computed, just return it.
As the result after this loop have completed, in LAST_INSN we'll
have the insn which has valid av_set to start backward computation
from: it either will be NULL because on it the window size was exceeded
or other valid av_set as returned by compute_av_set for the last insn
of the basic block. We may encounter valid av_set not only on bb_head, but also on
those insns on which previously MAX_WS was exceeded. The special case: the last insn of the BB may be an
ineligible_successor due to its SEQ_NO that was set on
it as a bookkeeping. We can reach max lookahead size at bb_header, so clean av_set
first. Get the valid av_set into AV above the LAST_INSN to start backward
computation from. It either will be empty av_set or av_set computed from
the successors on the last insn of the current bb. This is needed only to obtain av_sets that are identical to
those computed by the old compute_av_set version. END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END.
Compute av_set in AV starting from below the LAST_INSN up to
location above the FIRST_INSN. If the expression for CUR_INSN is already in the set,
replace it by the new one. Clear stale bb_av_set.
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Compute available instructions on BNDS. FENCE is the current fence. Write the computed set to *AV_VLIW_P.
Rewind BND->TO to the basic block header in case some bookkeeping
instructions were inserted before BND->TO and it needs to be
adjusted.
References advance_one_cycle(), and issue_rate.
| regset compute_live | ( | ) |
Compute the set of all live registers at the point before INSN and save it at INSN if INSN is bb header.
Return the valid set if we're already on it.
We've skipped the wrong lv_set. Don't skip the right one.
Find a valid LV set in this block or below, if needed.
Start searching from the next insn: either ignore_first is true, or
INSN doesn't have a correct live set. Put correct lv sets on the insns which have bad sets.
Also put it in a BB.
We return LV to the pool, but will not clear it there. Thus we can
legimatelly use LV till the next use of regset_pool_get ().
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Return livness set at the end of BB.
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Compute liveness below INSN and write it into REGS.
References spec_info_def::control_weakness_cutoff, spec_info_def::data_weakness_cutoff, ds_weak(), pipelining_p, and spec_info.
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Convert a vectored and sorted av set to the ready list that the rest of the backend wants to see.
Allocate and fill the ready list from the sorted vector.
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Helper function for count_occurences_equiv.
Bail out if mode is different or more than one register is used.
Do not traverse subexprs.
??? Do not support substituting regs inside subregs. In that case,
simplify_subreg will be called by validate_replace_rtx, and
unsubstitution will fail later. Continue search.
References cancel_changes(), get_dest_and_mode(), validate_change(), and verify_changes().
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Return the number of places WHAT appears within WHERE. Bail out when we found a reference occupying several hard registers.
References copy_rtx(), and create_insn_rtx_from_pattern().
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Create new basic block for bookkeeping code for path(s) incoming into E2->dest, except from E1->src. Return created block.
Check that we don't spoil the loop structure.
We do not split header.
We do not redirect the only edge to the latch block.
Split BB to insert BOOK_INSN there.
Move note_list from the upper bb.
Skip block for bookkeeping copy when leaving E1->src.
To keep basic block numbers in sync between debug and non-debug
compilations, we have to rotate blocks here. Consider that we
started from (a,b)->d, (c,d)->e, and d contained only debug
insns. It would have been removed before if the debug insns
weren't there, so we'd have split e rather than d. So what we do
now is to swap the block numbers of new_bb and
single_succ(new_bb) == e, so that the insns that were in e before
get the new block number.
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Create a pattern with rhs of VI and lhs of LHS_RTX.
Referenced by rtx_ok_for_substitution_p().
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Functions to support register renaming.
Substitute VI's set source with REGNO. Returns newly created pattern that has REGNO as its source.
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Get a speculation check instruction. C_EXPR is a speculative expression, CHECK_DS describes speculations that should be checked, ORIG_INSN is the original non-speculative insn in the stream.
Create a recovery block if target is going to emit branchy check, or if
ORIG_INSN was speculative already. Get pattern of the check.
Emit check.
Make check to be non-speculative.
Decrease priority of check by difference of load/check instruction
latencies. Emit copy of original insn (though with replaced target register,
if needed) to the recovery block. If we've generated a data speculation check, make sure
that all the bookkeeping instruction we'll create during
this move_op () will allocate an ALAT entry so that the
check won't fail.
In case of control speculation we must convert C_EXPR to control
speculative mode, because failing to do so will bring us an exception
thrown by the non-control-speculative load.
References can_substitute_through_p(), DEPS_IN_INSN, DEPS_IN_LHS, DEPS_IN_RHS, has_dependence_p(), MOVEUP_EXPR_AS_RHS, MOVEUP_EXPR_CHANGED, MOVEUP_EXPR_NULL, MOVEUP_EXPR_SAME, and substitute_reg_in_expr().
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Return true if all basic blocks of current region are empty.
Referenced by code_motion_process_successors().
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Referenced by find_file_set_debug().
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Debug a DFA state as an array of bytes.
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Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning NEW_SEQNO to it. Return created insn.
References get_nop_from_pool().
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Functions that implement the core of the scheduler.
Emit an instruction from EXPR with SEQNO and VINSN after PLACE_TO_INSERT.
This assert fails when we have identical instructions
one of which dominates the other. In this case move_op ()
finds the first instruction and doesn't search for second one.
The solution would be to compute av_set after the first found
insn and, if insn present in that set, continue searching.
For now we workaround this issue in move_op.
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Returns true if after moving EXPR along PATH it equals to EXPR_VLIW.
References global_level, is_ineligible_successor(), max_ws, sched_verbose, and sel_print().
Referenced by find_place_for_bookkeeping().
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Estimate the cost of issuing INSN on DFA state STATE.
References sel_bb_head().
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Construct successor fences from OLD_FENCEs and put them in NEW_FENCES. When a successor will continue a ebb, transfer all parameters of a fence to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round of scheduling helping to distinguish between the old and the new code.
Get the only element of FENCE_BNDS (fence).
When in the "middle" of the block, just move this fence
to the new list. Otherwise copy fence's structures to (possibly) multiple successors.
Mark block of the SUCC as head of the new ebb.
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Gather a parallel group of insns at FENCE and assign their seqno to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP list for later recalculation of seqnos.
Do while we can add any operation to the current group.
Return early if we have nothing to schedule.
Choose the best expression and, if needed, destination register
for it. All expressions required a stall. Do not recompute av sets
as we'll get the same answer (modulo the insns between
the fence and its boundary, which will not be available for
pipelining).
If we are going to stall for too long, break to recompute av
sets and bring more insns for pipelining. Now either we've selected expr_vliw or we have nothing to schedule.
This code will be executed only once until we'd have several
boundaries per fence. Add insn to the list of scheduled on this cycle instructions.
We currently support information about candidate blocks only for
one 'target_bb' block. Hence we can't schedule after jump insn,
as this will bring two boundaries and, hence, necessity to handle
information for two or more blocks concurrently. Update boundaries of the FENCE.
Update target context on the fence.
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Initialize ready list from *AV_PTR for the max_issue () call. If any unrecognizable insn found in *AV_PTR, return it (and skip max_issue). BND and FENCE are current boundary and fence, respectively. If we need to stall for some cycles before an expr from *AV_PTR would become available, write this number to *PNEED_STALL.
We do not support multiple boundaries per fence.
Process expressions required special handling, i.e. pipelined,
speculative and recog() < 0 expressions first. A USE could be scheduled immediately.
Turn the av set to a vector for sorting.
Build the final ready list.
Turn AV into a vector, filter inappropriate insns and sort it. Return true if there is something to schedule. BNDS and FENCE are current boundaries and fence, respectively. If we need to stall for some cycles before an expr from AV would become available, write this number to *PNEED_STALL.
Bail out early when the ready list contained only USEs/CLOBBERs that are
already scheduled. Empty vector from the previous stuff.
Turn the set into a vector for sorting and call sel_target_adjust_priority
for each insn. Adjust priority using target backend hook.
Sort the vector.
We record maximal priority of insns in av set for current instruction
group. Filter out inappropriate expressions. Loop's direction is reversed to
visit "best" instructions first. We assume that vec::unordered_remove
moves last element in place of one being deleted. Don't allow any insns other than from SCHED_GROUP if we have one.
Set number of sched_next insns (just in case there
could be several). Check all liveness requirements and try renaming.
FIXME: try to minimize calls to this. If insn was already scheduled on the current fence,
set TARGET_AVAILABLE to -1 no matter what expr's attribute says. If the availability of the EXPR is invalidated by the insertion of
bookkeeping earlier, make sure that we won't choose this expr for
scheduling if it's not separable, and if it is separable, then
we have to recompute the set of available registers for it. Do nothing -- we can use an existing register.
Don't try to find a register for low-priority expression.
??? FIXME: Don't try to rename data speculation.
Filter expressions that need to be renamed or speculated when
pipelining, because compensating register copies or speculation
checks are likely to be placed near the beginning of the loop,
causing a stall. Estimation of number of cycles until loop branch for
renaming/speculation to be successful. We want to schedule speculation checks as late as possible. Discard
them from av set if there are instructions with higher priority. Ignore EXPRs available from pipelining to update AV_MAX_PRIO.
Don't allow any insns whose data is not yet ready.
Check first whether we've already tried them and failed. Now resort to dependence analysis to find whether EXPR might be
stalled due to dependencies from FENCE's context. Clear SCHED_NEXT.
No need to stall if this variable was not initialized.
We need to set *pneed_stall here, because later we skip this code
when ready list is empty. Sort the vector.
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Choose the best expr from *AV_VLIW_PTR and a suitable register for it. BNDS and FENCE are current boundaries and scheduling fence respectively. Return the expr found and NULL if nothing can be issued atm. Write to PNEED_STALL the number of cycles to stall if no expr was found.
Choose the best insn for scheduling via:
1) sorting the ready list based on priority;
2) calling the reorder hook;
3) calling max_issue. Try choosing the best insn until we find one that is could be
scheduled due to liveness restrictions on its destination register.
In the future, we'd like to choose once and then just probe insns
in the order of their priority. We had some available insns, so if we can't issue them,
we have a stall.
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Select and assign best register to EXPR searching from BNDS.
Set *IS_ORIG_REG_P to TRUE if original register was selected.
Return FALSE if no register can be chosen, which could happen when:
* EXPR_SEPARABLE_P is true but we were unable to find suitable register;
* EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
that are used on the moving path. Don't bother to do anything if this insn doesn't set any registers.
If after reload, make sure we're working with hard regs here.
Check that we have computed availability of a target register
correctly. Turn everything in hard regs after reload.
Join hard registers unavailable due to register class
restrictions and live range intersection. In case of unification BEST_REG may be different from EXPR's LHS
when EXPR's LHS is unavailable, and there is another LHS among
ORIGINAL_INSNS. Forbid renaming of low-cost insns.
If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
any of the HARD_REGS_USED set.
|
static |
Referenced by invoke_aftermath_hooks().
|
static |
Attempt to find a block that can hold bookkeeping code for path(s) incoming into E2->dest, except from E1->src (there may be a sequence of empty basic blocks between E1->src and E2->dest). Return found block, or NULL if new one must be created. If LAX holds, don't assume there is a simple path from E1->src to E2->dest.
Loop over edges from E1 to E2, inclusive.
Found additional edge leading to path from e1 to e2
from aside. Several edges leading to path from e1 to e2 from aside.
|
static |
Find boundaries of the EBB starting from basic block BB, marking blocks of this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL, PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure.
|
inlinestatic |
Return an EXPR corresponding to INDEX element of ready list, if FOLLOW_READY_ELEMENT is true (i.e., an expr of ready_element (&ready, INDEX) will be returned), and to INDEX element of ready.vec otherwise.
|
static |
Calculate MIN_SEQNO and MAX_SEQNO.
The first element is already processed.
Referenced by sel_region_init().
|
static |
Return insn after which we must insert bookkeeping code for path(s) incoming into E2->dest, except from E1->src. If the returned insn immediately precedes a fence, assign that fence to *FENCE_TO_REWIND.
Find a basic block that can hold bookkeeping. If it can be found, do not
create new basic block, but insert bookkeeping there. Don't use a block containing only debug insns for
bookkeeping, this causes scheduling differences between debug
and non-debug compilations, for the block would have been
removed already. If basic block ends with a jump, insert bookkeeping code right before it.
Notice if we are crossing a fence when taking PREV_INSN.
References av_set_add(), equal_after_moveup_path_p(), expr_dest_regno(), replace_dest_with_reg_in_expr(), stat_renamed_scheduled, and stat_substitutions_total.
|
static |
Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT for JOIN_POINT.
Check if we are about to insert bookkeeping copy before a jump, and use
jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. Sometimes the fences can move in such a way that there will be
no instructions with positive seqno around this bookkeeping.
This means that there will be no way to get to it by a regular
fence movement. Never mind because we pick up such pieces for
rescheduling anyways, so any positive value will do for now.
Referenced by choose_best_reg().
|
static |
Calculate the sequential av set on BND corresponding to the EXPR_VLIW expression. When FOR_MOVEOP is true, also replace the register of expressions found with the register from EXPR_VLIW.
The sequential expression has the right form to pass
to move_op except when renaming happened. Put the
correct register in EXPR then. Also put the correct TARGET_AVAILABLE bit on the expr.
This is needed when renaming came up with original
register. With substitution inside insn group, it is possible
that more than one expression in expr_seq will correspond
to expr_vliw. In this case, choose one as the attempt to
move both leads to miscompiles.
|
static |
Find the set of registers that are unavailable for storing expres
while moving ORIG_OPS up on the path starting from INSN due to
liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
All the original operations found during the traversal are saved in the
ORIGINAL_INSNS list.
REG_RENAME_P denotes the set of hardware registers that
can not be used with renaming due to the register class restrictions,
mode restrictions and other (the register we'll choose should be
compatible class with the original uses, shouldn't be in call_used_regs,
should be HARD_REGNO_RENAME_OK etc).
Returns TRUE if we've found all original insns, FALSE otherwise.
This function utilizes code_motion_path_driver (formerly find_used_regs_1)
to traverse the code motion paths. This helper function finds registers
that are not available for storing expres while moving ORIG_OPS up on the
path starting from INSN. A register considered as used on the moving path,
if one of the following conditions is not satisfied:
(1) a register not set or read on any path from xi to an instance of
the original operation,
(2) not among the live registers of the point immediately following the
first original operation on a given downward path, except for the
original target register of the operation,
(3) not live on the other path of any conditional branch that is passed
by the operation, in case original operations are not present on
both paths of the conditional branch.
All the original operations found during the traversal are saved in the
ORIGINAL_INSNS list.
REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
from INSN to original insn. In this case CALL_USED_REG_SET will be added
to unavailable hard regs at the point original operation is found. We haven't visited any blocks yet.
Init parameters for code_motion_path_driver.
Set the appropriate hooks and data.
??? We calculate whether an expression needs a check when computing
av sets. This information is not as precise as it could be due to
merging this bit in merge_expr. We can do better in find_used_regs,
but we want to avoid multiple traversals of the same code motion
paths. Mark hardware regs in REG_RENAME_P that are not suitable
for renaming expr in INSN due to hardware restrictions (register class,
modes compatibility etc). Do not allow clobbering of ld.[sa] address in case some of the
original operations need a check.
References av_set_iter_remove().
Referenced by choose_best_reg().
|
static |
This function is called on the ascending pass, before returning from the current basic block.
|
static |
Add used regs for the successor SUCC into SPARAMS->USED_REGS.
SUCC is one of the SUCCS_NORMAL successors of INSN,
MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
if SUCC is one of SUCCS_BACK or SUCCS_OUT.
STATIC_PARAMS contain USED_REGS set. Here we compute live regsets only for branches that do not lie
on the code motion paths. These branches correspond to value
MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
for such branches code_motion_path_driver is not called. Mark all registers that do not meet the following condition:
(3) not live on the other path of any conditional branch
that is passed by the operation, in case original
operations are not present on both paths of the
conditional branch.
|
static |
This function is called on enter to the basic block. Returns TRUE if this block already have been visited and code_motion_path_driver should return 1, FALSE otherwise.
If we have found something below this block, there should be at
least one insn in ORIGINAL_INSNS. Adjust CROSSES_CALL, since we may have come to this block along
different path.
|
static |
The function is called when original expr is found. INSN - current insn traversed, EXPR - the corresponding expr found, crosses_call and original_insns in STATIC_PARAMS are updated.
Mark the registers that do not meet the following condition:
(2) not among the live registers of the point
immediately following the first original operation on
a given downward path, except for the original target
register of the operation. (*1) We need to add to USED_REGS registers that are read by
INSN's lhs. This may lead to choosing wrong src register.
E.g. (scheduling const expr enabled):
429: ax=0x0 <- Can't use AX for this expr (0x0)
433: dx=[bp-0x18]
427: [ax+dx+0x1]=ax
REG_DEAD: ax
168: di=dx
REG_DEAD: dx FIXME: see comment above and enable MEM_P
in vinsn_separable_p.
|
static |
This function is called while descending current basic block if current insn is not the original EXPR we're searching for. Return value: TRUE (code_motion_path_driver should continue).
If current insn we are looking at cannot be executed together
with original insn, then we can skip it safely.
Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
INSN = (!p6) r14 = r14 + 1;
Here we can schedule ORIG_OP with lhs = r14, though only
looking at the set of used and set registers of INSN we must
forbid it. So, add set/used in INSN registers to the
untouchable set only if there is an insn in ORIG_OPS that can
affect INSN. Mark all registers that do not meet the following condition:
(1) Not set or read on any path from xi to an instance of the
original operation.
References bitmap_clear_bit().
|
static |
|
static |
Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to E2->dest, except from E1->src (there may be a sequence of empty blocks between E1->src and E2->dest). Return block containing the copy. All scheduler data is initialized for the newly created insn.
When inserting bookkeeping insn in new block, av sets should be
following: old basic block (that now holds bookkeeping) data sets are
the same as was before generation of bookkeeping, and new basic block
(that now hold all other insns of old basic block) data sets are
invalid. So exchange data sets for these basic blocks as sel_split_block
mistakenly exchanges them in this case. Cannot do it earlier because
when single instruction is added to new basic block it should hold NULL
lv_set.
|
static |
All exprs in ORIG_OPS must have the same destination register or memory. Return that destination.
|
static |
Return the cost of issuing EXPR on the FENCE as estimated by DFA. This function properly handles ASMs, USEs etc.
This is asm insn which is tryed to be issued on the
cycle not first. Issue it on the next cycle. A USE insn, or something else we don't need to
understand. We can't pass these directly to
state_transition because it will trigger a
fatal error for unrecognizable insns.
|
static |
Returns register class of the output register in INSN. Returns NO_REGS for call insns because some targets have constraints on destination register of a call insn. Code adopted from regrename.c::build_def_use.
Insns like
(insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
may result in returning NO_REGS, cause flags is written implicitly through
CMP insn, which has no OP_OUT | OP_INOUT operands.
|
static |
Helper for move_op () and find_used_regs (). Return speculation type for which a check should be created on the place of INSN. EXPR is one of the original ops we are searching for.
References av_set_iter_remove().
|
static |
Handle transformations that leave an insn in place of original insn such as renaming/speculation. Return true if one of such transformations actually happened, and we have emitted this insn.
|
static |
True when INSN is a "regN = regN" copy.
|
static |
Return true when the conflict with newly created implicit clobbers between EXPR and THROUGH_INSN is found because of renaming.
Make a new pseudo register.
Validate a change and bail out early.
Make a new insn with it.
Calculate implicit clobbers.
If any implicit clobber registers intersect with regular ones in
through_insn, we have a dependency and thus bail out.
Referenced by moving_insn_creates_bookkeeping_block_p().
|
static |
Returns true when SUCC in a fallthru bb of INSN, possibly skipping empty basic blocks.
|
static |
Calculate HARD_REGNO_RENAME_OK data for REGNO.
We are not interested in renaming in other regs.
References _def::orig_insn, and SET.
|
static |
Init all register sets gathered in HRD.
Initialize registers that are valid based on mode when this is
really needed. Mark that all HARD_REGNO_RENAME_OK is not calculated.
|
static |
Calculate set of registers that are capable of holding MODE.
Can't use regs which aren't saved by
the prologue. Can't use regs with non-null REG_BASE_VALUE, because adjusting
it affects aliasing globally and invalidates all AV sets. We can't use a non-leaf register if we're in a
leaf function. See whether it accepts all modes that occur in
original insns. If the CUR_REG passed all the checks above,
then it's ok.
References _def::crosses_call, and reg_rename::unavailable_hard_regs.
|
static |
Initialize seqnos for the current region. BLOCKS_TO_RESCHEDULE contains blocks on which we're rescheduling when pipelining, FROM is the block where traversing region begins (it may not be the head of the region when pipelining, but the head of the loop instead). Returns the maximal seqno found.
cur_seqno may be positive if the number of instructions is less than
sched_max_luid - 1 (when rescheduling or if some instructions have been
removed by the call to purge_empty_blocks in sel_sched_region_1).
|
static |
A helper for init_seqno. Traverse the region starting from BB and compute seqnos for visited insns, marking visited bbs in VISITED_BBS. Clear visited blocks from BLOCKS_TO_RESCHEDULE.
Referenced by move_op_on_enter().
|
static |
Call the rest of the hooks after the choice was made. Return the number of insns that still can be issued given that the current number is ISSUE_MORE. FENCE and BEST_INSN are the current fence and the insn chosen for scheduling, respectively.
First, call dfa_new_cycle, and then variable_issue, if available.
References find_block_for_bookkeeping().
|
static |
Calculate insns worth trying via lookahead_guard hook. Return a number of such insns found.
In this loop insn is Ith element of the ready list given by
ready_element, not Ith element of ready.vec. Only insns with ready_try = 0 can get here
from fill_ready_list.
|
static |
Invoke reorder* target hooks on the ready list. Return the number of insns we can issue. FENCE is the current fence.
Call the reorder hook at the beginning of the cycle, and call
the reorder2 hook in the middle of the cycle. Don't give reorder the most prioritized insn as it can break
pipelining. Initialize can_issue_more for variable_issue.
Ensure that ready list and vec_av_set are in line with each other,
i.e. vec_av_set[i] == ready_element (&ready, i).
References df_set_regs_ever_live(), expr_dest_regno(), and reg_rename_this_tick.
|
static |
Functions that compute av and lv sets.
Returns true if INSN is not a downward continuation of the given path P in the current stage.
Check if insn is not deleted.
If it's the first insn visited, then the successor is ok.
is already visited.
We can reach another fence here and still seqno of insn
would be equal to seqno of prev_insn. This is possible
when prev_insn is a previously created bookkeeping copy.
In that case it'd get a seqno of insn. Thus, check here
whether insn is in current fence too. Was already scheduled on this round.
An insn from another fence could also be
scheduled earlier even if this insn is not in
a fence list right now. Check INSN_SCHED_CYCLE instead.
Referenced by equal_after_moveup_path_p(), and moveup_set_expr().
|
static |
Mark hardware regs in REG_RENAME_P that are not suitable for renaming rhs in INSN due to hardware restrictions (register class, modes compatibility etc). This doesn't affect original insn's dest reg, if it isn't in USED_REGS. DEF is a definition insn of rhs for which the destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM. Registers that are in used_regs are always marked in unavailable_hard_regs as well.
We have decided not to rename 'mem = something;' insns, as 'something'
is usually a register. If before reload, don't try to work with pseudos.
Stop if the original register is one of the fixed_regs, global_regs or
frame pointer, or we could not discover its class. Give a chance for original register, if it isn't in used_regs.
If something allocated on stack in this function, mark frame pointer
register unavailable, considering also modes.
FIXME: it is enough to do this once per all original defs. For the stack registers the presence of FIRST_STACK_REG in USED_REGS
is equivalent to as if all stack regs were in this set.
I.e. no stack register can be renamed, and even if it's an original
register here we make sure it won't be lifted over it's previous def
(it's previous def will appear as if it's a FIRST_STACK_REG def.
The HARD_REGNO_RENAME_OK covers other cases in condition below. If there's a call on this path, make regs from call_used_reg_set
unavailable. Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
but not register classes. Leave regs as 'available' only from the current
register class. Leave only registers available for this mode.
Exclude registers that are partially call clobbered.
Leave only those that are ok to rename.
Regno is always ok from the renaming part of view, but it really
could be in *unavailable_hard_regs already, so set it here instead
of there.
References reg_rename::available_for_renaming, gen_rtx_REG(), rtx_search_arg::n, and _def::orig_insn.
|
static |
Emit a register-register copy for INSN if needed. Return true if emitted one. PARAMS is the move_op static parameters.
Bail out early when expression can not be renamed at all.
If original operation has expr and the register chosen for
that expr is not original operation's dest reg, substitute
operation's right hand side with the register chosen.
References sched_verbose, and sel_print().
|
static |
Emit a speculative check for INSN speculated as EXPR if needed. Return true if we've emitted one. PARAMS is the move_op static parameters.
A speculation check should be inserted.
| bool maybe_skip_selective_scheduling | ( | void | ) |
Return true when we need to skip selective scheduling. Used for debugging.
Referenced by sched_rgn_local_free().
|
static |
@verbatim
Moving conditional jump through some instructions.
Consider example:
... <- current scheduling point NOTE BASIC BLOCK: <- bb header (p8) add r14=r14+0x9;; (p8) mov [r14]=r23 (!p8) jump L1;; NOTE BASIC BLOCK: ...
We can schedule jump one cycle earlier, than mov, because they cannot be executed together as their predicates are mutually exclusive.
This is done in this way: first, new fallthrough basic block is created after jump (it is always can be done, because there already should be a fallthrough block, where control flow goes in case of predicate being true - in our example; otherwise there should be a dependence between those instructions and jump and we cannot schedule jump right now); next, all instructions between jump and current scheduling point are moved to this new block. And the result is this:
NOTE BASIC BLOCK: (!p8) jump L1 <- current scheduling point NOTE BASIC BLOCK: <- bb header (p8) add r14=r14+0x9;; (p8) mov [r14]=r23 NOTE BASIC BLOCK: ...
Moving of jump should not cross any other jumps or beginnings of new
basic blocks. The only exception is when we move a jump through
mutually exclusive insns along fallthru edges. Jump is moved to the boundary.
There must be a fallthrough block (or where should go control flow in case of false jump predicate otherwise?).
Create new empty basic block after source block.
Move all instructions except INSN to BLOCK_NEW.
The jump being moved can be the first insn in the block.
In this case we don't have to move anything in this block. Cleanup possibly empty blocks left.
Assert there is no jump to BLOCK_NEW, only fallthrough edge.
Update data sets for BLOCK_NEW to represent that INSN and
instructions from the other branch of INSN is no longer
available at BLOCK_NEW. INSN is a new basic block header - so prepare its data
structures and update availability and liveness sets.
|
static |
Find original instructions for EXPR_SEQ and move it to BND boundary. Return the expression to emit in C_EXPR.
Make a move. This call will remove the original operation,
insert all necessary bookkeeping instructions and update the
data sets. After that all we have to do is add the operation
at before BND_TO (BND). We should be able to find the expression we've chosen for
scheduling. We allocate these bitmaps lazily.
Transitively add all originators' originators.
References av_set_clear(), av_set_copy(), av_set_lookup(), sel_bb_head(), update_data_sets(), and vinsn_vec_add().
|
static |
Move nop to previous block.
|
static |
Move up the operations from ORIG_OPS set traversing the dag starting from INSN. PATH represents the edges traversed so far. DEST is the register chosen for scheduling the current expr. Insert bookkeeping code in the join points. EXPR_VLIW is the chosen expression, C_EXPR is how it looks like at the given cfg point. Set *SHOULD_MOVE to indicate whether we have only disconnected one of the insns found. Returns whether original instructions were found, which is asserted to be true in the caller.
Init params for code_motion_path_driver.
We haven't visited any blocks yet.
Set appropriate hooks and data.
|
static |
This function is called after the last successor. Copies LP->C_EXPR_MERGED into SP->CEXPR.
|
static |
Called on the backward stage of recursion to call moveup_expr for insn and sparams->c_expr.
Update liveness for this insn as it was invalidated.
|
static |
This function is called on the ascending pass, before returning from current basic block.
When we have removed the boundary insn for scheduling, which also
happened to be the end insn in its bb, we don't need to update sets. We should generate bookkeeping code only if we are not at the
top level of the move_op. Update data sets for the current insn.
If bookkeeping code was inserted, we need to update av sets of basic
block that received bookkeeping. After generation of bookkeeping insn,
bookkeeping block does not contain valid av set because we are not following
the original algorithm in every detail with regards to e.g. renaming
simple reg-reg copies. Consider example:
bookkeeping block scheduling fence
\ /
\ join /
----------
| |
----------
/ \
/ \
r1 := r2 r1 := r3
We try to schedule insn "r1 := r3" on the current
scheduling fence. Also, note that av set of bookkeeping block
contain both insns "r1 := r2" and "r1 := r3". When the insn has
been scheduled, the CFG is as follows:
r1 := r3 r1 := r3
bookkeeping block scheduling fence
\ /
\ join /
----------
| |
----------
/ \
/ \
r1 := r2
Here, insn "r1 := r3" was scheduled at the current scheduling point
and bookkeeping code was generated at the bookeeping block. This
way insn "r1 := r2" is no longer available as a whole instruction
(but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
This situation is handled by calling update_data_sets.
Since update_data_sets is called only on the bookkeeping block, and
it also may have predecessors with av_sets, containing instructions that
are no longer available, we save all such expressions that become
unavailable during data sets update on the bookkeeping block in
VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
expressions for scheduling. This allows us to avoid recomputation of
av_sets outside the code motion path. If INSN was previously marked for deletion, it's time to do it.
Do not tidy control flow at the topmost moveop, as we can erroneously
kill a block with a single nop in which the insn should be emitted.
|
static |
The main effect of this function is that sparams->c_expr is merged with (or copied to) lparams->c_expr_merged. If there's only one successor, we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged. lparams->c_expr_merged is copied back to sparams->c_expr after all successors has been traversed. lparams->c_expr_local is an expr allocated on stack in the caller function, and is used if there is more than one successor. SUCC is one of the SUCCS_NORMAL successors of INSN, MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ, LPARAMS and STATIC_PARAMS contain the parameters described above.
Nothing to do, if original expr wasn't found below.
If this is a first successor.
We must merge all found expressions to get reasonable
EXPR_SPEC_DONE_DS for the resulting insn. If we don't
do so then we can first find the expr with epsilon
speculation success probability and only then with the
good probability. As a result the insn will get epsilon
probability and will never be scheduled because of
weakness_cutoff in find_best_expr.
We call merge_expr_data here instead of merge_expr
because due to speculation C_EXPR and X may have the
same insns with different speculation types. And as of
now such insns are considered non-equal.
However, EXPR_SCHED_TIMES is different -- we must get
SCHED_TIMES from a real insn, not a bookkeeping copy.
We force this here. Instead, we may consider merging
SCHED_TIMES to the maximum instead of minimum in the
below function.
|
static |
Same as above but for move_op.
References bitmap_bit_p(), bitmap_set_bit(), in_current_region_p(), basic_block_def::index, and init_seqno_1().
|
static |
This function is called when original expr is found. INSN - current insn traversed, EXPR - the corresponding expr found. LPARAMS is the local parameters of code modion driver, STATIC_PARAMS is static parameters of move_op.
Mark that we've disconnected an insn.
|
static |
This function is called while descending current basic block if current
insn is not the original EXPR we're searching for.
Return value: FALSE, if code_motion_path_driver should perform a local
cleanup and return 0 itself;
TRUE, if code_motion_path_driver should continue. If we're scheduling separate expr, in order to generate correct code
we need to stop the search at bookkeeping code generated with the
same destination register or memory.
|
static |
Modifies EXPR so it can be moved through the THROUGH_INSN, performing necessary transformations. Record the type of transformation made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP, permit all dependencies except true ones, and try to remove those too via forward substitution. All cases when a non-eliminable non-zero cost dependency exists inside an insn group will be fixed in tick_check_p instead.
??? We use dependencies of non-debug insns on debug insns to
indicate that the debug insns need to be reset if the non-debug
insn is pulled ahead of it. It's hard to figure out how to
introduce such a notion in sel-sched, but it already fails to
support debug insns in other ways, so we just go ahead and
let the deug insns go corrupt for now. When inside_insn_group, delegate to the helper.
Deal with unique insns and control dependencies.
We can move jumps without side-effects or jumps that are
mutually exclusive with instruction THROUGH_INSN (all in cases
dependencies allow to do so and jump is not speculative). Do not move checks and do not move jumps through other
jumps. Don't move jumps through CFG joins.
The jump should have a clear fallthru block, and
this block should be in the current region. And it should be mutually exclusive with through_insn.
Don't move what we can't move.
Don't move SCHED_GROUP instruction through anything.
If we don't force this, then it will be possible to start
scheduling a sched_group before all its dependencies are
resolved.
??? Haifa deals with this issue by delaying the SCHED_GROUP
as late as possible through rank_for_schedule. Don't move debug insns if this would require bookkeeping.
Deal with data dependencies.
We can move UNIQUE insn up only as a whole and unchanged,
so it shouldn't have any dependencies. Speculation was successful.
We have some dependency that cannot be discarded.
Only separable insns can be moved up with the new register.
Anyways, we should mark that the original register is
unavailable. When renaming a hard register to a pseudo before reload, extra
dependencies can occur from the implicit clobbers of the insn.
Filter out such cases here. At this point we have either separable insns, that will be lifted
up only as RHSes, or non-separable insns with no dependency in lhs.
If dependency is in RHS, then try to perform substitution and move up
substituted RHS:
Ex. 1: Ex.2
y = x; y = x;
z = y*2; y = y*2;
In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
moved above y=x assignment as z=x*2.
In Ex.2 y*2 also can be substituted for x*2, but only the right hand
side can be moved because of the output dependency. The operation was
cropped to its rhs above. Can't substitute UNIQUE VINSNs.
Speculation was successful.
??? We cannot perform substitution AND speculation on the same
insn. Don't move trapping insns through jumps.
This check should be at the end to give a chance to control speculation
to perform its duties.
|
static |
Same as moveup_expr, but first looks up the result of transformation in caches.
Don't use cached information for debug insns that are heads of
basic blocks. When inside insn group, we do not want remove stores conflicting
with previosly issued loads. Invoke moveup_expr and record the results.
??? Invent something better than this. We can't allow old_vinsn
to go, we need it for the history vector.
References av_set_copy(), av_set_is_in_p(), and av_set_iter_remove().
Referenced by try_transformation_cache().
|
static |
Moveup_* helpers for code motion and computing av sets.
Propagates EXPR inside an insn group through THROUGH_INSN. The difference from the below function is that only substitution is performed.
Do this only inside insn group.
Substitution is the possible choice in this case.
Can't substitute UNIQUE VINSNs.
Don't care about this, as even true dependencies may be allowed
in an insn group. This can catch output dependencies in COND_EXECs.
This is either an output or an anti dependence, which usually have
a zero latency. Allow this here, if we'd be wrong, tick_check_p
will fix this.
|
static |
Moves an av set AVP up through INSN, performing necessary transformations.
References cur_insn, is_ineligible_successor(), sched_verbose, sel_bb_end(), and sel_print().
|
static |
Moves AVP set along PATH.
Return true when moving a debug INSN across THROUGH_INSN will create a bookkeeping block. We don't want to create such blocks, for they would cause codegen differences between compilations with and without debug info.
References enable_schedule_as_rhs_p, implicit_clobber_conflict_p(), MOVEUP_EXPR_NULL, reload_completed, sched_verbose, and sel_print().
|
static |
If INSN is the only insn in the basic block (not counting JUMP, which may be a jump to next insn, and DEBUG_INSNs), we want to leave a NOP there till the return to fill_insns.
References sched_verbose, and sel_print().
|
static |
Prepare a place to insert the chosen expression on BND.
Init place_to_insert before calling move_op, as the later
can possibly remove BND_TO (bnd). Add it after last scheduled.
Add it before BND_TO. The difference is in the
basic block, where INSN will be added.
References rtx_equal_p().
|
static |
Filter out expressions from av set pointed to by AV_PTR that are pipelined too many times.
Don't pipeline already pipelined code as that would increase
number of unnecessary register moves.
|
static |
Filter speculative insns from AV_PTR if we don't want them.
Scan *AV_PTR to find out if we want to consider speculative
instructions for scheduling. The probability of a success is too low - don't speculate.
We don't want any data speculative instructions right
now. We don't want any control speculative instructions right
now.
|
static |
Search for any use-like insns in AV_PTR and decide on scheduling them. Return one when found, and NULL otherwise. Note that we check here whether a USE could be scheduled to avoid an infinite loop later.
This will also initialize INSN_CODE for later use.
If we have a USE in *AV_PTR that was not scheduled yet,
do so because it will do good only. If we don't want to schedule any USEs right now and we have some
in *AV_PTR, remove them, else just return the first one found.
|
static |
Propagate a liveness set LV through INSN.
|
static |
Put TImode markers on insns starting a new issue group.
|
static |
Remove INSN from stream. When ONLY_DISCONNECT is true, its data is not removed but reused when INSN is re-emitted.
If there's only one insn in the BB, make sure that a nop is
inserted into it, so the basic block won't disappear when we'll
delete INSN below with sel_remove_insn. It should also survive
till the return to fill_insns.
References basic_block_def::index, sched_verbose, and sel_print().
|
static |
Remove from AV_VLIW_P all instructions but next when debug counter tells us so. Next instruction is fetched from BNDS.
Leave only the next insn in av_vliw.
|
static |
Remove from AV_PTR all insns that may need bookkeeping when scheduling on FENCE, but we are unable to copy them.
An expression does not need bookkeeping if it is available on all paths
from current block to original block and current block dominates
original block. We check availability on all paths by examining
EXPR_SPEC; this is not equivalent, because it may be positive even
if expr is available on all paths (but if expr is not available on
any path, EXPR_SPEC will be positive).
References dfa_state_size, and sel_print().
|
static |
Remove nops generated during move_op for preventing removal of empty basic blocks.
Empty the vector.
|
static |
Substitute lhs in the given expression EXPR for the register with number NEW_REGNO. SET_DEST may be arbitrary rtx, not only register.
Referenced by choose_best_pseudo_reg(), and find_place_for_bookkeeping().
|
static |
Returns whether INSN still be valid after replacing it's DEST with register NEW_REG.
We should deal here only with separable insns.
See whether SET_DEST can be replaced with this register.
Referenced by choose_best_pseudo_reg().
|
static |
Returns whether INSN's src can be replaced with register number
NEW_SRC_REG. E.g. the following insn is valid for i386:
(insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
(set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
(reg:SI 0 ax [orig:770 c1 ] [770]))
(const_int 288 [0x120])) [0 str S1 A8])
(const_int 0 [0x0])) 43 {*movqi_1} (nil)
(nil))
But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
because of operand constraints:
(define_insn "*movqi_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
(match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
)]
So do constrain_operands here, before choosing NEW_SRC_REG as best
reg for rhs. See whether SET_SRC can be replaced with this register.
References asm_noperands(), operand_alternative::cl, constrain_operands(), extract_insn(), operand_alternative::matches, recog_data_d::n_operands, OP_OUT, recog_data_d::operand_loc, recog_data_d::operand_type, preprocess_constraints(), recog_data, recog_op_alt, and which_alternative.
Referenced by choose_best_pseudo_reg().
|
static |
Regenerate INSN_SCHED_CYCLEs for insns of current EBB.
None of the arguments are actually used in any target.
NB: We should have md_reset () hook for cases like this. Initialize HAIFA_COST.
This is asm insn which *had* to be scheduled first
on the cycle. This is a use/clobber insn. It should not change
cost. Stall for whatever cycles we've stalled before.
The DFA may report that e.g. insn requires 2 cycles to be
issued, but on the next cycle it says that insn is ready
to go. Check this here. When the data dependency stall is longer than the DFA stall,
and when we have issued exactly issue_rate insns and stalled,
it could be that after this longer stall the insn will again
become unavailable to the DFA restrictions. Looks strange
but happens e.g. on x86-64. So recheck DFA on the last
iteration.
Forward declarations of static functions.
|
static |
Returns TRUE if WHAT is found in WHERE rtx tree.
References change_vinsn_in_expr(), create_insn_rtx_with_lhs(), and create_vinsn_from_insn_rtx().
| void run_selective_scheduling | ( | void | ) |
The entry point.
Referenced by sched_rgn_local_free().
|
static |
Schedule EXPR_VLIW on BND. Return the insn emitted.
In case of scheduling a jump skipping some other instructions,
prepare CFG. After this, jump is at the boundary and can be
scheduled as usual insn by MOVE_OP. Speculative jumps are not handled.
Find a place for C_EXPR to schedule.
Add the instruction. The corner case to care about is when
the expr_seq set has more than one expr, and we chose the one that
is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
we can't use it. Generate the new vinsn. Return the nops generated for preserving of data sets back
into pool. Save the expression scheduled so to reset target availability if we'll
meet it later on the same fence. Check that the recent movement didn't destroyed loop
structure.
|
static |
Functions that implement the scheduler driver.
Schedule a parallel instruction group on each of FENCES. MAX_SEQNO is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list of insns scheduled -- these would be postprocessed later.
Choose the next fence group to schedule.
The fact that insn can be scheduled only once
on the cycle is guaranteed by two properties:
1. seqnos of parallel groups decrease with each iteration.
2. If is_ineligible_successor () sees the larger seqno, it
checks if candidate insn is_in_current_fence_p (). ??? Seqnos of different groups should be different.
As FENCE is nonnull, SEQNO is initialized.
All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
don't need to keep bookkeeping-invalidated and target-unavailable
vinsns any more.
Referenced by sel_region_init().
| void sel_add_to_insn_priority | ( | rtx | insn, |
| int | amount | ||
| ) |
Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT.
References targetm.
|
static |
Compute instruction priorities for current region.
Compute insn priorities in haifa style. Then free haifa style
dependencies that we've calculated for this.
Referenced by code_motion_process_successors().
|
static |
Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced.
References dump_expr(), and sel_print().
|
static |
Free the global data of the scheduler.
|
static |
Perform global init for the scheduler.
Setup the infos for sched_init.
Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass.
|
inlinestatic |
A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs data first.
Check whether this is all calculated.
|
static |
|
static |
Rank two available exprs for schedule. Never return 0 here.
Schedule debug insns as early as possible.
Prefer SCHED_GROUP_P insns to any others.
Now uniqueness means SCHED_GROUP_P is set, because schedule groups
cannot be cloned. Discourage scheduling of speculative checks.
Prefer not scheduled insn over scheduled one.
Prefer jump over non-jump instruction.
Prefer an expr with greater priority.
This code was taken from haifa-sched.c: rank_for_schedule ().
Prefer an old insn to a bookkeeping insn.
Prefer an insn with smaller UID, as a last resort.
We can't safely use INSN_LUID as it is defined only for those insns
that are in the stream.
|
static |
Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P is true, make an additional pass emulating scheduler to get correct insn cycles for md_finish calls.
Free the vectors.
If LV_SET of the region head should be updated, do it now because
there will be no other chance. Emulate the Haifa scheduler for bundling.
|
static |
Init scheduling data for RGN. Returns true when this region should not be scheduled.
Even if sched_is_disabled_for_current_region_p() is true, we still
do region initialization here so the region can be bundled correctly,
but we'll skip the scheduling in sel_sched_region (). Initialize luids and dependence analysis which both sel-sched and haifa
need. Initialize haifa data.
Main initialization.
Init correct liveness sets on each instruction of a single-block loop.
This is the only situation when we can't update liveness when calling
compute_live for the first insn of the loop. Set hooks so that no newly generated insn will go out unnoticed.
!!! We call target.sched.init () for the whole region, but we invoke
targetm.sched.finish () for every ebb. None of the arguments are actually used in any target.
Reset register allocation ticks array.
References calculate_new_fences(), find_min_max_seqno(), num_insns_scheduled, sched_verbose, schedule_on_fences(), scheduled_insns, sel_print(), stat_bookkeeping_copies, stat_insns_needed_bookkeeping, stat_renamed_scheduled, stat_substitutions_total, and update_seqnos_and_stage().
|
static |
Perform MD_FINISH on EBBs comprising current region. When RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler to produce correct sched cycles on insns.
While pipelining outer loops, skip bundling for loop
preheaders. Those will be rescheduled in the outer loop. Extend luids so that insns generated by the target will
get zero luid.
| void sel_sched_region | ( | ) |
Schedule the RGN region.
Force initialization of INSN_SCHED_CYCLEs for correct bundling.
|
static |
Schedule a region. When pipelining, search for possibly never scheduled bookkeeping code and schedule it. Reschedule pipelined code without pipelining after.
Remove empty blocks that might be in the region from the beginning.
When pipelining outer loops, create fences on the loop header,
not preheader. Schedule newly created code, that has not been scheduled yet.
While pipelining outer loops, skip bundling for loop
preheaders. Those will be rescheduled in the outer
loop. Mark BB as head of the new ebb.
|
static |
|
static |
The main driver for scheduling a region. This function is responsible for correct propagation of fences (i.e. scheduling points) and creating a group of parallel insns at each of them. It also supports pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass of scheduling.
|
static |
Initialize scheduling parameters for current region.
Referenced by code_motion_process_successors().
|
static |
Functions to choose the best insn from available ones.
Adjusts the priority for EXPR using the backend *_adjust_priority hook.
If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly.
References moveop_static_params::dest, moveop_static_params::failed_insn, and register_unavailable_p().
|
static |
Prepare and verify loop nest for pipelining.
If this loop has any saved loop preheaders from nested loops,
add these basic blocks to the current region. Check that we're starting with a valid information.
Referenced by code_motion_process_successors().
|
static |
Simplify insns after the scheduling.
|
static |
Stall for N cycles on FENCE.
|
static |
Substitute all occurrences of INSN's destination in EXPR' vinsn with INSN's source (if INSN is eligible for substitution). Returns TRUE if substitution was actually performed, FALSE otherwise. Substitution might be not performed because it's either EXPR' vinsn doesn't contain INSN's destination or the resulting insn is invalid for the target machine. When UNDO is true, perform unsubstitution instead (the difference is in the part of rtx on which validate_replace_rtx is called).
Do not try to replace in SET_DEST. Although we'll choose new
register for the RHS, we don't want to change RHS' original reg.
If the insn is not SET, we may still be able to substitute something
in it, and if we're here (don't have deps), it doesn't write INSN's
dest. Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI.
We should copy these rtxes before substitution.
Where we'll replace.
WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
used instead of SET_SRC. ??? Actually, constrain_operands result depends upon choice of
destination register. E.g. if we allow single register to be an rhs,
and if we try to move dx=ax(as rhs) through ax=dx, we'll result
in invalid insn dx=dx, so we'll loose this rhs here.
Just can't come up with significant testcase for this, so just
leaving it for now. Do not allow clobbering the address register of speculative
insns.
Referenced by create_speculation_check().
|
static |
Track bookkeeping copies created, insns scheduled, and blocks for rescheduling when INSN is found by move_op.
Even if this insn can be a copy that will be removed during current move_op,
we still need to count it as an originator. Note that original block needs to be rescheduled, as we pulled an
instruction out of it. For instructions we must immediately remove insn from the
stream, so subsequent update_data_sets () won't include this
insn into av_set.
For expr we must make insn look like "INSN_REG (insn) := c_expr".
|
static |
Try to look at bitmap caches for EXPR and INSN pair, return true if successful. When INSIDE_INSN_GROUP, also try ignore dependencies that can exist within a parallel group. Write to RES the resulting code for moveup_expr.
First check whether we've analyzed this situation already.
This is the only case when propagation result can change over time,
as we can dynamically switch off scheduling as RHS. In this case,
just check the flag to reach the correct decision.
|
static |
Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG. If BEST_REG is valid, replace LHS of EXPR with it.
Try whether we'll be able to generate the insn
'dest := best_reg' at the place of the original operation. Make sure that EXPR has the right destination
register.
References sel_create_recovery_block().
|
static |
Try to look at bitmap caches for EXPR and INSN pair, return true if successful. Write to RES the resulting code for moveup_expr.
This EXPR was already moved through this insn and was
changed as a result. Fetch the proper data from
the hashtable.
References moveup_expr_cached(), and MOVEUP_EXPR_NULL.
|
static |
Undo all transformations on *AV_PTR that were done when moving through INSN.
First, kill any EXPR that uses registers set by an insn. This is
required for correctness. When an insn looks like 'r1 = r1', we could substitute through
it, but the above condition will still hold. This happened with
gcc.c-torture/execute/961125-1.c. Undo transformations looking at the history vector.
Compute the difference between old and new speculative
statuses: that's what we need to check.
Earlier we used to assert that the status will really
change. This no longer works because only the probability
bits in the status may have changed during compute_av_set,
and in the case of merging different probabilities of the
same speculative status along different paths we do not
record this in the history vector. This happens when we're unsubstituting on a bookkeeping
copy, which was in turn substituted. The history is wrong
in this case. Do it the hard way.
References bitmap_bit_p(), cancel_changes(), copy_rtx(), emit_insn(), end_sequence(), extract_insn(), gen_reg_rtx(), ira_implicitly_set_insn_hard_regs(), max_reg_num(), max_regno, maybe_extend_reg_info_p(), preprocess_constraints(), sched_verbose, sel_print(), start_sequence(), validate_change(), and verify_changes().
|
static |
Update data sets for the bookkeeping block and record those expressions which become no longer available after inserting this bookkeeping.
First, get correct liveness in the bookkeeping block. The problem is
the range between the bookeeping insn and the end of block. If there's valid av_set on BOOK_BLOCK, then there might exist another
fence above, where we may choose to schedule an insn which is
actually blocked from moving up with the bookkeeping we create here. Traverse all the expressions in the old av_set and check whether
CUR_EXPR is in new AV_SET. In this case, we can just turn off the E_T_A bit, but we can't
represent this information with the current vector. Unfortunately, the below code could be also fired up on
separable insns, e.g. when moving insns through the new
speculation check as in PR 53701.
References fur_static_params::crosses_call, and fur_static_params::original_insns.
|
static |
Update bitmap caches on INSN with result RES of propagating EXPR.
Do not cache result of propagating jumps through an insn group,
as it is always true, which is not useful outside the group.
|
static |
Update boundary BND (and, if needed, FENCE) with INSN, remove the old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and return it.
|
static |
Update the data gathered in av and lv sets starting from INSN.
References av_set_iter_remove().
Referenced by move_exprs_to_boundary().
|
static |
Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL is nonzero if we need to stall after issuing INSN.
First, reflect that something is scheduled on this fence.
Set instruction scheduling info. This will be used in bundling,
pipelining, tick computations etc. This does not account for adjust_cost hooks, just add the biggest
constant the hook may add to the latency. TODO: make this
a target dependent constant. Change these fields last, as they're used above.
Indicate that we've scheduled something on this fence.
Print debug information when insn's fields are updated.
References moveop_static_params::c_expr, and cmpd_local_params::c_expr_merged.
|
inlinestatic |
Update liveness sets for INSN.
Referenced by code_motion_process_successors().
|
static |
Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is the highest seqno used in a region. Return the updated highest seqno.
Actually, new_hs is the seqno of the instruction, that was
scheduled first (i.e. it is the first one in SCHEDULED_INSNS). When not pipelining, purge unneeded insn info on the scheduled insns.
For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
require > 1GB of memory e.g. on limit-fnargs.c.
Referenced by sel_region_init().
|
static |
Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN and transformation type TRANS_TYPE.
|
static |
True when target of EXPR is available due to EXPR_TARGET_AVAILABLE, USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS.
When target is not available, it may be due to hard register
restrictions, e.g. crosses calls, so we check hard_available too. Check only if we haven't scheduled something on the previous fence,
cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
and having more than one fence, we may end having targ_un in a block
in which successors target register is actually available.
The last condition handles the case when a dependence from a call insn
was created in sched-deps.c for insns with destination registers that
never crossed a call before, but do cross one after our code motion.
FIXME: in the latter case, we just uselessly called find_used_regs,
because we can't move this expression with any other register
as well.
|
static |
Add the vinsn of EXPR to the VINSN_VEC.
References ready_list::n_ready, and ready.
Referenced by move_exprs_to_boundary().
|
static |
Clear VINSN_VEC and detach vinsns.
|
static |
Free the vector representing blocked expressions.
|
static |
Lookup EXPR in VINSN_VEC and return TRUE if found. Also check patterns from EXPR's history of changes.
Start with checking expr itself and then proceed with all the old forms
of expr taken from its history vector. For non-separable instructions, the blocking insn can have
another pattern due to substitution, and we can't choose
different register as in the above case. Check all registers
being written instead.
|
static |
Returns whether VI writes either one of the USED_REGS registers or, if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers.
|
static |
Set of basic blocks that are forced to start new ebbs. This is a subset of all the ebb heads.
| bitmap blocks_to_reschedule = NULL |
Blocks that need to be rescheduled after pipelining.
| bool bookkeeping_p |
True if bookkeeping is enabled.
|
static |
Whether we can issue more instructions.
| struct code_motion_path_driver_info_def* code_motion_path_driver_info |
Global pointer to current hooks, either points to MOVE_OP_HOOKS or FUR_HOOKS.
|
static |
This bitmap marks the blocks visited by code_motion_path_driver so we don't visit them afterwards.
|
static |
Functions that work with regions.
Current number of seqno used in init_seqno and init_seqno_1.
|
static |
|
static |
These bitmaps record original instructions scheduled on the current iteration and bookkeeping copies created by them.
|
static |
True when separable insns should be scheduled as RHSes.
Referenced by moving_insn_creates_bookkeeping_block_p().
| flist_t fences |
Current fences.
Referenced by has_preds_in_current_region_p().
|
static |
All newly emitted insns will have their uids greater than this value.
Referenced by code_motion_process_successors().
| bitmap_head* forced_ebb_heads = &_forced_ebb_heads |
Used in bb_in_ebb_p.
| struct code_motion_path_driver_info_def fur_hooks |
Set of hooks for performing move_op and find_used_regs routines with code_motion_path_driver.
Hooks and data to perform find_used_regs operations with code_motion_path_driver.
| int global_level |
GLOBAL_LEVEL is used to discard information stored in basic block headers av_sets. Av_set of bb header is valid if its (bb header's) level is equal to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance scheduling window.
Referenced by equal_after_moveup_path_p().
|
static |
True when the first lv set should be ignored when updating liveness.
| int max_insns_to_rename |
Maximum number of insns that are eligible for renaming.
|
static |
Number of insns max_issue has initialized data structures for.
Referenced by av_set_could_be_blocked_by_bookkeeping_p().
|
static |
Records the maximal UID before moving up an instruction. Used for distinguishing between bookkeeping copies and original insns.
|
static |
Maximum software lookahead window size, reduced when rescheduling after pipelining.
Referenced by equal_after_moveup_path_p().
| struct code_motion_path_driver_info_def move_op_hooks |
Hooks and data to perform move_op operations with code_motion_path_driver.
|
static |
Number of insns scheduled in current region.
Referenced by sel_region_init().
| bool pipelining_p |
@verbatim
Instruction scheduling pass. Selective scheduler and pipeliner. Copyright (C) 2006-2013 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see http://www.gnu.org/licenses/.
Implementation of selective scheduling approach.
The below implementation follows the original approach with the following
changes:
o the scheduler works after register allocation (but can be also tuned
to work before RA);
o some instructions are not copied or register renamed;
o conditional jumps are not moved with code duplication;
o several jumps in one parallel group are not supported;
o when pipelining outer loops, code motion through inner loops
is not supported;
o control and data speculation are supported;
o some improvements for better compile time/performance were made.
Terminology
===========
A vinsn, or virtual insn, is an insn with additional data characterizing
insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
Vinsns also act as smart pointers to save memory by reusing them in
different expressions. A vinsn is described by vinsn_t type.
An expression is a vinsn with additional data characterizing its properties
at some point in the control flow graph. The data may be its usefulness,
priority, speculative status, whether it was renamed/subsituted, etc.
An expression is described by expr_t type.
Availability set (av_set) is a set of expressions at a given control flow
point. It is represented as av_set_t. The expressions in av sets are kept
sorted in the terms of expr_greater_p function. It allows to truncate
the set while leaving the best expressions.
A fence is a point through which code motion is prohibited. On each step,
we gather a parallel group of insns at a fence. It is possible to have
multiple fences. A fence is represented via fence_t.
A boundary is the border between the fence group and the rest of the code.
Currently, we never have more than one boundary per fence, as we finalize
the fence group when a jump is scheduled. A boundary is represented
via bnd_t.
High-level overview
===================
The scheduler finds regions to schedule, schedules each one, and finalizes.
The regions are formed starting from innermost loops, so that when the inner
loop is pipelined, its prologue can be scheduled together with yet unprocessed
outer loop. The rest of acyclic regions are found using extend_rgns:
the blocks that are not yet allocated to any regions are traversed in top-down
order, and a block is added to a region to which all its predecessors belong;
otherwise, the block starts its own region.
The main scheduling loop (sel_sched_region_2) consists of just
scheduling on each fence and updating fences. For each fence,
we fill a parallel group of insns (fill_insns) until some insns can be added.
First, we compute available exprs (av-set) at the boundary of the current
group. Second, we choose the best expression from it. If the stall is
required to schedule any of the expressions, we advance the current cycle
appropriately. So, the final group does not exactly correspond to a VLIW
word. Third, we move the chosen expression to the boundary (move_op)
and update the intermediate av sets and liveness sets. We quit fill_insns
when either no insns left for scheduling or we have scheduled enough insns
so we feel like advancing a scheduling point.
Computing available expressions
===============================
The computation (compute_av_set) is a bottom-up traversal. At each insn,
we're moving the union of its successors' sets through it via
moveup_expr_set. The dependent expressions are removed. Local
transformations (substitution, speculation) are applied to move more
exprs. Then the expr corresponding to the current insn is added.
The result is saved on each basic block header.
When traversing the CFG, we're moving down for no more than max_ws insns.
Also, we do not move down to ineligible successors (is_ineligible_successor),
which include moving along a back-edge, moving to already scheduled code,
and moving to another fence. The first two restrictions are lifted during
pipelining, which allows us to move insns along a back-edge. We always have
an acyclic region for scheduling because we forbid motion through fences.
Choosing the best expression
============================
We sort the final availability set via sel_rank_for_schedule, then we remove
expressions which are not yet ready (tick_check_p) or which dest registers
cannot be used. For some of them, we choose another register via
find_best_reg. To do this, we run find_used_regs to calculate the set of
registers which cannot be used. The find_used_regs function performs
a traversal of code motion paths for an expr. We consider for renaming
only registers which are from the same regclass as the original one and
using which does not interfere with any live ranges. Finally, we convert
the resulting set to the ready list format and use max_issue and reorder*
hooks similarly to the Haifa scheduler.
Scheduling the best expression
==============================
We run the move_op routine to perform the same type of code motion paths
traversal as in find_used_regs. (These are working via the same driver,
code_motion_path_driver.) When moving down the CFG, we look for original
instruction that gave birth to a chosen expression. We undo
the transformations performed on an expression via the history saved in it.
When found, we remove the instruction or leave a reg-reg copy/speculation
check if needed. On a way up, we insert bookkeeping copies at each join
point. If a copy is not needed, it will be removed later during this
traversal. We update the saved av sets and liveness sets on the way up, too.
Finalizing the schedule
=======================
When pipelining, we reschedule the blocks from which insns were pipelined
to get a tighter schedule. On Itanium, we also perform bundling via
the same routine from ia64.c.
Dependence analysis changes
===========================
We augmented the sched-deps.c with hooks that get called when a particular
dependence is found in a particular part of an insn. Using these hooks, we
can do several actions such as: determine whether an insn can be moved through
another (has_dependence_p, moveup_expr); find out whether an insn can be
scheduled on the current cycle (tick_check_p); find out registers that
are set/used/clobbered by an insn and find out all the strange stuff that
restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
init_global_and_expr_for_insn).
Initialization changes
======================
There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
reused in all of the schedulers. We have split up the initialization of data
of such parts into different functions prefixed with scheduler type and
postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
The same splitting is done with current_sched_info structure:
dependence-related parts are in sched_deps_info, common part is in
common_sched_info, and haifa/sel/etc part is in current_sched_info.
Target contexts
===============
As we now have multiple-point scheduling, this would not work with backends
which save some of the scheduler state to use it in the target hooks.
For this purpose, we introduce a concept of target contexts, which
encapsulate such information. The backend should implement simple routines
of allocating/freeing/setting such a context. The scheduler calls these
as target hooks and handles the target context as an opaque pointer (similar
to the DFA state type, state_t).
Various speedups
================
As the correct data dependence graph is not supported during scheduling (which
is to be changed in mid-term), we cache as much of the dependence analysis
results as possible to avoid reanalyzing. This includes: bitmap caches on
each insn in stream of the region saying yes/no for a query with a pair of
UIDs; hashtables with the previously done transformations on each insn in
stream; a vector keeping a history of transformations on each expr.
Also, we try to minimize the dependence context used on each fence to check
whether the given expression is ready for scheduling by removing from it
insns that are definitely completed the execution. The results of
tick_check_p checks are also cached in a vector on each fence.
We keep a valid liveness set on each insn in a region to avoid the high
cost of recomputation on large basic blocks.
Finally, we try to minimize the number of needed updates to the availability
sets. The updates happen in two cases: when fill_insns terminates,
we advance all fences and increase the stage number to show that the region
has changed and the sets are to be recomputed; and when the next iteration
of a loop in fill_insns happens (but this one reuses the saved av sets
on bb headers.) Thus, we try to break the fill_insns loop only when
"significant" number of insns from the current scheduling window was
scheduled. This should be made a target param.
TODO: correctly support the data dependence graph at all stages and get rid
of all caches. This should speed up the scheduler.
TODO: implement moving cond jumps with bookkeeping copies on both targets.
TODO: tune the scheduler before RA so it does not create too much pseudos.
References:
S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
selective scheduling and software pipelining.
ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
for GCC. In Proceedings of GCC Developers' Summit 2006.
Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
http://rogue.colorado.edu/EPIC7/. True when pipelining is enabled.
Referenced by choose_best_insn(), and compute_live_below_insn().
|
static |
Indicates the number of times renaming happened before the current one.
Referenced by invoke_reorder_hooks().
|
static |
reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the best register more recently than REG2.
| int sched_emulate_haifa_p |
True if/when we want to emulate Haifa scheduler in the common code. This is used in sched_rgn_local_init and in various places in sched-deps.c.
|
static |
Used in verify_target_availability to assert that target reg is reported unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if we haven't scheduled anything on the previous fence. if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can have more conservative value than the one returned by the find_used_regs, thus we shouldn't assert that these values are equal.
|
static |
A global structure that contains the needed information about harg regs.
|
static |
Variables to accumulate different statistics.
The number of bookkeeping copies created.
Referenced by sel_region_init().
|
static |
The number of insns that required bookkeeiping for their scheduling.
Referenced by sel_region_init().
|
static |
The number of insns that got renamed.
Referenced by find_place_for_bookkeeping(), and sel_region_init().
|
static |
The number of substitutions made during scheduling.
Referenced by find_place_for_bookkeeping(), and sel_region_init().
|
static |
This vector has the exprs which may still present in av_sets, but actually can't be moved up due to bookkeeping created during code motion to another fence. See comment near the call to update_and_record_unavailable_insns for the detailed explanations.
|
static |
This vector has vinsns which are scheduled with renaming on the first fence and then seen on the second. For expressions with such vinsns, target availability information may be wrong.
Vector to store temporary nops inserted in move_op to prevent removal of empty bbs.
|
static |
True when a conflict on a target register was found during moveup_expr.
1.8.1.1