GCC Middle and Back End API Reference

Data Structures  
struct  reg_stat_struct 
struct  insn_link 
struct  undo 
struct  undobuf 
struct  likely_spilled_retval_info 
Typedefs  
typedef struct reg_stat_struct  reg_stat_type 
Enumerations  
enum  undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS } 
typedef struct reg_stat_struct reg_stat_type 
enum undo_kind 

static 
Adjust INSN after we made a change to its destination. Changing the destination can invalidate notes that say something about the results of the insn and a LOG_LINK pointing to the insn.
For notes, be conservative and simply remove them.
The new insn will have a destination that was previously the destination of an insn just above it. Call distribute_links to make a LOG_LINK from the next use of that destination.

staticread 
Allocate a link.
References UNDO_INT, UNDO_LINKS, UNDO_MODE, and UNDO_RTX.
Referenced by create_log_links().

static 
See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) if so.
Distributivity is not true for floating point as it can change the value. So we don't do it unless funsafemathoptimizations.
The outer operation can only be one of the following:
If either operand is a primitive we can't do anything, so get out fast.
See if the inner and outer operations distribute.
These all distribute except over PLUS.
This is also a multiply, so it distributes over everything.
This used to handle SUBREG, but this turned out to be counter productive, since (subreg (op ...)) usually is not handled by insn patterns, and this "optimization" therefore transformed recognizable patterns into unrecognizable ones. Therefore the SUBREG case was removed from here. It is possible that distributing SUBREG over arithmetic operations leads to an intermediate result than can then be optimized further, e.g. by moving the outer SUBREG to the other side of a SET as done in simplify_set. This seems to have been the original intent of handling SUBREGs here. However, with current GCC this does not appear to actually happen, at least on major platforms. If some case is found where removing the SUBREG case here prevents followon optimizations, distributing SUBREGs ought to be readded at that place, e.g. in simplify_set.
Set LHS and RHS to the inner operands (A and B in the example above) and set OTHER to the common operand (C in the example). There is only one way to do this unless the inner operation is commutative.
Form the new inner operation, seeing if it simplifies first.
There is one exception to the general way of distributing: (a  c) ^ (b  c) > (a ^ b) & ~c
We may be able to continuing distributing the result, so call ourselves recursively on the inner operation before forming the outer operation, which we return.

static 
Return TRUE if combine can reuse reg X in mode MODE. ADDED_SETS is nonzero if the original set is still required.
Allow hard registers if the new mode is legal, and occupies no more registers than the old mode.
Or a pseudo that is only used once.

static 
See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are optionally insns that were previously combined into I3 or that will be combined into the merger of INSN and I3. The order is PRED, PRED2, INSN, SUCC, SUCC2, I3. Return 0 if the combination is not allowed for any reason. If the combination is allowed, *PDEST will be set to the single destination of INSN and *PSRC to the single source, and this function will return 1.
Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. or a PARALLEL consisting of such a SET and CLOBBERs. If INSN has CLOBBER parallel parts, ignore them for our processing. By definition, these happen during the execution of the insn. When it is merged with another insn, all bets are off. If they are, in fact, needed and aren't also supplied in I3, they may be added by recog_for_combine. Otherwise, it won't match. We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED note. Get the source and destination of INSN. If more than one, can't combine.
This is important to combine floating point insns for the SH4 port.
Combining an isolated USE doesn't make sense. We depend here on combinable_i3pat to reject them.
The code below this loop only verifies that the inputs of the SET in INSN do not change. We call reg_set_between_p to verify that the REG in the USE does not change between I3 and INSN. If the USE in INSN was for a pseudo register, the matching insn pattern will likely match any register; combining this with any other USE would only be safe if we knew that the used registers have identical values, or if there was something to tell them apart, e.g. different modes. For now, we forgo such complicated tests and simply disallow combining of USES of pseudo registers with any other USE.
We can ignore CLOBBERs.
Ignore SETs whose result isn't used but not those that have sideeffects.
If we have already found a SET, this is a second one and so we cannot combine with this insn.
Anything else means we can't combine.
If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, so don't do anything with it.
The simplification in expand_field_assignment may call back to get_last_value, so set safe guard here.
Don't eliminate a store in the stack pointer.
Don't combine with an insn that sets a register to itself if it has a REG_EQUAL note. This may be part of a LIBCALL sequence.
Can't merge an ASM_OPERANDS.
Can't merge a function call.
Don't eliminate a function call argument.
Don't substitute into an incremented register.
Don't substitute into a nonlocal goto, this confuses CFG.
Make sure that DEST is not used after SUCC but before I3.
Make sure that the value that is to be substituted for the register does not use any registers whose values alter in between. However, If the insns are adjacent, a use can't cross a set even though we think it might (this can happen for a sequence of insns each setting the same destination; last_set of that register might point to a NOTE). If INSN has a REG_EQUIV note, the register is always equivalent to the memory so the substitution is valid even if there are intervening stores. Also, don't move a volatile asm or UNSPEC_VOLATILE across any other insns.
Don't combine across a CALL_INSN, because that would possibly change whether the life span of some REGs crosses calls or not, and it is a pain to update that information. Exception: if source is a constant, moving it later can't hurt. Accept that as a special case.
DEST must either be a REG or CC0.
If register alignment is being enforced for multiword items in all cases except for parameters, it is possible to have a register copy insn referencing a hard register that is not allowed to contain the mode being copied and which would not be valid as an operand of most insns. Eliminate this problem by not combining with such an insn. Also, on some machines we don't want to extend the life of a hard register.
Don't extend the life of a hard register unless it is user variable (if we have few registers) or it can't fit into the desired register (meaning something special is going on). Also avoid substituting a return register into I3, because reload can't handle a conflict with constraints of other inputs.
Don't substitute for a register intended as a clobberable operand.
If the clobber represents an earlyclobber operand, we must not substitute an expression containing the clobbered register. As we do not analyze the constraint strings here, we have to make the conservative assumption. However, if the register is a fixed hard reg, the clobber cannot represent any operand; we leave it up to the machine description to either accept or reject useandclobber patterns.
If INSN contains anything volatile, or is an `asm' (whether volatile or not), reject, unless nothing volatile comes between it and I3
Make sure neither succ nor succ2 contains a volatile reference.
We'll check insns between INSN and I3 below.
If INSN is an asm, and DEST is a hard register, reject, since it has to be an explicit register variable, and was chosen for a reason.
If INSN contains volatile references (specifically volatile MEMs), we cannot combine across any other volatile references. Even if INSN doesn't contain volatile references, any intervening volatile insn might affect machine state.
If INSN contains an autoincrement or autodecrement, make sure that register is not used between there and I3, and not already used in I3 either. Neither must it be used in PRED or SUCC, if they exist. Also insist that I3 not be a jump; if it were one and the incremented register were spilled, we would lose.
Don't combine an insn that follows a CC0setting insn. An insn that uses CC0 must not be separated from the one that sets it. We do, however, allow I2 to follow a CC0setting insn if that insn is passed as I1; in that case it will be deleted also. We also allow combining in this case if all the insns are adjacent because that would leave the two CC0 insns adjacent as well. It would be more logical to test whether CC0 occurs inside I1 or I2, but that would be much slower, and this ought to be equivalent.
If we get here, we have passed all the tests and the combination is to be allowed.

static 
If X refers to a register that equals REG in value, replace these references with REG.
fall through

static 

static 
Determine whether INSN can be used in a combination. Return nonzero if not. This is used in try_combine to detect early some cases where we can't perform combinations.
If this isn't really an insn, we can't do anything. This can occur when flow deletes an insn that it has merged into an autoincrement address.
Never combine loads and stores involving hard regs that are likely to be spilled. The register allocator can usually handle such regreg moves by tying. If we allow the combiner to make substitutions of likelyspilled regs, reload might die. As an exception, we allow combinations involving fixed regs; these are not available to the register allocator so there's no risk involved.

static 
Scan X for promoted SUBREGs. For each one found, note what it implies to the registers used in it.

static 
LOC is the location within I3 that contains its pattern or the component of a PARALLEL of the pattern. We validate that it is valid for combining. One problem is if I3 modifies its output, as opposed to replacing it entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as doing so would produce an insn that is not equivalent to the original insns. Consider: (set (reg:DI 101) (reg:DI 100)) (set (subreg:SI (reg:DI 101) 0) <foo>) This is NOT equivalent to: (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) (set (reg:DI 101) (reg:DI 100))]) Not only does this modify 100 (in which case it might still be valid if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. We can also run into a problem if I2 sets a register that I1 uses and I1 gets directly substituted into I3 (not via I2). In that case, we would be getting the wrong value of I2DEST into I3, so we must reject the combination. This case occurs when I2 and I1 both feed into I3, rather than when I1 feeds into I2, which feeds into I3. If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source of a SET must prevent combination from occurring. The same situation can occur for I0, in which case I0_NOT_IN_SRC is set. Before doing the above check, we first try to expand a field assignment into a set of logical operations. If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which we place a register that is both set and used within I3. If more than one such register is detected, we fail. Return 1 if the combination is valid, zero otherwise.
Check for the case where I3 modifies its output, as discussed above. We don't want to prevent pseudos from being combined into the address of a MEM, so only prevent the combination if i1 or i2 set the same MEM.
This is the same test done in can_combine_p except we can't test all_adjacent; we don't have to, since this instruction will stay in place, thus we are not considering increasing the lifetime of INNER_DEST. Also, if this insn sets a function argument, combining it with something that might need a spill could clobber a previous function argument; the all_adjacent test in can_combine_p also checks this; here, we do a more specific test for this case.
If DEST is used in I3, it is being killed in this insn, so record that for later. We have to consider paradoxical subregs here, since they kill the whole register, but we ignore partial subregs, STRICT_LOW_PART, etc. Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the STACK_POINTER_REGNUM, since these are always considered to be live. Similarly for ARG_POINTER_REGNUM if it is fixed.
References targetm.

static 
Main entry point for combiner. F is the first insn of the function. NREGS is the first unused pseudoreg number. Return nonzero if the combiner has turned an indirect jump instruction into a direct jump.
Allocate array for insn info.
Don't use reg_stat[].nonzero_bits when computing it. This can cause problems when, for example, we have j <<= 1 in a loop.
Scan all SETs and see if we can deduce anything about what bits are known to be zero for some registers and how many copies of the sign bit are known to exist for those registers. Also set any known values so that we can use it while searching for what bits are known to be set.
Allow the entry block and the first block to fall into the same EBB. Conceptually the incoming promotions are assigned to the entry block.
Record the current insn_rtx_cost of this instruction.
Now scan all the insns in forward order.
See if we know about function return values before this insn based upon SUBREG flags.
See if we can find hardregs and subreg of pseudos in narrower modes. This could help turning TRUNCATEs into SUBREGs.
Try this insn with each insn it links back to.
Try each sequence of three linked insns ending with this one.
If the linked insn has been replaced by a note, then there is no point in pursuing this chain any further.
Try to combine a jump insn that uses CC0 with a preceding insn that sets CC0, and maybe with its logical predecessor as well. This is how we make decrementandbranch insns. We need this special code because data flow connections via CC0 do not get entered in LOG_LINKS.
Do the same for an insn that explicitly references CC0.
Finally, see if any of the insns that this insn links to explicitly references CC0. If so, try this insn, that insn, and its predecessor if it sets CC0.
Try combining an insn with two different insns whose results it uses.
Try fourinstruction combinations.
If the linked insn has been replaced by a note, then there is no point in pursuing this chain any further.
I0 > I1 > I2 > I3.
I0, I1 > I2, I2 > I3.
I0 > I2; I1, I2 > I3.
I0 > I1; I1, I2 > I3.
Try this insn with each REG_EQUAL note it links back to.
Avoid using a register that may already been marked dead by an earlier instruction.
Temporarily replace the set's source with the contents of the REG_EQUAL note. The insn will be deleted or recognized by try_combine.
Clean up.
Make recognizer allow volatile MEMs again.

static 
Simplify X, a piece of RTL. We just operate on the expression at the outer level; call `subst' to simplify recursively. Return the new expression. OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level of a condition.
If this is a commutative operation, put a constant last and a complex expression first. We don't need to do this for comparisons here.
If this is a simple operation applied to an IF_THEN_ELSE, try applying it to the arms of the IF_THEN_ELSE. This often simplifies things. Check for cases where both arms are testing the same condition. Don't do anything if all operands are very simple.
If everything is a comparison, what we have is highly unlikely to be simpler, so don't use it.
Simplify the alternative arms; this may collapse the true and false arms to storeflag values. Be careful to use copy_rtx here since true_rtx or false_rtx might share RTL with x as a result of the if_then_else_cond call above.
If true_rtx and false_rtx are not general_operands, an if_then_else is unlikely to be simpler.
Restarting if we generate a storeflag expression will cause us to loop. Just drop through in this case.
If the result values are STORE_FLAG_VALUE and zero, we can just make the comparison operation.
Likewise, we can make the negate of a comparison operation if the result values are  STORE_FLAG_VALUE and zero.
Try to fold this expression in case we have constants that weren't present before.
First see if we can apply the inverse distributive law.
If CODE is an associative operation not otherwise handled, see if we can associate some operands. This can win if they are constants or if they are logically related (i.e. (a & b) & a).
Make sure we pass the constant operand if any as the second one if this is a commutative operation.
For commutative operations, try the other pair if that one didn't simplify.
A little bit of algebraic simplification here.
Ensure that our address has any ASHIFTs converted to MULT in case addressrecognizing predicates are called later.
See if this can be moved to simplify_subreg.
Don't call gen_lowpart if the inner mode is VOIDmode and we cannot simplify it, as SUBREG without inner mode is invalid.
If op is known to have all lower bits zero, the result is zero.
Don't change the mode of the MEM if that would change the meaning of the address.
Note that we cannot do any narrowing for nonconstants since we might have been counting on using the fact that some bits were zero. We now do this in the SET.
For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be replaced by (lshiftrt X C). This will convert (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).
If X has only a single bit that might be nonzero, say, bit I, convert (neg X) to (ashiftrt (ashift X CI) CI) where C is the bitsize of MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to (sign_extract X 1 Y). But only do this if TEMP isn't a register or a SUBREG of one since we'd be making the expression more complex if it was just a register.
If all we did was surround TEMP with the two shifts, we haven't improved anything, so don't use it. Otherwise, we are better off with TEMP1.
We can't handle truncation to a partial integer mode here because we don't know the real bitsize of the partial integer mode.
We can truncate a constant value and return it.
Similarly to what we do in simplifyrtx.c, a truncate of a register whose value is a comparison can be replaced with a subreg if STORE_FLAG_VALUE permits.
(const (const X)) can become (const X). Do it this way rather than returning the inner CONST since CONST can be shared with a REG_EQUAL note.
Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we can add in an offset. find_split_point will split this address up again if it doesn't match.
(plus (xor (and <foo> (const_int pow2  1)) <c>) <c>) when c is (const_int (pow2 + 1) / 2) is a sign extension of a bitfield and can be replaced by either a sign_extend or a sign_extract. The `and' may be a zero_extend and the two <c>, <c> constants may be reversed.
If only the loworder bit of X is possibly nonzero, (plus x 1) can become (ashiftrt (ashift (xor x 1) C) C) where C is the bitsize of the mode  1. This allows simplification of "a = (b & 8) == 0;"
If we are adding two things that have no bits in common, convert the addition into an IOR. This will often be further simplified, for example in cases like ((a & 1) + (a & 2)), which can become a & 3.
Try to simplify the expression further.
If we could, great. If not, do not go ahead with the IOR replacement, since PLUS appears in many special purpose address arithmetic instructions.
(minus <foo> (and <foo> (const_int pow2))) becomes (and <foo> (const_int pow21))
If we have (mult (plus A B) C), apply the distributive law and then the inverse distributive law to see if things simplify. This occurs mostly in addresses, often when unrolling loops.
Try simplify a*(b/c) as (a*b)/c.
If this is a divide by a power of two, treat it as a shift if its first operand is a shift.
If the first operand is a condition code, we can't do anything with it.
Simplify our comparison, if possible.
If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X if only the loworder bit is possibly nonzero in X (such as when X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to (xor X 1) or (minus 1 X); we use the former. Finally, if X is known to be either 0 or 1, NE becomes a NEG and EQ becomes (plus X 1). Remove any ZERO_EXTRACT we made when thinking this was a comparison. It may now be simpler to use, e.g., an AND. If a ZERO_EXTRACT is indeed appropriate, it will be placed back by the call to make_compound_operation in the SET case. Don't apply these optimizations if the caller would prefer a comparison rather than a value. E.g., for the condition in an IF_THEN_ELSE most targets need an explicit comparison.
If STORE_FLAG_VALUE is 1, we have cases similar to those above.
If X is 0/1, (eq X 0) is X1.
If STORE_FLAG_VALUE says to just test the sign bit and X has just one bit that might be nonzero, we can convert (ne x 0) to (ashift x c) where C puts the bit in the sign bit. Remove any AND with STORE_FLAG_VALUE when we are done, since we are only going to test the sign bit.
If the code changed, return a whole new comparison. We also need to avoid using SUBST in cases where simplify_comparison has widened a comparison with a CONST_INT, since in that case the wider CONST_INT may fail the sanity checks in do_SUBST.
Otherwise, keep this operation, but maybe change its operands. This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).
If we are processing SET_DEST, we are done.
If this is a shift by a constant amount, simplify it.

static 
Try to split PATTERN found in INSN. This returns NULL_RTX if PATTERN can not be split. Otherwise, it returns an insn sequence. This is a wrapper around split_insns which ensures that the reg_stat vector is made larger if the splitter creates a new register.

static 
Subroutine of try_combine. Determine whether the replacement patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. Return false if the cost of all the instructions can be estimated and the replacements are more expensive than the original sequence.
Lookup the original insn_rtx_costs.
Calculate the replacement insn_rtx_costs.
Disallow this combination if both new_cost and old_cost are greater than zero, and new_cost is greater than old cost.
Update the uid_insn_cost array with the replacement costs.

static 

static 
Return 1 if X is an arithmetic expression that contains a multiplication and division. We don't count multiplications by powers of two here.

static 
Utility function for record_value_for_reg. Count number of rtxs in X.

static 
Fill in log links field for all insns.
Pass through each block from the end, recording the uses of each register and establishing log links when def is encountered. Note that we do not clear next_use array in order to save time, so we have to test whether the use is in the same basic block as def. There are a few cases below when we do not consider the definition or usage  these are taken from original flow.c did. Don't ask me why it is done this way; I don't know and if it works, I don't want to know.
Log links are created only once.
Do not consider if it is pre/post modification in MEM.
Do not make the log link for frame pointer.
flow.c claimed: We don't build a LOG_LINK for hard registers contained in ASM_OPERANDs. If these registers get replaced, we might wind up changing the semantics of the insn, even if reload can make what appear to be valid assignments later.
Don't add duplicate links between instructions.
Do not consider the usage of the stack pointer by function call.
References alloc_insn_link(), and insn_link::insn.

static 
Delete any insns that copy a register to itself.

static 
See if X is of the form (* (+ A B) C), and if so convert to (+ (* A C) (* B C)) and try to simplify. Most of the time, this results in no change. However, if some of the operands are the same or inverses of each other, simplifications will result. For example, (and (ior A B) (not B)) can occur as the result of expanding a bit field assignment. When we apply the distributive law to this, we get (ior (and (A (not B))) (and (B (not B)))), which then simplifies to (and (A (not B))). Note that no checks happen on the validity of applying the inverse distributive law. This is pointless since we can do it in the few places where this routine is called. N is the index of the term that is decomposed (the arithmetic operation, i.e. (+ A B) in the first example above). !N is the index of the term that is distributed, i.e. of C in the first example above.
Distributivity is not true for floating point as it can change the value. So we don't do it unless funsafemathoptimizations.
Special case (and (xor B C) (not A)), which is equivalent to (xor (ior A B) (ior A C))
Distribute the second term.
Distribute the first term.
References expand_compound_operation(), mode_dependent_address_p(), mode_for_size(), and subreg_lowpart_p().

static 

static 
Similarly to above, distribute the LOG_LINKS that used to be present on I3, I2, and I1 to new locations. This is also called to add a link pointing at I3 when I3's destination is changed.
If the insn that this link points to is a NOTE or isn't a single set, ignore it. In the latter case, it isn't clear what we can do other than ignore the link, since we can't tell which register it was for. Such links wouldn't be used by combine anyway. It is not possible for the destination of the target of the link to have been changed by combine. The only potential of this is if we replace I3, I2, and I1 by I3 and I2. But in that case the destination of I2 also remains unchanged.
A LOG_LINK is defined as being placed on the first insn that uses a register and points to the insn that sets the register. Start searching at the next insn after the target of the link and stop when we reach a set of the register or the end of the basic block. Note that this correctly handles the link that used to point from I3 to I2. Also note that not much searching is typically done here since most links don't point very far away.
If we found a place to put the link, place it there unless there is already a link to the same insn as LINK at that point.
Set added_links_insn to the earliest insn we added a link to.

static 
Given a chain of REG_NOTES originally from FROM_INSN, try to place them as appropriate. I3 and I2 are the insns resulting from the combination insns including FROM (I2 may be zero). ELIM_I2 and ELIM_I1 are either zero or registers that we know will not need REG_DEAD notes because they are being substituted for. This saves searching in the most common cases. Each note in the list is either ignored or placed on some insns, depending on the type of note.
Doesn't matter much where we put this, as long as it's somewhere. It is preferable to keep these notes on branches, which is most likely to be i3.
These notes must remain with the call or trapping instruction.
??? Otherwise assume we've combined things such that we can now prove that the instructions can't trap. Drop the note in this case.
??? How to distribute between i3i1. Assume i3 contains the entire adjustment. Assert i3 contains at least some adjust.
fixup_args_size_notes looks at REG_NORETURN note, so ensure the note is placed there first.
emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS REG_ARGS_SIZE note to all noreturn calls, allow that here.
These notes must remain with the call. It should not be possible for both I2 and I3 to be a call.
Any clobbers for i3 may still exist, and so we must process REG_UNUSED notes from that insn. Any clobbers from i2 or i1 can only exist if they were added by recog_for_combine. In that case, recog_for_combine created the necessary REG_UNUSED notes. Trying to keep any original REG_UNUSED notes from these insns can cause incorrect output if it is for the same register as the original i3 dest. In that case, we will notice that the register is set in i3, and then add a REG_UNUSED note for the destination of i3, which is wrong. However, it is possible to have REG_UNUSED notes from i2 or i1 for register which were both used and clobbered, so we keep notes from i2 or i1 if they will turn into REG_DEAD notes.
If this register is set or clobbered in I3, put the note there unless there is one already.
Otherwise, if this register is used by I3, then this register now dies here, so we must put a REG_DEAD note here unless there is one already.
These notes say something about results of an insn. We can only support them if they used to be on I3 in which case they remain on I3. Otherwise they are ignored. If the note refers to an expression that is not a constant, we must also ignore the note since we cannot tell whether the equivalence is still true. It might be possible to do slightly better than this (we only have a problem if I2DEST or I1DEST is present in the expression), but it doesn't seem worth the trouble.
These notes say something about how a register is used. They must be present on any use of the register in I2 or I3.
This can show up in several ways  either directly in the pattern, or hidden off in the constant pool with (or without?) a REG_EQUAL note.
??? Ignore the withoutreg_equalnote problem for now.
For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note as a JUMP_LABEL or decrement LABEL_NUSES if it's already there.
This note says something about the value of a register prior to the execution of an insn. It is too much trouble to see if the note is still correct in all situations. It is better to simply delete it.
If we replaced the right hand side of FROM_INSN with a REG_EQUAL note, the original use of the dying register will not have been combined into I3 and I2. In such cases, FROM_INSN is guaranteed to be the first of the combined instructions, so we simply need to search back before FROM_INSN for the previous use or set of this register, then alter the notes there appropriately. If the register is used as an input in I3, it dies there. Similarly for I2, if it is nonzero and adjacent to I3. If the register is not used as an input in either I3 or I2 and it is not one of the registers we were supposed to eliminate, there are two possibilities. We might have a nonadjacent I2 or we might have somehow eliminated an additional register from a computation. For example, we might have had A & B where we discover that B will always be zero. In this case we will eliminate the reference to A. In both cases, we must search to see if we can find a previous use of A and put the death note there.
If the register is being set at TEM, see if that is all TEM is doing. If so, delete TEM. Otherwise, make this into a REG_UNUSED note instead. Don't delete sets to global register vars.
Verify that it was the set, and not a clobber that modified the register. CC0 targets must be careful to maintain setter/user pairs. If we cannot delete the setter due to side effects, mark the user with an UNUSED note instead of deleting it.
Move the notes and links of TEM elsewhere. This might delete other dead insns recursively. First set the pattern to something that won't use any register.
Delete the setter too.
If there isn't already a REG_UNUSED note, put one here. Do not place a REG_DEAD note, even if the register is also used here; that would not match the algorithm used in lifetime analysis and can cause the consistency check in the scheduler to fail.
If we are doing a 3>2 combination, and we have a register which formerly died in i3 and was not used by i2, which now no longer dies in i3 and is used in i2 but does not die in i2, and place is between i2 and i3, then we may need to move a link from place to i2.
If the register is set or already dead at PLACE, we needn't do anything with this note if it is still a REG_DEAD note. We check here if it is set at all, not if is it totally replaced, which is what `dead_or_set_p' checks, so also check for it being set partially.
Unless the register previously died in PLACE, clear last_death. [I no longer understand why this is being done.]
If this is a death note for a hard reg that is occupying multiple registers, ensure that we are still using all parts of the object. If we find a piece of the object that is unused, we must arrange for an appropriate REG_DEAD note to be added for it. However, we can't just emit a USE and tag the note to it, since the register might actually be dead; so we recourse, and the recursive call then finds the previous insn that used this register.
Put only REG_DEAD notes for pieces that are not already dead or set.
Any other notes should not be present at this point in the compilation.
Referenced by use_crosses_set_p().

static 
Substitute NEWVAL, an rtx expression, into INTO, a place in some insn. The substitution can be undone by undo_all. If INTO is already set to NEWVAL, do not record this change. Because computing NEWVAL might also call SUBST, we have to compute it before we put anything into the undo table.
We'd like to catch as many invalid transformations here as possible. Unfortunately, there are way too many mode changes that are perfectly valid, so we'd waste too much effort for little gain doing the checks here. Focus on catching invalid transformations involving integer constants.
Sanity check that we're replacing oldval with a CONST_INT that is a valid signextension for the original mode.
Replacing the operand of a SUBREG or a ZERO_EXTEND with a CONST_INT is not valid, because after the replacement, the original mode would be gone. Unfortunately, we can't tell when do_SUBST is called to replace the operand thereof, so we perform this test on oldval instead, checking whether an invalid replacement took place before we got here.
References undobuf::frees, undo::i, undo::kind, undo::next, undo::old_contents, UNDO_INT, undobuf::undos, and undo::where.

static 

static 
Similar to SUBST, but NEWVAL is an int expression. Note that substitution for the value of a HOST_WIDE_INT value (including CONST_INT) is not safe.
References undobuf::frees, undo::kind, undo::l, undo::next, undo::old_contents, UNDO_LINKS, undobuf::undos, and undo::where.

static 
Similar to SUBST, but NEWVAL is a LOG_LINKS expression.

static 
Similar to SUBST, but just substitute the mode. This is used when changing the mode of a pseudoregister, so that any other references to the entry in the regno_reg_rtx array will change as well.
References new_cost().
DEBUG_FUNCTION void dump_combine_stats  (  ) 
void dump_combine_total_stats  (  ) 
Referenced by opt_info_switch_p().
Referenced by distribute_and_simplify_rtx(), and simplify_set().

static 
We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound operations" because they can be replaced with two more basic operations. ZERO_EXTEND is also considered "compound" because it can be replaced with an AND operation, which is simpler, though only one operation. The function expand_compound_operation is called with an rtx expression and will convert it to the appropriate shifts and AND operations, simplifying at each stage. The function make_compound_operation is called to convert an expression consisting of shifts and ANDs into the equivalent compound expression. It is the inverse of this function, loosely speaking.
We can't necessarily use a const_int for a multiword mode; it depends on implicitly extending the value. Since we don't know the right way to extend it, we can't tell whether the implicit way is right. Even for a mode that is no wider than a const_int, we can't win, because we need to sign extend one of its bits through the rest of it, and we don't know which bit.
Return if (subreg:MODE FROM 0) is not a safe replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded. If not for that, MEM's would very rarely be safe. Reject MODEs bigger than a word, because we might not be able to reference a tworegister group starting with an arbitrary register (and currently gen_lowpart might crash for a SUBREG).
Reject MODEs that aren't scalar integers because turning vector or complex modes into shifts causes problems.
If the inner object has VOIDmode (the only way this can happen is if it is an ASM_OPERANDS), we can't do anything since we don't know how much masking to do.
... fall through ...
If the operand is a CLOBBER, just return it.
Reject MODEs that aren't scalar integers because turning vector or complex modes into shifts causes problems.
This should stay within the object being extracted, fail otherwise.
Convert sign extension to zero extension, if we know that the high bit is not set, as this is easier to optimize. It will be converted back to cheaper alternative in make_extraction.
Make sure this is a profitable operation.
We can optimize some special cases of ZERO_EXTEND.
(zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we know that the last value didn't have any inappropriate bits set.
Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).
(zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo is a comparison and STORE_FLAG_VALUE permits. This is like the first case, but it works even when GET_MODE (x) is larger than HOST_WIDE_INT.
Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).
If we reach here, we want to return a pair of shifts. The inner shift is a left shift of BITSIZE  POS  LEN bits. The outer shift is a right shift of BITSIZE  LEN bits. It is arithmetic or logical depending on the value of UNSIGNEDP. If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be converted into an AND of a shift. We must check for the case where the left shift would have a negative count. This can happen in a case like (x >> 31) & 255 on machines that can't shift by a constant. On those machines, we would first combine the shift with the AND to produce a variableposition extraction. Then the constant of 31 would be substituted in to produce such a position.
Any other cases we can't handle.
If we couldn't do this for some reason, return the original expression.

static 
X is a SET which contains an assignment of one object into a part of another (such as a bitfield assignment, STRICT_LOW_PART, or certain SUBREGS). If possible, convert it into a series of logical operations. We halfheartedly support variable positions, but do not at all support variable lengths.
Loop until we find something we can't simplify.
A constant position should stay within the width of INNER.
If position is ADJUST  X, new position is X.
A SUBREG between two modes that occupy the same numbers of words can be done by moving the SUBREG to the source.
We need SUBREGs to compute nonzero_bits properly.
Don't attempt bitwise arithmetic on non scalar integer modes.
Don't do anything for vector or complex integral types.
Try to find an integral mode to pun with.
Compute a mask of LEN bits, if we can do this on the host machine.
Now compute the equivalent expression. Make a copy of INNER for the SET_DEST in case it is a MEM into which we will substitute; we don't want shared RTL in that case.
unsigned int extended_count  (  ) 
Return the number of "extended" bits there are in X, when interpreted as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For unsigned quantities, this is the number of highorder zero bits. For signed quantities, this is the number of copies of the sign bit minus 1. In both case, this function returns the number of "spare" bits. For example, if two quantities for which this function returns at least 1 are added, the addition is known not to overflow. This function will always return 0 unless called during combine, which implies that it must be called from a define_split.
Referenced by make_extraction().

static 
See if X contains an ASHIFT of COUNT or more bits that can be commuted with any other operations in X. Return X without that shift if so.
This is the shift itself. If it is wide enough, we will return either the value being shifted if the shift count is equal to COUNT or a shift for the difference.
If we can safely shift this constant and we find the inner shift, make a new operation.

static 
See if DEST, produced in INSN, is used only a single time in the sequel. If so, return a pointer to the innermost rtx expression in which it is used. If PLOC is nonzero, *PLOC is set to the insn containing the single use. If DEST is cc0_rtx, we look only at the next insn. In that case, we don't care about REG_DEAD notes or LOG_LINKS. Otherwise, we find the single use by finding an insn that has a LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is only referenced once in that insn, we know that it must be the first and last insn referencing DEST.
References undobuf::frees, undo::kind, undo::next, undo::old_contents, undo::r, trunc_int_for_mode(), UNDO_RTX, undobuf::undos, and undo::where.

static 
This is used by find_single_use to locate an rtx in LOC that contains exactly one use of DEST, which is typically either a REG or CC0. It returns a pointer to the innermost rtx expression containing DEST. Appearances of DEST that are being used to totally replace it are not counted.
If the destination is anything other than CC0, PC, a REG or a SUBREG of a REG that occupies all of the REG, the insn uses DEST if it is mentioned in the destination or the source. Otherwise, we need just check the source.
If it wasn't one of the common cases above, check each expression and vector of this code. Look for a unique usage of DEST.
Duplicate usage.
Referenced by undo_commit().

static 
Find the innermost point within the rtx at LOC, possibly LOC itself, where we have an arithmetic expression and return that point. LOC will be inside INSN. try_combine will call this function to see if an insn can be split into two insns.
First specialcase some codes.
If we are making a paradoxical SUBREG invalid, it becomes a split point.
If we have (mem (const ..)) or (mem (symbol_ref ...)), split it using LO_SUM and HIGH.
If we have a PLUS whose second operand is a constant and the address is not valid, perhaps will can split it up using the machinespecific way to split large constants. We use the first pseudoreg (one of the virtual regs) as a placeholder; it will not remain in the result.
This should have produced two insns, each of which sets our placeholder. If the source of the second is a valid address, we can make put both sources together and make a split point in the middle.
Replace the placeholder in SRC2 with SRC1. If we can find where in SRC2 it was placed, that can become our split point and we can replace this address with SRC2. Just try two obvious places.
If that didn't work, perhaps the first operand is complex and needs to be computed separately, so make a split point there. This will occur on machines that just support REG + CONST and have a constant moved through some previous computation.
If we have a PLUS whose first operand is complex, try computing it separately by making a split there.
If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a ZERO_EXTRACT, the most likely reason why this doesn't match is that we need to put the operand into a register. So split at that point.
See if we can split SET_SRC as it stands.
See if we can split SET_DEST as it stands.
See if this is a bitfield assignment with everything constant. If so, this is an IOR of an AND, so split it into that.
Otherwise, see if this is an operation that we can split into two. If so, try to split that.
If we are AND'ing with a large constant that is only a single bit and the result is only being used in a context where we need to know if it is zero or nonzero, replace it with a bit extraction. This will avoid the large constant, which might have taken more than one insn to make. If the constant were not a valid argument to the AND but took only one insn to make, this is no worse, but if it took more than one insn, it will be better.
If STORE_FLAG_VALUE is 1, this is (NE X 0) and only one bit of X is known to be on, this can be converted into a NEG of a shift.
We can't optimize if either mode is a partial integer mode as we don't know how many bits are significant in those modes.
For unsigned, we have a choice of a shift followed by an AND or two shifts. Use two shifts for field sizes where the constant might be too large. We assume here that we can always at least get 8bit constants in an AND insn, which is true for every current RISC.
See if this is a simple operation with a constant as the second operand. It might be that this constant is out of range and hence could be used as a split point.
Finally, see if this is a simple operation with its first operand not in a register. The operation might require this operand in a register, so return it as a split point. We can always do this because if the first operand were another operation, we would have already found it as a split point.
We write NOR as (and (not A) (not B)), but if we don't have a NOR, it is better to write this as (not (ior A B)) so we can split it. Similarly for IOR.
Many RISC machines have a large set of logical insns. If the second operand is a NOT, put it first so we will try to split the other operand first.
Canonicalization can produce (minus A (mult B C)), where C is a constant. It may be better to try splitting (plus (mult B C) A) instead if this isn't a multiply by a power of two.
Split at a multiplyaccumulate instruction. However if this is the SET_SRC, we likely do not have such an instruction and it's worthless to try this split.
Otherwise, select our actions depending on our rtx class.
... fall through ...
... fall through ...
Some machines have (and (shift ...) ...) insns. If X is not an AND, but XEXP (X, 0) is, use it as our split point.
Otherwise, we don't have a split point.

static 
See if X can be simplified knowing that we will only refer to it in MODE and will only refer to those bits that are nonzero in MASK. If other bits are being computed or if masking operations are done that select a superset of the bits in MASK, they can sometimes be ignored. Return a possibly simplified expression, but always convert X to MODE. If X is a CONST_INT, AND the CONST_INT with MASK. If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK are all off in X. This is used when X will be complemented, by either NOT, NEG, or XOR.
If this is a CALL or ASM_OPERANDS, don't do anything. Some of the code below will do the wrong thing since the mode of such an expression is VOIDmode. Also do nothing if X is a CLOBBER; this can happen if X was the return value from a call to gen_lowpart.
We want to perform the operation is its present mode unless we know that the operation is valid in MODE, in which case we do the operation in MODE.
It is not valid to do a rightshift in a narrower mode than the one it came in with.
Truncate MASK to fit OP_MODE.
When we have an arithmetic operation, or a shift whose count we do not know, we need to assume that all bits up to the highestorder bit in MASK will be needed. This is how we form such a mask.
Determine what bits of X are guaranteed to be (non)zero.
If none of the bits in X are needed, return a zero.
If X is a CONST_INT, return a new one. Do this here since the test below will fail.
If X is narrower than MODE and we want all the bits in X's mode, just get X in the proper mode.
We can ignore the effect of a SUBREG if it narrows the mode or if the constant masks to zero all the bits the mode doesn't have.
The arithmetic simplifications here only work for scalar integer modes.
If X is a (clobber (const_int)), return it since we know we are generating something that won't match.
Similarly for a truncate.
If this is an AND with a constant, convert it into an AND whose constant is the AND of that constant with MASK. If it remains an AND of MASK, delete it since it is redundant.
If X is still an AND, see if it is an AND with a mask that is just some loworder bits. If so, and it is MASK, we don't need it.
If it remains an AND, try making another AND with the bits in the mode mask that aren't in MASK turned on. If the constant in the AND is wide enough, this might make a cheaper constant.
In (and (plus FOO C1) M), if M is a mask that just turns off loworder bits (as in an alignment operation) and FOO is already aligned to that boundary, mask C1 to that boundary as well. This may eliminate that PLUS and, later, the AND.
If MODE is narrower than HOST_WIDE_INT and mask is a negative number, sign extend it.
... fall through ...
For PLUS, MINUS and MULT, we need any bits less significant than the most significant bit in MASK since carries from those bits will affect the bits we are interested in.
If X is (minus C Y) where C's least set bit is larger than any bit in the mask, then we may replace with (neg Y).
Similarly, if C contains every bit in the fuller_mask, then we may replace with (not Y).
If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) operation which may be a bitfield extraction. Ensure that the constant we form is not wider than the mode of X.
For most binary operations, just propagate into the operation and change the mode if we have an operation of that mode.
If we ended up truncating both operands, truncate the result of the operation instead.
For left shifts, do the same, but just for the first operand. However, we cannot do anything with shifts where we cannot guarantee that the counts are smaller than the size of the mode because such a count will have a different meaning in a wider mode.
If the shift count is a constant and we can do arithmetic in the mode of the shift, refine which bits we need. Otherwise, use the conservative form of the mask.
Here we can only do something if the shift count is a constant, this shift constant is valid for the host, and we can do arithmetic in OP_MODE.
Select the mask of the bits we need for the shift operand.
We can only change the mode of the shift if we can do arithmetic in the mode of the shift and INNER_MASK is no wider than the width of X's mode.
If we have (and (lshiftrt FOO C1) C2) where the combination of the shift and AND produces only copies of the sign bit (C2 is one less than a power of two), we can do this with just a shift.
The shift puts one of the sign bit copies in the least significant bit.
Number of bits left after the shift must be more than the mask needs.
Must be more sign bit copies than the mask needs.
If we are just looking for the sign bit, we don't need this shift at all, even if it has a variable count.
If this is a shift by a constant, get a mask that contains those bits that are not copies of the sign bit. We then have two cases: If MASK only includes those bits, this can be a logical shift, which may allow simplifications. If MASK is a singlebit field not within those bits, we are requesting a copy of the sign bit and hence can shift the sign bit to the appropriate location.
If the considered data is wider than HOST_WIDE_INT, we can't represent a mask for all its bits in a single scalar. But we only care about the lower bits, so calculate these.
GET_MODE_PRECISION (GET_MODE (x))  INTVAL (XEXP (x, 1)) is the number of bits a fullwidth mask would have set. We need only shift if these are fewer than nonzero can hold. If not, we must keep all bits set in nonzero.
If MASK is 1, convert this to an LSHIFTRT. This can be done even if the shift count isn't a constant.
If this is a zero or signextension operation that just affects bits we don't care about, remove it. Be sure the call above returned something that is still a shift.
If the shift count is constant and we can do computations in the mode of X, compute where the bits we care about are. Otherwise, we can't do anything. Don't change the mode of the shift or propagate MODE into the shift, though.
If we just want the loworder bit, the NEG isn't needed since it won't change the loworder bit.
We need any bits less significant than the most significant bit in MASK since carries from those bits will affect the bits we are interested in.
(not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the same as the XOR case above. Ensure that the constant we form is not wider than the mode of X.
(and (not FOO) CONST) is (not (or FOO (not CONST))), so we must use the full mask inside the NOT.
(and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, which is equal to STORE_FLAG_VALUE.
We have no way of knowing if the IF_THEN_ELSE can itself be written in a narrower mode. We play it safe and do not do so.
Ensure we return a value of the proper mode.
Referenced by make_extraction().

static 
Referenced by move_deaths().

static 
Like gen_lowpart_general but for use by combine. In combine it is not possible to create any new pseudoregs. However, it is safe to create invalid memory addresses, because combine will try to recognize them and all they will do is make the combine attempt fail. If for some reason this cannot do its job, an rtx (clobber (const_int 0)) is returned. An insn containing that will not be recognized.
We can only support MODE being wider than a word if X is a constant integer or has a mode the same size.
X might be a paradoxical (subreg (mem)). In that case, gen_lowpart won't know what to do. So we will strip off the SUBREG here and process normally.
For use in case we fall down into the address adjustments further below, we need to adjust the known mode and size of x; imode and isize, since we just adjusted x.
Refuse to work on a volatile memory ref or one with a modedependent address.
If we want to refer to something bigger than the original memref, generate a paradoxical subreg instead. That will force a reload of the original memref X.
Adjust the address so that the addressafterthedata is unchanged.
If X is a comparison operator, rewrite it in a new mode. This probably won't match, but may allow further simplifications.
If we couldn't simplify X any other way, just enclose it in a SUBREG. Normally, this SUBREG won't match, but some patterns may include an explicit SUBREG or we may simplify it further in combine.

static 
Return X converted to MODE. If the value is already truncated to MODE we can just return a subreg even though in the general case we would need an explicit truncation.
Bitcast X into an integer mode.

static 
Get the last value assigned to X, if known. Some registers in the value may be replaced with (clobber (const_int 0)) if their value is known longer known reliably.
If this is a nonparadoxical SUBREG, get the value of its operand and then convert it to the desired mode. If this is a paradoxical SUBREG, we cannot predict what values the "extra" bits might have.
If we don't have a value, or if it isn't for this basic block and it's either a hard register, set more than once, or it's a live at the beginning of the function, return 0. Because if it's not live at the beginning of the function then the reg is always set before being used (is never used without being set). And, if it's set only once, and it's always set before use, then all uses must have the same last value, even if it's not from this basic block.
If the value was set in a later insn than the ones we are processing, we can't use it even if the register was only set once.
If the value has all its registers valid, return it.
Otherwise, make a copy and replace any invalid register with (clobber (const_int 0)). If that fails for some reason, return 0.
References find_regno_note().

static 
Verify that all the registers and memory references mentioned in *LOC are still valid. *LOC was part of a value set in INSN when label_tick was equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace the invalid references with (clobber (const_int 0)) and return 1. This replacement is useful because we often can get useful information about the form of a value (e.g., if it was produced by a shift that always produces 1 or 0) even though we don't know exactly what registers it was produced from.
If this is a pseudoregister that was only set once and not live at the beginning of the function, it is always valid.
If this is a memory reference, make sure that there were no stores after it that might have clobbered the value. We don't have alias info, so we assume any store invalidates it. Moreover, we only have local UIDs, so we also assume that there were stores in the intervening basic blocks.
Check for identical subexpressions. If x contains identical subexpression we only have to traverse one of them.
Note that at this point x0 has already been checked and found valid.
If x0 and x1 are identical then x is also valid.
If x1 is identical to a subexpression of x0 then while checking x0, x1 has already been checked. Thus it is valid and so as x.
If x0 is identical to a subexpression of x1 then x is valid iff the rest of x1 is valid.
If we haven't found a reason for it to be invalid, it is valid.
References find_reg_fusage(), i2, next_nonnote_nondebug_insn(), reg_overlap_mentioned_p(), reg_referenced_p(), and rtx_equal_p().

static 

static 
Given M see if it is a value that would select a field of bits within an item, but not the entire word. Return 1 if not. Otherwise, return the starting position of the field, where 0 is the loworder bit. *PLEN is set to the length of the field.
Get the bit number of the first 1 bit from the right, 1 if none.
Now shift off the loworder zero bits and see if we have a power of two minus 1.

static 
Return nonzero if X is an expression that has one of two values depending on whether some other value is zero or nonzero. In that case, we return the value that is being tested, *PTRUE is set to the value if the rtx being returned has a nonzero value, and *PFALSE is set to the other alternative. If we return zero, we set *PTRUE and *PFALSE to X.
If we are comparing a value against zero, we are done.
If this is a unary operation whose operand has one of two values, apply our opcode to compute those values.
If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would make can't possibly match and would suppress other optimizations.
If this is a binary operation, see if either side has only one of two values. If either one does or if both do and they are conditional on the same value, compute the new true and false values.
If if_then_else_cond returned zero, then true/false are the same rtl. We must copy one of them to prevent invalid rtl sharing.
See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the operands is zero when the other is nonzero, and viceversa, and STORE_FLAG_VALUE is 1 or 1.
Similarly for MULT, AND and UMIN, except that for these the result is always zero.
If we have IF_THEN_ELSE already, extract the condition and canonicalize it if it is NE or EQ.
If X is a SUBREG, we can narrow both the true and false values if the inner expression, if there is a condition.
If X is a constant, this isn't special and will cause confusions if we treat it as such. Likewise if it is equivalent to a constant.
If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that will be least confusing to the rest of the compiler.
If X is known to be either 0 or 1, those are the true and false values when testing X.
Likewise for 0 or a single bit.
Otherwise fail; show no condition with true and false values the same.

static 
Wipe the last_xxx fields of reg_stat in preparation for another pass.
References reg_stat.

static 
Walk the LOG_LINKS of insn B to see if we find a reference to A. Return true if we found a LOG_LINK that proves that A feeds B. This only works if there are no instructions between A and B which could have a link depending on A, since in that case we would not record a link for B. We also check the implicit dependency created by a cc0 setter/user pair.

static 
Return the value of expression X given the fact that condition COND is known to be true when applied to REG as its first operand and VAL as its second. X is known to not be shared and so can be modified in place. We only handle the simplest cases, and specifically those cases that arise with IF_THEN_ELSE expressions.
If either operand of the condition is a floating point value, then we have to avoid collapsing an EQ comparison.
If X is (abs REG) and we know something about REG's relationship with zero, we may be able to simplify this.
The only other cases we handle are MIN, MAX, and comparisons if the operands are the same as REG and VAL.
Do not reverse the condition when it is NE or EQ. This is because we cannot conclude anything about the value of 'SMAX (x, y)' when x is not equal to y, but we can when x equals y.
We must simplify subreg here, before we lose track of the original inner_mode.
We don't have to handle SIGN_EXTEND here, because even in the case of replacing something with a modeless CONST_INT, a CONST_INT is already (supposed to be) a valid sign extension for its narrower mode, which implies it's already properly signextended for the wider mode. Now, for ZERO_EXTEND, the story is different.
We must simplify the zero_extend here, before we lose track of the original inner_mode.

static 
Called via note_stores by likely_spilled_retval_p. Remove from info>mask hard registers that are known to be written to / clobbered in full.

static 
Return nonzero iff part of the return value is live during INSN, and it is likely spilled. This can happen when more than one insn is needed to copy the return value, e.g. when we consider to combine into the second copy insn for a complex value.
We assume here that no machine mode needs more than 32 hard registers when the value overlaps with a register for which TARGET_FUNCTION_VALUE_REGNO_P is true.
Disregard parts of the return value that are set later.
Check if any of the (probably) live return value registers is likely spilled.
References insn_code_number.
rtx make_compound_operation  (  ) 
Look at the expression rooted at X. Look for expressions equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. Form these expressions. Return the new rtx, usually just X. Also, for machines like the VAX that don't have logical shift insns, try to convert logical to arithmetic shift operations in cases where they are equivalent. This undoes the canonicalizations to logical shifts done elsewhere. We try, as much as possible, to reuse rtl expressions to save memory. IN_CODE says what kind of expression we are processing. Normally, it is SET. In a memory address (inside a MEM, PLUS or minus, the latter two being kludges), it is MEM. When processing the arguments of a comparison or a COMPARE against zero, it is COMPARE.
Select the code to be used in recursive calls. Once we are inside an address, we stay there. If we have a comparison, set to COMPARE, but once inside, go back to our default of SET.
Process depending on the code of this operation. If NEW is set nonzero, it will be returned.
Convert shifts by constants into multiplications if inside an address.
If the second operand is not a constant, we can't do anything with it.
If the constant is a power of two minus one and the first operand is a logical right shift, make an extraction.
Same as previous, but for (subreg (lshiftrt ...)) in first op.
Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).
Apply the distributive law, and then try to make extractions.
If we are have (and (rotate X C) M) and C is larger than the number of bits in M, this is an extraction.
On machines without logical shifts, if the operand of the AND is a logical shift and our mask turns off all the propagated sign bits, we can replace the logical shift with an arithmetic shift.
If the constant is one less than a power of two, this might be representable by an extraction even if no shift is present. If it doesn't end up being a ZERO_EXTEND, we will ignore it unless we are in a COMPARE.
If we are in a comparison and this is an AND with a power of two, convert this into the appropriate bit extract.
If the sign bit is known to be zero, replace this with an arithmetic shift.
... fall through ...
If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, this is a SIGN_EXTRACT.
See if we have operations between an ASHIFTRT and an ASHIFT. If so, try to merge the shifts into a SIGN_EXTEND. We could also do this for some cases of SIGN_EXTRACT, but it doesn't seem worth the effort; the case checked for occurs on Alpha.
Call ourselves recursively on the inner expression. If we are narrowing the object and it has a different RTL code from what it originally did, do this SUBREG as a force_to_mode.
If in_code is COMPARE, it isn't always safe to pass it through to the recursive make_compound_operation call.
(subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0) is (const_int 0), rather than (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
If we have something other than a SUBREG, we might have done an expansion, so rerun ourselves.
force_to_mode can expand compounds. If it just reexpanded the compound, use gen_lowpart to convert to the desired mode.
Likewise if it reexpanded the compound only partially. This happens for SUBREG of ZERO_EXTRACT if they extract the same number of bits.
Now recursively process each operand of this operation. We need to handle ZERO_EXTEND specially so that we don't lose track of the inner mode.
If this is a commutative operation, the changes to the operands may have made it noncanonical.
References int_mode_for_mode(), and simplify_gen_unary().
Referenced by make_extraction().

static 
Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, it is an RTX that represents the (variable) starting position; otherwise, POS is the (constant) starting bit position. Both are counted from the LSB. UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one. IN_DEST is nonzero if this is a reference in the destination of a SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will be used. IN_COMPARE is nonzero if we are in a COMPARE. This means that a ZERO_EXTRACT should be built even for bits starting at bit 0. MODE is the desired mode of the result (if IN_DEST == 0). The result is an RTX for the extraction or NULL_RTX if the target can't handle it.
This mode describes the size of the storage area to fetch the overall value from. Within that, we ignore the POS lowest bits, etc.
If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), consider just the QI as the memory to extract from. The subreg adds or removes high bits; its mode is irrelevant to the meaning of this extraction, since POS and LEN count from the lsb.
We're extracting the least significant bits of an rtx (ashift X (const_int C)), where LEN > C. Extract the least significant (LEN  C) bits of X, giving an rtx whose mode is MODE, then shift it left C times.
See if this can be done without an extraction. We never can if the width of the field is not the same as that of some integer mode. For registers, we can only avoid the extraction if the position is at the loworder bit and this is either not in the destination or we have the appropriate STRICT_LOW_PART operation available. For MEM, we can avoid an extract if the field starts on an appropriate boundary and we can change the mode of the memory reference.
We can't do this if we are widening INNER_MODE (it may not be aligned, for one thing).
If INNER is a MEM, make a new MEM that encompasses just the desired field. If the original and current mode are the same, we need not adjust the offset. Otherwise, we do if bytes big endian. If INNER is not a MEM, get a piece consisting of just the field of interest (in this case POS % BITS_PER_WORD must be 0).
POS counts from lsb, but make OFFSET count in memory order.
We can't call gen_lowpart in a DEST since we always want a SUBREG (see below) and it would sometimes return a new hard register.
Avoid creating invalid subregs, for example when simplifying (x>>32)&255.
If this extraction is going into the destination of a SET, make a STRICT_LOW_PART unless we made a MEM.
If we know that no extraneous bits are set, and that the high bit is not set, convert the extraction to the cheaper of sign and zero extension, that are equivalent in these cases.
Prefer ZERO_EXTENSION, since it gives more information to backends.
Otherwise, sign or zeroextend unless we already are in the proper mode.
Unless this is a COMPARE or we have a funny memory reference, don't do anything with zeroextending field extracts starting at the loworder bit since they are simple AND operations.
Unless INNER is not MEM, reject this if we would be spanning bytes or if the position is not a constant and the length is not 1. In all other cases, we would only be going outside our object in cases when an original shift would have been undefined.
If INNER is not from memory, we want it to have the mode of a register extraction pattern's structure operand, or word_mode if there is no such pattern. The same applies to extraction_mode and pos_mode and their respective operands. For memory, assume that the desired extraction_mode and pos_mode are the same as for a register operation, since at present we don't have named patterns for aligned memory structures.
Never narrow an object, since that might not be safe.
Be careful not to go beyond the extracted object and maintain the natural alignment of the memory.
POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to BITS_BIG_ENDIAN style. If position is constant, compute new position. Otherwise, build subtraction. Note that POS is relative to the mode of the original argument. If it's a MEM we need to recompute POS relative to that. However, if we're extracting from (or inserting into) a register, we want to recompute POS relative to wanted_inner_mode.
POS may be less than 0 now, but we check for that below. Note that it can only be less than 0 if !MEM_P (inner).
If INNER has a wider mode, and this is a constant extraction, try to make it smaller and adjust the byte to point to the byte containing the value.
The computations below will be correct if the machine is big endian in both bits and bytes or little endian in bits and bytes. If it is mixed, we must adjust.
If bytes are big endian and we had a paradoxical SUBREG, we must adjust OFFSET to compensate.
We can now move to the desired byte.
If INNER is not memory, get it into the proper mode. If we are changing its mode, POS must be a constant and smaller than the size of the new mode.
On the LHS, don't create paradoxical subregs implicitely truncating the register unless TRULY_NOOP_TRUNCATION.
Adjust mode of POS_RTX, if needed. If we want a wider mode, we have to zero extend. Otherwise, we can just use a SUBREG.
If we know that no extraneous bits are set, and that the high bit is not set, convert extraction to cheaper one  either SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these cases.
Prefer ZERO_EXTENSION, since it gives more information to backends.
Make POS_RTX unless we already have it and it is correct. If we don't have a POS_RTX but we do have an ORIG_POS_RTX, the latter must be a CONST_INT.
Make the required operation. See if we can use existing rtx.
References exact_log2(), extract_left_shift(), force_to_mode(), gen_int_mode(), have_insn_for(), HOST_BITS_PER_WIDE_INT, HOST_WIDE_INT, make_compound_operation(), nonzero_bits(), rtx_equal_p(), SET, simplify_gen_binary(), simplify_gen_unary(), simplify_subreg(), subreg_lowpart_p(), and trunc_int_for_mode().

static 
See if X, a SET operation, can be rewritten as a bitfield assignment. Return that assignment if so. We only handle the most common cases.
If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is a clear of a onebit field. We will have changed it to (and (rotate (const_int 2) POS) DEST), so check for that. Also check for a SUBREG.
If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a onebit field.
If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the SRC is an AND with all bits of that field set, then we can discard the AND.
Complete overlap. We can remove the source AND.
Partial overlap. We can reduce the source AND.
The other case we handle is assignments into a constantposition field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents a mask that has all one bits except for a group of zero bits and OTHER is known to have zeros where C1 has ones, this is such an assignment. Compute the position and length from C1. Shift OTHER to the appropriate position, force it to the required mode, and make the extraction. Check for the AND in both operands.
The mode to use for the source is the mode of the assignment, or of what is inside a possible STRICT_LOW_PART.
Shift OTHER right POS places and make it the source, restricting it to the proper length and mode.
If SRC is masked by an AND that does not make a difference in the value being stored, strip it.
References SET, and trunc_int_for_mode().
rtl_opt_pass* make_pass_combine  (  ) 

static 

static 
Note hard registers in X that are used.
CC0 must die in the insn after it is set, so we don't need to take special note of it here.
If we are clobbering a MEM, mark any hard registers inside the address as used.
A hard reg in a wide mode may really be multiple registers. If so, mark all of them just like the first.
None of this applies to the stack, frame or arg pointers.
If setting a MEM, or a SUBREG of a MEM, then note any hard regs in the address.
Recursively scan the operands of this expression.
References insn_link::insn, and reg_referenced_p().

static 

static 
This function is called from `simplify_shift_const' to merge two outer operations. Specifically, we have already found that we need to perform operation *POP0 with constant *PCONST0 at the outermost position. We would now like to also perform OP1 with constant CONST1 (with *POP0 being done last). Return 1 if we can do the operation and update *POP0 and *PCONST0 with the resulting operation. *PCOMP_P is set to 1 if we would need to complement the innermost operand, otherwise it is unchanged. MODE is the mode in which the operation will be done. No bits outside the width of this mode matter. It is assumed that the width of this mode is smaller than or equal to HOST_BITS_PER_WIDE_INT. If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper result is simply *PCONST0. If the resulting operation cannot be expressed as one operation, we return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.
If OP0 is an AND, clear unimportant bits in CONST1.
If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or if OP0 is SET.
Otherwise, if either is a PLUS or NEG, we can't do anything.
If the two constants aren't the same, we can't do anything. The remaining six cases can all be done.
(a & b)  b == b
(a ^ b)  b == a  b
(a & b) ^ b == (~a) & b
(a  b) ^ b == a & ~b
(a  b) & b == b
(a ^ b) & b) == (~a) & b
Check for NOOP cases.
??? Slightly redundant with the above mask, but not entirely. Moving this above means we'd have to signextend the mode mask for the final test.

static 
For each register (hardware or pseudo) used within expression X, if its death is in an instruction with luid between FROM_LUID (inclusive) and TO_INSN (exclusive), put a REG_DEAD note for that register in the list headed by PNOTES. That said, don't move registers killed by maybe_kill_insn. This is done when X is being merged by combination into TO_INSN. These notes will then be distributed as needed.
Don't move the register if it gets killed in between from and to.
It is possible for the call above to return 0. This can occur when last_death points to I2 or I1 that we combined with. In that case make a new note. We must also check for the case where X is a hard register and NOTE is a death note for a range of hard registers including X. In that case, we must put REG_DEAD notes for the remaining registers in place of NOTE.
If we didn't find any note, or if we found a REG_DEAD note that covers only part of the given reg, and we have a multireg hard register, then to be safe we must check for REG_DEAD notes for each register other than the first. They could have their own REG_DEAD notes lying around.
In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG that accesses one word of a multiword item, some piece of everything register in the expression is used by this insn, so remove any old death.
??? So why do we test for equality of the sizes?
If this is some other SUBREG, we know it replaces the entire value, so use that as the destination.
If this is a MEM, adjust deaths of anything used in the address. For a REG (the only other possibility), the entire value is being replaced so the old value is not used in this insn.
References execute(), gate_handle_combine(), and rest_of_handle_combine().
Referenced by record_value_for_reg().

static 
Like recog, but we receive the address of a pointer to a new pattern. We try to match the rtx that the pointer points to. If that fails, we may try to modify or replace the pattern, storing the replacement into the same pointer object. Modifications include deletion or addition of CLOBBERs. PNOTES is a pointer to a location where any REG_UNUSED notes added for the CLOBBERs are placed. The value is the final insn code from the pattern ultimately matched, or 1.
If PAT is a PARALLEL, check to see if it contains the CLOBBER we use to indicate that something didn't match. If we find such a thing, force rejection.
If it isn't, there is the possibility that we previously had an insn that clobbered some register as a side effect, but the combined insn doesn't need to do that. So try once more without the clobbers unless this represents an ASM insn.
Recognize all noop sets, these will be killed by followup pass.
If we had any clobbers to add, make a new pattern than contains them. Then check to make sure that all of them are dead.
Allow targets to reject combined insn.
Callers expect recog_for_combine to strip clobbers from the pattern on failure.
References swap_condition().

static 

static 
Update the records of when each REG was most recently set or killed for the things done by INSN. This is the last thing done in processing INSN in the combiner loop. We update reg_stat[], in particular fields last_set, last_set_value, last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, last_death, and also the similar information mem_last_set (which insn most recently modified memory) and last_call_luid (which insn was the most recent subroutine call).
We can't combine into a call pattern. Remember, though, that the return value register is set at this LUID. We could still replace a register with the return value from the wrong subroutine call!

static 
Called via note_stores from record_dead_and_set_regs to handle one SET or CLOBBER in an insn. DATA is the instruction in which the set is occurring.
If we are setting the whole register, we know its value. Otherwise show that we don't know the value. We can handle SUBREG in some cases.
Ignore pushes, they clobber nothing.

static 
If a SUBREG has the promoted bit set, it is in fact a property of the register present in the SUBREG, so for each such SUBREG go back and adjust nonzero and sign bit information of the registers that are known to have some zero/sign bits set. This is needed because when combine blows the SUBREGs away, the information on zero/sign bits is lost and further combines can be missed because of that.
References find_reg_note(), and find_regno_note().

static 

static 
Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode that the register is accessed in. For nonTRULY_NOOP_TRUNCATION targets we might be able to turn a truncate into a subreg using this information. Return 1 if traversing *P is complete or 0 otherwise.
??? For hardregs we now record everything. We might be able to optimize this using last_set_mode.

static 

static 
Callback for note_uses. Find hardregs and subregs of pseudos and the modes they are used in. This can help truning TRUNCATEs into SUBREGs.

static 
Record that REG is set to VALUE in insn INSN. If VALUE is zero, we are saying that the register is clobbered and we no longer know its value. If INSN is zero, don't update reg_stat[].last_set; this is only permitted with VALUE also zero and is used to invalidate the register.
If VALUE contains REG and we have a previous value for REG, substitute the previous value.
Set things up so get_last_value is allowed to see anything set up to our insn.
If TEM is simply a binary operation with two CLOBBERs as operands, it isn't going to be useful and will take a lot of time to process, so just use the CLOBBER.
If there are two or more occurrences of REG in VALUE, prevent the value from growing too much.
For each register modified, show we don't know its value, that we don't know about its bitwise content, that its value has been updated, and that we don't know the location of the death of the register.
Mark registers that are being referenced in this value.
Now update the status of each register being set. If someone is using this register in this block, set this register to invalid since we will get confused between the two lives in this basic block. This makes using this register always invalid. In cse, we scan the table to invalidate all entries using this register, but this is too much work for us.
The value being assigned might refer to X (like in "x++;"). In that case, we must replace it with (clobber (const_int 0)) to prevent infinite loops.
For the main register being modified, update the value, the mode, the nonzero bits, and the number of sign bit copies.
References move_deaths(), offset, and regno_reg_rtx.
Referenced by use_crosses_set_p().

static 
Return 1 if X is the target of a bitfield assignment in BODY, the pattern of an insn. X must be a REG.

static 
Return nonzero if REG is known to be dead at INSN. We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER referencing REG, it is dead. If we hit a SET referencing REG, it is live. Otherwise, see if it is live or dead at the start of the basic block we are in. Hard regs marked as being live in NEWPAT_USED_REGS must be assumed to be always live.
Set variables for reg_dead_at_p_1.
Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers we allow the machine description to decide whether useandclobber patterns are OK.
Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or beginning of basic block.
Look at livein sets for the basic block that we were in.

static 
Function called via note_stores from reg_dead_at_p. If DEST is within [reg_dead_regno, reg_dead_endregno), set reg_dead_flag to 1 if X is a CLOBBER and to 1 it is a SET.

static 
Given a REG, X, compute which bits in X can be nonzero. We don't care about bits outside of those defined in MODE. For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is a shift, AND, or zero_extract, we can do better.
If X is a register whose nonzero bits value is current, use it. Otherwise, if X is a register whose value we can find, use that value. Otherwise, use the previouslycomputed global nonzero bits for this register.
If X is narrower than MODE and TEM is a nonnegative constant that would appear negative in the mode of X, signextend it for use in reg_nonzero_bits because some machines (maybe most) will actually do the signextension and this is the conservative approach. ??? For 2.5, try to tighten up the MD files in this regard instead of this kludge.
We don't know anything about the upper bits.

static 
Return the number of bits at the highorder end of X that are known to be equal to the sign bit. X will be used in mode MODE; if MODE is VOIDmode, X will be used in its own mode. The returned value will always be between 1 and the number of bits in MODE.

static 
Check whether X, the destination of a set, refers to part of the register specified by REG.
Check that reg is an integer mode register.

static 

static 
Check if X, a register, is known to contain a value already truncated to MODE. In this case we can use a subreg to refer to the truncated value even though in the generic case we would need an explicit truncation.
References i2.
rtx remove_death  (  ) 
Remove register number REGNO from the dead registers list of INSN. Return the note used to record the death, if there was one.
References cleanup_cfg(), get_insns(), rebuild_jump_labels(), timevar_pop(), and timevar_push().

static 
Try combining insns through substitution.
Combining insns may have turned an indirect jump into a direct jump. Rebuild the JUMP_LABEL fields of jumping instructions.
Referenced by move_deaths().

static 
See if X and Y are equal for the purposes of seeing if we can rewrite an assignment as a field assignment.
Check for a paradoxical SUBREG of a MEM compared with the MEM. Note that all SUBREGs of MEM are paradoxical; otherwise they would have been rewritten.
We used to see if get_last_value of X and Y were the same but that's not correct. In one direction, we'll cause the assignment to have the wrong destination and in the case, we'll import a register into this insn that might have already have been dead. So fail if none of the above cases are true.
References reg_stat_struct::last_set_sign_bit_copies.

static 
Called via note_stores. If X is a pseudo that is narrower than HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. If we are setting only a portion of X and we can't figure out what portion, assume all bits will be used since we don't know what will be happening. Similarly, set how many bits of X are known to be copies of the sign bit at all locations in the function. This is the smallest number implied by any set of X.
If this register is undefined at the start of the file, we can't say what its contents were.
If this register is being initialized using itself, and the register is uninitialized in this basic block, and there are no LOG_LINKS which set the register, then part of the register is uninitialized. In that case we can't assume anything about the number of nonzero bits. ??? We could do better if we checked this in reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we could avoid making assumptions about the insn which initially sets the register, while still using the information in other insns. We would have to be careful to check every insn involved in the combination.
If this is a complex assignment, see if we can convert it into a simple assignment.
If this is a simple assignment, or we have a paradoxical SUBREG, set what we know about X.
If X is narrower than a word and SRC is a nonnegative constant that would appear negative in the mode of X, signextend it for use in reg_stat[].nonzero_bits because some machines (maybe most) will actually do the signextension and this is the conservative approach. ??? For 2.5, try to tighten up the MD files in this regard instead of this kludge.
Don't call nonzero_bits if it cannot change anything.
References find_reg_note(), insn_nothrow_p(), next_active_insn(), reg_set_between_p(), SET, and side_effects_p().

static 

static 
Set up any promoted values for incoming argument registers.
Only continue if the incoming argument is in a register.
Determine, if possible, whether all call sites of the current function lie within the current compilation unit. (This does take into account the exporting of a function via taking its address, and so forth.)
The mode and signedness of the argument before any promotions happen (equal to the mode of the pseudo holding it at that stage).
The mode and signedness of the argument after any source language and TARGET_PROMOTE_PROTOTYPESdriven promotions.
The mode and signedness of the argument as it is actually passed, after any TARGET_PROMOTE_FUNCTION_ARGSdriven ABI promotions.
The mode of the register in which the argument is being passed.
Eliminate sign extensions in the callee when: (a) A mode promotion has occurred;
(b) The mode of the register is the same as the mode of the argument as it is passed;
(c) There's no language level extension;
(c.1) All callers are from the current compilation unit. If that's the case we don't have to rely on an ABI, we only have to know what we're generating right now, and we know that we will do the mode1 to mode2 promotion with the given sign.
(c.2) The combination of the two promotions is useful. This is true when the signs match, or if the first promotion is unsigned. In the later case, (sign_extend (zero_extend x)) is the same as (zero_extend (zero_extend x)), so make sure to force UNS3 true.
Record that the value was promoted from mode1 to mode3, so that any sign extension at the head of the current function may be eliminated.

static 
We have X, a logical `and' of VAROP with the constant CONSTOP, to be done in MODE. Return an equivalent form, if different from X. Otherwise, return X. If X is zero, we are to always construct the equivalent form.
Referenced by simplify_set().

static 
Simplify a logical `and' of VAROP with the constant CONSTOP, to be done in MODE. Return an equivalent form, if different from (and VAROP (const_int CONSTOP)). Otherwise, return NULL_RTX.
Simplify VAROP knowing that we will be only looking at some of the bits in it. Note by passing in CONSTOP, we guarantee that the bits not set in CONSTOP are not significant and will never be examined. We must ensure that is the case by explicitly masking out those bits before returning.
If VAROP is a CLOBBER, we will fail so return it.
If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP to VAROP and return the new constant.
See what bits may be nonzero in VAROP. Unlike the general case of a call to nonzero_bits, here we don't care about bits outside MODE.
Turn off all bits in the constant that are known to already be zero. Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS which is tested below.
If we don't have any bits left, return zero.
If VAROP is a NEG of something known to be zero or 1 and CONSTOP is a power of two, we can replace this with an ASHIFT.
If VAROP is an IOR or XOR, apply the AND to both branches of the IOR or XOR, then try to apply the distributive law. This may eliminate operations if either branch can be simplified because of the AND. It may also make some cases more complex, but those cases probably won't match a pattern either with or without this.
If VAROP is PLUS, and the constant is a mask of low bits, distribute the AND and see if one of the operands simplifies to zero. If so, we may eliminate it.
Make a SUBREG if necessary. If we can't make it, fail.
If we are only masking insignificant bits, return VAROP.
Otherwise, return an AND.
References exact_log2(), and simplify_gen_binary().

static 
Try to simplify a comparison between OP0 and a constant OP1, where CODE is the comparison code that will be tested, into a (CODE OP0 const0_rtx) form. The result is a possibly different comparison code to use. *POP1 may be updated.
Get the constant we are comparing against and turn off all bits not on in our mode.
If we are comparing against a constant power of two and the value being compared can only have that single bit nonzero (e.g., it was `and'ed with that bit), we can replace this with a comparison with zero.
Similarly, if we are comparing a value known to be either 1 or 0 with 1, change it to the opposite comparison against zero.
Do some canonicalizations based on the comparison code. We prefer comparisons against zero and then prefer equality comparisons. If we can reduce the size of a constant, we will do that too.
< C is equivalent to <= (C  1)
... fall through to LE case below.
<= C is equivalent to < (C + 1); we do this for C < 0
If we are doing a <= 0 comparison on a value known to have a zero sign bit, we can replace this with == 0.
>= C is equivalent to > (C  1).
... fall through to GT below.
> C is equivalent to >= (C + 1); we do this for C < 0.
If we are doing a > 0 comparison on a value known to have a zero sign bit, we can replace this with != 0.
< C is equivalent to <= (C  1).
... fall through ...
(unsigned) < 0x80000000 is equivalent to >= 0.
unsigned <= 0 is equivalent to == 0
(unsigned) <= 0x7fffffff is equivalent to >= 0.
>= C is equivalent to > (C  1).
... fall through ...
(unsigned) >= 0x80000000 is equivalent to < 0.
unsigned > 0 is equivalent to != 0
(unsigned) > 0x7fffffff is equivalent to < 0.

static 
Simplify a comparison between *POP0 and *POP1 where CODE is the comparison code that will be tested. The result is a possibly different comparison code to use. *POP0 and *POP1 may be updated. It is possible that we might detect that a comparison is either always true or always false. However, we do not perform general constant folding in combine, so this knowledge isn't useful. Such tautologies should have been detected earlier. Hence we ignore all such cases.
Try a few ways of applying the same transformation to both operands.
The test below this one won't handle SIGN_EXTENDs on these machines, so check specially.
If both operands are the same constant shift, see if we can ignore the shift. We can if the shift is a rotate or if the bits shifted out of this shift are known to be zero for both inputs and if the type of comparison is compatible with the shift.
If both operands are AND's of a paradoxical SUBREG by constant, the SUBREGs are of the same mode, and, in both cases, the AND would be redundant if the comparison was done in the narrower mode, do the comparison in the narrower mode (e.g., we are AND'ing with 1 and the operand's possibly nonzero bits are 0xffffff01; in that case if we only care about QImode, we don't need the AND). This case occurs if the output mode of an scc insn is not SImode and STORE_FLAG_VALUE == 1 (e.g., the 386). Similarly, check for a case where the AND's are ZERO_EXTEND operations from some narrower mode even though a SUBREG is not present.
The resulting comparison is always unsigned since we masked off the original sign bit.
If both operands are NOT, we can strip off the outer operation and adjust the comparison code for swapped operands; similarly for NEG, except that this must be an equality comparison.
If the first operand is a constant, swap the operands and adjust the comparison code appropriately, but don't do this if the second operand is already a constant integer.
We now enter a loop during which we will try to simplify the comparison. For the most part, we only are concerned with comparisons with zero, but some things may really be comparisons with zero but not start out looking that way.
We only want to handle integral modes. This catches VOIDmode, CCmode, and the floatingpoint modes. An exception is that we can handle VOIDmode if OP0 is a COMPARE or a comparison operation.
Try to simplify the compare to constant, possibly changing the comparison op, and/or changing op1 to zero.
Compute some predicates to simplify code below.
If this is a sign bit comparison and we can do arithmetic in MODE, say that we will only be needing the sign bit of OP0.
Now try cases based on the opcode of OP0. If none of the cases does a "continue", we exit this loop immediately after the switch.
If we are extracting a single bit from a variable position in a constant that has only a single bit set and are comparing it with zero, we can convert this into an equality comparison between the position and the location of the single bit.
Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might have already reduced the shift count modulo the word size.
Result is nonzero iff shift count is equal to I.
... fall through ...
If testing for equality, we can take the NOT of the constant.
If just looking at the sign bit, reverse the sense of the comparison.
If testing for equality, we can take the NEG of the constant.
The remaining cases only apply to comparisons with zero.
When X is ABS or is known positive, (neg X) is < 0 if and only if X != 0.
If we have NEG of something whose two highorder bits are the same, we know that "(a) < 0" is equivalent to "a > 0".
If we are testing equality and our count is a constant, we can perform the inverse operation on our RHS.
If we are doing a < 0 or >= 0 comparison, it means we are testing a particular bit. Convert it to an AND of a constant of that bit. This will be converted into a ZERO_EXTRACT.
Fall through.
ABS is ignorable inside an equality comparison with zero.
Can simplify (compare (zero/sign_extend FOO) CONST) to (compare FOO CONST) if CONST fits in FOO's mode and we are either testing inequality or have an unsigned comparison with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. But don't do it if we don't have a compare insn of the given mode, since we'd have to revert it later on, and then we wouldn't know whether to sign or zeroextend.
Check for the case where we are comparing A  C1 with C2, that is (subreg:MODE (plus (A) (C1))) op (C2) with C1 a constant, and try to lift the SUBREG, i.e. to do the comparison in the wider mode. One of the following two conditions must be true in order for this to be valid: 1. The mode extension results in the same bit pattern being added on both sides and the comparison is equality or unsigned. As C2 has been truncated to fit in MODE, the pattern can only be all 0s or all 1s. 2. The mode extension results in the sign bit being copied on each side. The difficulty here is that we have predicates for A but not for (A  C1) so we need to check that C1 is within proper bounds so as to perturbate A as little as possible.
(A  C1) zeroextends if it is positive and signextends if it is negative, C2 both zero and signextends.
(A  C1) signextends if it is positive and 1extends if it is negative, C2 both sign and 1extends.
(A  C1) always signextends, like C2.
If the inner mode is narrower and we are extracting the low part, we can treat the SUBREG as if it were a ZERO_EXTEND.
Fall through
... fall through ...
(eq (plus X A) B) > (eq X (minus B A)). We can only do this for equality comparisons due to pathological cases involving overflows.
(plus (abs X) (const_int 1)) is < 0 if and only if X == 0.
We used to optimize signed comparisons against zero, but that was incorrect. Unsigned comparisons against zero (GTU, LEU) arrive here as equality comparisons, or (GEU, LTU) are optimized away. No need to specialcase them.
(eq (minus A B) C) > (eq A (plus B C)) or (eq B (minus A C)), whichever simplifies. We can only do this for equality comparisons due to pathological cases involving overflows.
The sign bit of (minus (ashiftrt X C) X), where C is the number of bits in X minus 1, is one iff X > 0.
(eq (xor A B) C) > (eq A (xor B C)). This is a simplification if C is zero or B is a constant.
We can't do anything if OP0 is a condition code value, rather than an actual data value.
Get the two operands being compared.
Check for the cases where we simply want the result of the earlier test or the opposite of that result.
The sign bit of (ior (plus X (const_int 1)) X) is nonzero iff X <= 0.
Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This will be converted to a ZERO_EXTRACT later.
If we are comparing (and (lshiftrt X C1) C2) for equality with zero and X is a comparison and C1 and C2 describe only bits set in STORE_FLAG_VALUE, we can compare with X.
If we are doing an equality comparison of an AND of a bit equal to the sign bit, replace this with a LT or GE comparison of the underlying value.
If this AND operation is really a ZERO_EXTEND from a narrower mode, the constant fits within that mode, and this is either an equality or unsigned comparison, try to do this comparison in the narrower mode. Note that in: (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0)) > (ne:DI (reg:SI 4) (const_int 0)) unless TRULY_NOOP_TRUNCATION allows it or the register is known to hold a value of the required mode the transformation is invalid.
If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits in both M1 and M2 and the SUBREG is either paradoxical or represents the low part, permute the SUBREG and the AND and try again.
Require an integral mode, to avoid creating something like (AND:SF ...).
It is unsafe to commute the AND into the SUBREG if the SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is not defined. As originally written the upper bits have a defined value due to the AND operation. However, if we commute the AND inside the SUBREG then they no longer have defined values and the meaning of the code has been changed.
Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).
Convert (ne (and (lshiftrt (not X)) 1) 0) to (eq (and (lshiftrt X) 1) 0). Also handle the case where (not X) is expressed using xor.
If we have (compare (ashift FOO N) (const_int C)) and the high order N bits of FOO (N+1 if an inequality comparison) are known to be zero, we can do this by comparing FOO with C shifted right N bits so long as the loworder N bits of C are zero.
We must perform a logical shift, not an arithmetic one, as we want the top N bits of C to be zero.
If we are doing a sign bit comparison, it means we are testing a particular bit. Convert it to the appropriate AND.
If this an equality comparison with zero and we are shifting the low bit to the sign bit, we can convert this to an AND of the loworder bit.
If this is an equality comparison with zero, we can do this as a logical shift, which might be much simpler.
If OP0 is a sign extension and CODE is not an unsigned comparison, do the comparison in a narrower mode.
Likewise if OP0 is a PLUS of a sign extension with a constant, which is usually represented with the PLUS between the shifts.
... fall through ...
If we have (compare (xshiftrt FOO N) (const_int C)) and the low order N bits of FOO are known to be zero, we can do this by comparing FOO with C shifted left N bits so long as no overflow occurs. Even if the low order N bits of FOO aren't known to be zero, if the comparison is >= or < we can use the same optimization and for > or <= by setting all the low order N bits in the comparison constant.
If the shift was logical, then we must make the condition unsigned.
If we are using this shift to extract just the sign bit, we can replace this with an LT or GE comparison.
Now make any compound operations involved in this comparison. Then, check for an outmost SUBREG on OP0 that is not doing anything or is paradoxical. The latter transformation must only be performed when it is known that the "extra" bits will be the same in op0 and op1 or that they don't matter. There are three cases to consider: 1. SUBREG_REG (op0) is a register. In this case the bits are don't care bits and we can assume they have any convenient value. So making the transformation is safe. 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. In this case the upper bits of op0 are undefined. We should not make the simplification in that case as we do not know the contents of those bits. 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not UNKNOWN. In that case we know those bits are zeros or ones. We must also be sure that they are the same as the upper bits of op1. We can never remove a SUBREG for a nonequality comparison because the sign bit is in a different place in the underlying object.
For paradoxical subregs, allow case 1 as above. Case 3 isn't implemented.
We now do the opposite procedure: Some machines don't have compare insns in all modes. If OP0's mode is an integer mode smaller than a word and we can't do a compare in that mode, see if there is a larger mode for which we can do the compare. There are a number of cases in which we can use the wider mode.
If this is a test for negative, we can make an explicit test of the sign bit. Test this first so we can use a paradoxical subreg to extend OP0.
If the only nonzero bits in OP0 and OP1 are those in the narrower mode and this is an equality or unsigned comparison, we can use the wider mode. Similarly for signextended values, in which case it is true for all comparisons.
If OP0 is an AND and we don't have an AND in MODE either, make a new AND in the proper mode.
We may have changed the comparison operands. Recanonicalize.
If this machine only supports a subset of valid comparisons, see if we can convert an unsupported one into a supported one.
References simplify_shift_const().

static 
Simplify X, an IF_THEN_ELSE expression. Return the new expression.
Simplify storing of the truth value.
Also when the truth value has to be reversed.
Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used in it is being compared against certain values. Get the true and false comparisons and see if that says anything about the value of each arm.
If FALSE_CODE is EQ, swap the codes and arms.
If we are comparing against zero and the expression being tested has only a single bit that might be nonzero, that is its value when it is not equal to zero. Similarly if it is known to be 1 or 0.
Now simplify an arm if we know the value of the register in the branch and it is used in the arm. Be careful due to the potential of locallyshared RTL.
If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be reversed, do so to avoid needing two sets of patterns for subtractandbranch insns. Similarly if we have a constant in the true arm, the false arm is the same as the first operand of the comparison, or the false arm is more complicated than the true arm.
It is possible that the conditional has been simplified out.
If the two arms are identical, we don't need the comparison.
Convert a == b ? b : a to "a".
Look for cases where we have (abs x) or (neg (abs X)).
Look for MIN or MAX.
If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its second operand is zero, this can be done as (OP Z (mult COND C2)) where C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or SIGN_EXTEND as long as Z is already extended (so we don't destroy it). We can do this kind of thing in some cases when STORE_FLAG_VALUE is neither 1 or 1, but it isn't worth checking for.
If an identityzero op is commutative, check whether there would be a match if we swapped the operands.
If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 1 and C1 is a single bit or A is known to be 0 or 1 and C1 is the negation of a single bit, we can convert this operation to a shift. We can actually do this more generally, but it doesn't seem worth it.
(IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.
References simplify_rtx().

static 
Simplify, X, and AND, IOR, or XOR operation, and return the simplified result.
We can call simplify_and_const_int only if we don't lose any (sign) bits when converting INTVAL (op1) to "unsigned HOST_WIDE_INT".
If we have any of (and (ior A B) C) or (and (xor A B) C), apply the distributive law and then the inverse distributive law to see if things simplify.
If we have (ior (and A B) C), apply the distributive law and then the inverse distributive law to see if things simplify.

static 
Simplify X, a SET expression. Return the new expression.
(set (pc) (return)) gets written as (return).
Now that we know for sure which bits of SRC we are using, see if we can simplify the expression for the object knowing that we only need the loworder bits.
If we are setting CC0 or if the source is a COMPARE, look for the use of the comparison result and try to simplify it unless we already have used undobuf.other_insn.
Attempt to simplify CC user.
Convert X into a noop move.
Simplify our comparison, if possible.
If this machine has CC modes other than CCmode, check to see if we need to use a different CC mode here.
If the mode changed, we have to change SET_DEST, the mode in the compare, and the mode in the place SET_DEST is used. If SET_DEST is a hard register, just build new versions with the proper mode. If it is a pseudo, we lose unless it is only time we set the pseudo, in which case we can safely change its mode.
If the code changed, we have to build a new comparison in undobuf.other_insn.
If the only change we made was to change an EQ into an NE or vice versa, OP0 has only one bit that might be nonzero, and OP1 is zero, check if changing the user of the condition code will produce a valid insn. If it won't, we can keep the original code in that insn by surrounding our operation with an XOR.
Otherwise, if we didn't previously have a COMPARE in the correct mode, we need one.
Otherwise, update the COMPARE if needed.
Get SET_SRC in a form where we have placed back any compound expressions. Then do the checks below.
If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, and X being a REG or (subreg (reg)), we may be able to convert this to (set (subreg:m2 x) (op)). We can always do this if M1 is narrower than M2 because that means that we only care about the low bits of the result. However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot perform a narrower operation than requested since the highorder bits will be undefined. On machine where it is defined, this transformation is safe as long as M1 and M2 have the same number of words.
If we have (set (cc0) (subreg ...)), we try to remove the subreg in SRC.
Here we make sure that we don't have a sign bit on.
If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this would require a paradoxical subreg. Replace the subreg with a zero_extend to avoid the reload that would otherwise be required.
If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we are comparing an item known to be 0 or 1 against 0, use a logical operation instead. Check for one of the arms being an IOR of the other arm with some value. We compute three terms to be IOR'ed together. In practice, at most two will be nonzero. Then we do the IOR's.
If either SRC or DEST is a CLOBBER of (const_int 0), make this whole thing fail.
Convert this into a field assignment operation, if possible.
References expand_compound_operation(), HOST_BITS_PER_WIDE_INT, len, nonzero_bits(), optimize_this_for_speed_p, set_src_cost(), simplify_and_const_int(), simplify_shift_const(), and subreg_lowpart_p().

static 
Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. The result of the shift is RESULT_MODE. If we cannot simplify it, return X or, if it is NULL, synthesize the expression with simplify_gen_binary. Otherwise, return a simplified value. The shift is normally computed in the widest mode we find in VAROP, as long as it isn't a different number of words than RESULT_MODE. Exceptions are ASHIFTRT and ROTATE, which are always done in their original mode.
Referenced by simplify_comparison(), and simplify_set().

static 
Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind of shift. The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot simplify it. Otherwise, return a simplified value. The shift is normally computed in the widest mode we find in VAROP, as long as it isn't a different number of words than RESULT_MODE. Exceptions are ASHIFTRT and ROTATE, which are always done in their original mode.
We form (outer_op (code varop count) (outer_const)).
Make sure and truncate the "natural" shift on the way in. We don't want to do this inside the loop as it makes it more difficult to combine shifts.
If we were given an invalid count, don't do anything except exactly what was requested.
Unless one of the branches of the `if' in this loop does a `continue', we will `break' the loop after the `if'.
If we have an operand of (clobber (const_int 0)), fail.
Convert ROTATERT to ROTATE.
Handle cases where the count is greater than the size of the mode minus 1. For ASHIFT, use the size minus one as the count (this can occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, take the count modulo the size. For other shifts, the result is zero. Since these shifts are being produced by the compiler by combining multiple operations, each of which are defined, we know what the result is supposed to be.
We can't simply return zero because there may be an outer op.
If we discovered we had to complement VAROP, leave. Making a NOT here would cause an infinite loop.
An arithmetic right shift of a quantity known to be 1 or 0 is a noop.
If we are doing an arithmetic right shift and discarding all but the sign bit copies, this is equivalent to doing a shift by the bitsize minus one. Convert it into that shift because it will often allow other simplifications.
We simplify the tests below and elsewhere by converting ASHIFTRT to LSHIFTRT if we know the sign bit is clear. `make_compound_operation' will convert it to an ASHIFTRT for those machines (such as VAX) that don't have an LSHIFTRT.
If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH minus the width of a smaller mode, we can do this with a SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.
If VAROP is a SUBREG, strip it as long as the inner operand has the same number of words as what we've seen so far. Then store the widest mode in MODE.
Some machines use MULT instead of ASHIFT because MULT is cheaper. But it is still better on those machines to merge two shifts into one.
Similar, for when divides are cheaper.
If we are extracting just the sign bit of an arithmetic right shift, that shift is not needed. However, the sign bit of a wider mode may be different from what would be interpreted as the sign bit in a narrower mode, so, if the result is narrower, don't discard the shift.
... fall through ...
Here we have two nested shifts. The result is usually the AND of a new shift with a mask. We compute the result below.
We have one common special case. We can't do any merging if the inner code is an ASHIFTRT of a smaller mode. However, if we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) with C2 == GET_MODE_BITSIZE (M1)  GET_MODE_BITSIZE (M2), we can convert it to (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1). This simplifies certain SIGN_EXTEND operations.
C3 has the loworder C1 bits zero.
If this was (ashiftrt (ashift foo C1) C2) and FOO has more than C1 highorder bits equal to the sign bit, we can convert this to either an ASHIFT or an ASHIFTRT depending on the two counts. We cannot do this if VAROP's mode is not SHIFT_MODE.
There are some cases we can't do. If CODE is ASHIFTRT, we can only do this if FIRST_CODE is also ASHIFTRT. We can't do the case when CODE is ROTATE and FIRST_CODE is ASHIFTRT. If the mode of this shift is not the mode of the outer shift, we can't do this if either shift is a right shift or ROTATE. Finally, we can't do any of these if the mode is too wide unless the codes are the same. Handle the case where the shift codes are the same first.
To compute the mask to apply after the shift, shift the nonzero bits of the inner shift the same way the outer shift will.
Give up if we can't compute an outer operation to use.
If the shifts are in the same direction, we add the counts. Otherwise, we subtract them.
If COUNT is positive, the new shift is usually CODE, except for the two exceptions below, in which case it is FIRST_CODE. If the count is negative, FIRST_CODE should always be used
If we have (A << B << C) for any shift, we can convert this to (A << C << B). This wins if A is a constant. Only try this if B is not a constant.
Make this fit the case below.
If we have (xshiftrt (ior (plus X (const_int 1)) X) C) with C the size of VAROP  1 and the shift is logical if STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is 1, we have an (le X 0) operation. If we have an arithmetic shift and STORE_FLAG_VALUE is 1 or we have a logical shift with STORE_FLAG_VALUE of 1, we have a (neg (le X 0)) operation.
If we have (shift (logical)), move the logical to the outside to allow it to possibly combine with another logical and the shift to combine with another shift. This also canonicalizes to what a ZERO_EXTRACT looks like. Also, some machines have (and (shift)) insns.
We can't do this if we have (ashiftrt (xor)) and the constant has its sign bit set in shift_mode.
If we can't do that, try to simplify the shift in each arm of the logical expression, make a new logical expression, and apply the inverse distributive law. This also can't be done for some (ashiftrt (xor)).
Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE says that the sign bit can be tested, FOO has mode MODE, C is GET_MODE_PRECISION (MODE)  1, and FOO has only its loworder bit that may be nonzero.
(lshiftrt (neg A) C) where A is either 0 or 1 and C is one less than the number of bits in the mode is equivalent to A.
NEG commutes with ASHIFT since it is multiplication. Move the NEG outside to allow shifts to combine.
(lshiftrt (plus A 1) C) where A is either 0 or 1 and C is one less than the number of bits in the mode is equivalent to (xor A 1).
If we have (xshiftrt (plus FOO BAR) C), and the only bits that might be nonzero in BAR are those being shifted out and those bits are known zero in FOO, we can replace the PLUS with FOO. Similarly in the other operand order. This code occurs when we are computing the size of a variablesize array.
(ashift (plus foo C) N) is (plus (ashift foo N) C').
Check for 'PLUS signbit', which is the canonical form of 'XOR signbit', and attempt to change the PLUS to an XOR and move it to the outer operation as is done above in the AND/IOR/XOR case leg for shift(logical). See details in logical handling above for reasoning in doing so.
If we have (xshiftrt (minus (ashiftrt X C)) X) C) with C the size of VAROP  1 and the shift is logical if STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is 1, we have a (gt X 0) operation. If the shift is arithmetic with STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == 1, we have a (neg (gt X 0)) operation.
Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) if the truncate does not affect the value.
We have now finished analyzing the shift. The result should be a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If OUTER_OP is nonUNKNOWN, it is an operation that needs to be applied to the result of the shift. OUTER_CONST is the relevant constant, but we must turn off all bits turned off in the shift.
Make a SUBREG if necessary. If we can't make it, fail.
If we have an outer operation and we just made a shift, it is possible that we could have simplified the shift were it not for the outer operation. So try to do the simplification recursively.
If we were doing an LSHIFTRT in a wider mode than it was originally, turn off all the bits that the shift would have turned off.
Do the remainder of the processing in RESULT_MODE.
If COMPLEMENT_P is set, we have to complement X before doing the outer operation.
This means that we have determined that the result is equivalent to a constant. This should be rare.

static 
Throughout X, replace FROM with TO, and return the result. The result is TO if X is FROM; otherwise the result is X, but its contents may have been modified. If they were modified, a record was made in undobuf so that undo_all will (among other things) return X to its original state. If the number of changes necessary is too much to record to undo, the excess changes are not made, so the result is invalid. The changes already made can still be undone. undobuf.num_undo is incremented for such changes, so by testing that the caller can tell whether the result is valid. `n_occurrences' is incremented each time FROM is replaced. IN_DEST is nonzero if we are processing the SET_DEST of a SET. IN_COND is nonzero if we are at the top level of a condition. UNIQUE_COPY is nonzero if each substitution must be unique. We do this by copying if `n_occurrences' is nonzero.
Two expressions are equal if they are identical copies of a shared RTX or if they are both registers with the same register number and mode.
If X and FROM are the same register but different modes, they will not have been seen as equal above. However, the log links code will make a LOG_LINKS entry for that case. If we do nothing, we will try to rerecognize our original insn and, when it succeeds, we will delete the feeding insn, which is incorrect. So force this insn not to match in this (rare) case.
If this is an object, we are done unless it is a MEM or LO_SUM, both of which may contain things that can be combined.
It is possible to have a subexpression appear twice in the insn. Suppose that FROM is a register that appears within TO. Then, after that subexpression has been scanned once by `subst', the second time it is scanned, TO may be found. If we were to scan TO here, we would find FROM within it and create a selfreferent rtl structure which is completely wrong.
Parallel asm_operands need special attention because all of the inputs are shared across the arms. Furthermore, unsharing the rtl results in recognition failures. Failure to handle this case specially can result in circular rtl. Solve this by doing a normal pass across the first entry of the parallel, and only processing the SET_DESTs of the subsequent entries. Ug.
If this substitution failed, this whole thing fails.
If this substitution failed, this whole thing fails.
We don't need to process a SET_DEST that is a register, CC0, or PC, so set up to skip this common case. All other cases where we want to suppress replacing something inside a SET_SRC are handled via the IN_DEST operand.
Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant.
If this substitution failed, this whole thing fails.
If this is a register being set, ignore it.
In general, don't install a subreg involving two modes not tieable. It can worsen register allocation, and can even make invalid reload insns, since the reg inside may need to be copied from in the outside mode, and that may be invalid if it is an fp reg copied in integer mode. We allow two exceptions to this: It is valid if it is inside another SUBREG and the mode of that SUBREG and the mode of the inside of TO is tieable and it is valid if X is a SET that copies FROM to CC0.
If we are in a SET_DEST, suppress most cases unless we have gone inside a MEM, in which case we want to simplify the address. We assume here that things that are actually part of the destination have their inner parts in the first expression. This is true for SUBREG, STRICT_LOW_PART, and ZERO_EXTRACT, which are the only things aside from REG and MEM that should appear in a SET_DEST.
If we found that we will have to reject this combination, indicate that by returning the CLOBBER ourselves, rather than an expression containing it. This will speed things up as well as prevent accidents where two CLOBBERs are considered to be equal, thus producing an incorrect simplification.
Check if we are loading something from the constant pool via float extension; in this case we would undo compress_float_constant optimization and degenerate constant load to an immediate value.
Try to simplify X. If the simplification changed the code, it is likely that further simplification will help, so loop, but limit the number of repetitions that will be performed.
If X is sufficiently simple, don't bother trying to do anything with it.
We no longer know the original mode of operand 0 since we have changed the form of X)
References const_true_rtx, reversed_comparison_code_parts(), simplify_gen_relational(), and simplify_gen_unary().

inlinestatic 
Convenience wrapper for the canonicalize_comparison target hook. Target hooks cannot use enum rtx_code.
References SET.

static 
Try to combine the insns I0, I1 and I2 into I3. Here I0, I1 and I2 appear earlier than I3. I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into I3. If we are combining more than two insns and the resulting insn is not recognized, try splitting it into two insns. If that happens, I2 and I3 are retained and I1/I0 are pseudodeleted by turning them into a NOTE. Otherwise, I0, I1 and I2 are pseudodeleted. Return 0 if the combination does not work. Then nothing is changed. If we did the combination, return the insn at which combine should resume scanning. Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a new direct jump instruction. LAST_COMBINED_INSN is either I3, or some insn after I3 that has been I3 passed to an earlier try_combine within the same basic block.
New patterns for I3 and I2, respectively.
Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not dead.
Total number of SETs to put into I3.
Nonzero if I2's or I1's body now appears in I3.
INSN_CODEs for new I3, new I2, and user of condition code.
Contains I3 if the destination of I3 is used in its source, which means that the old life of I3 is being killed. If that usage is placed into I2 and not in I3, a REG_DEAD note must be made.
SET_DEST and SET_SRC of I2, I1 and I0.
Copy of SET_SRC of I1 and I0, if needed.
Set if I2DEST was reused as a scratch register.
The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.
Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.
Notes that must be added to REG_NOTES in I3 and I2.
Notes that we substituted I3 into I2 instead of the normal case.
Notes that I1, I2 or I3 is a MULT operation.
Only try fourinsn combinations when there's high likelihood of success. Look for simple insns, such as loads of constants or binary operations involving a constant.
Exit early if one of the insns involved can't be used for combinations.
Reset the hard register usage information.
If multiple insns feed into one of I2 or I3, they can be in any order. To simplify the code below, reorder them in sequence.
First check for one important special case that the code below will not handle. Namely, the case where I1 is zero, I2 is a PARALLEL and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, we may be able to replace that destination with the destination of I3. This occurs in the common code where we compute both a quotient and remainder into a structure, in which case we want to do the computation directly into the structure to avoid registerregister copies. Note that this case handles both multiple sets in I2 and also cases where I2 has a number of CLOBBERs inside the PARALLEL. We make very conservative checks below and only try to handle the most common cases of this. For example, we only handle the case where I2 and I3 are adjacent to avoid making difficult register usage tests.
If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code below would need to check what is inside (and reg_overlap_mentioned_p doesn't support those codes anyway). Don't allow those destinations; the resulting insn isn't likely to be recognized anyway.
Make sure that the destination of I3, which we are going to substitute into one output of I2, is not used within another output of I2. We must avoid making this: (parallel [(set (mem (reg 69)) ...) (set (reg 69) ...)]) which is not welldefined as to order of actions. (Besides, reload can't handle output reloads for this.) The problem can also happen if the dest of I3 is a memory ref, if another dest in I2 is an indirect memory ref.
Replace the dest in I2 with our dest and make the resulting insn the new pattern for I3. Then skip to where we validate the pattern. Everything was set up above.
If I2 is setting a pseudo to a constant and I3 is setting some subpart of it to another constant, merge them by making a new constant.
If this is the low part, we're done.
Handle the case where inner is twice the size of outer.
Otherwise give up for now.
Replace the source in I2 with the new constant and make the resulting insn the new pattern for I3. Then skip to where we validate the pattern. Everything was set up above.
The dest of I3 has been replaced with the dest of I2.
If we have no I1 and I2 looks like: (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) (set Y OP)]) make up a dummy I1 that is (set Y OP) and change I2 to be (set (reg:CC X) (compare:CC Y (const_int 0))) (We can ignore any trailing CLOBBERs.) This undoes a previous combination and allows us to match a branchand decrement insn.
We make I1 with the same INSN_UID as I2. This gives it the same DF_INSN_LUID for value tracking. Our fake I1 will never appear in the insn stream so giving it the same INSN_UID as I2 will not cause a problem.
Verify that I2 and I1 are valid for combining.
Record whether I2DEST is used in I2SRC and similarly for the other cases. Knowing this will help in register status updating below.
For the earlier insns, determine which of the subsequent ones they feed.
Ensure that I3's pattern can be the destination of combines.
See if any of the insns is a MULT operation. Unless one is, we will reject a combination that is, since it must be slower. Be conservative here.
If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. We used to do this EXCEPT in one case: I3 has a postinc in an output operand. However, that exception can give rise to insns like mov r3,(r3)+ which is a famous insn on the PDP11 where the value of r3 used as the source was modeldependent. Avoid this sort of thing.
It's not the exception.
See if the SETs in I1 or I2 need to be kept around in the merged instruction: whenever the value set there is still needed past I3. For the SET in I2, this is easy: we see if I2DEST dies or is set in I3. For the SET in I1, we have two cases: if I1 and I2 independently feed into I3, the set in I1 needs to be kept around unless I1DEST dies or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set in I1 needs to be kept around unless I1DEST dies or is set in either I2 or I3. The same considerations apply to I0.
We are about to copy insns for the case where they need to be kept around. Check that they can be copied in the merged instruction.
If the set in I2 needs to be kept around, we must make a copy of PATTERN (I2), so that when we substitute I1SRC for I1DEST in PATTERN (I2), we are only substituting for the original I1DEST, not into an alreadysubstituted copy. This also prevents making selfreferential rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to I2DEST.
Substitute in the latest insn for the regs set by the earlier ones.
Many machines that don't use CC0 have insns that can both perform an arithmetic operation and set the condition code. These operations will be represented as a PARALLEL with the first element of the vector being a COMPARE of an arithmetic operation with the constant zero. The second element of the vector will set some pseudo to the result of the same arithmetic operation. If we simplify the COMPARE, we won't match such a pattern and so will generate an extra insn. Here we test for this case, where both the comparison and the operation result are needed, and make the PARALLEL by just replacing I2DEST in I3SRC with I2SRC. Later we will make the PARALLEL that contains I2.
Do the rest only if op1 is const0_rtx, which may be the result of simplification.
If a single use of the CC is found, prepare to modify it when SELECT_CC_MODE returns a new CCclass mode, or when the above simplify_compare_const() returned a new comparison operator. undobuf.other_insn is assigned the CC use insn when modifying it.
Cases for modifying the CCusing comparison.
??? Do we need to verify the zero rtx?
Replace cc_use_loc with entire new RTX.
Just replace the CC reg with a new mode.
Now we modify the current newpat: First, SET_DEST(newpat) is updated if the CC mode has been altered. For targets without SELECT_CC_MODE, this should be optimized away.
This is always done to propagate i2src into newpat.
Create new version of i2pat if needed; the below PARALLEL creation needs this to work correctly.
It is possible that the source of I2 or I1 may be performing an unneeded operation, such as a ZERO_EXTEND of something that is known to have the high part zero. Handle that case by letting subst look at the inner insns. Another way to do this would be to have a function that tries to simplify a single insn instead of merging two or more insns. We don't do this because of the potential of infinite loops and because of the potential extra memory required. However, doing it the way we are is a bit of a kludge and doesn't catch all cases. But only do this if fexpensiveoptimizations since it slows things down and doesn't usually win. This is not done in the COMPARE case above because the unmodified I2PAT is used in the PARALLEL and so a pattern with a modified I2SRC would not match.
Pass pc_rtx so no substitutions are done, just simplifications.
If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique copy of I2SRC each time we substitute it, in order to avoid creating selfreferential RTL when we will be substituting I1SRC for I1DEST later. Likewise if I0 feeds into I2, either directly or indirectly through I1, and I0DEST is in I0SRC.
Record whether I2's body now appears within I3's body.
If we already got a failure, don't try to do more. Otherwise, try to substitute I1 if we have it.
Check that an autoincrement sideeffect on I1 has not been lost. This happens if I1DEST is mentioned in I2 and dies there, and has disappeared from the new pattern.
Before we can do this substitution, we must redo the test done above (see detailed comments there) that ensures I1DEST isn't mentioned in any SETs in NEWPAT that are field assignments.
If the following substitution will modify I1SRC, make a copy of it for the case where it is substituted for I1DEST in I2PAT later.
If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique copy of I1SRC each time we substitute it, in order to avoid creating selfreferential RTL when we will be substituting I0SRC for I0DEST later.
Record whether I1's body now appears within I3's body.
Likewise for I0 if we have it.
If the following substitution will modify I0SRC, make a copy of it for the case where it is substituted for I0DEST in I1PAT later.
And a copy for I0DEST in I2PAT substitution.
Fail if an autoincrement sideeffect has been duplicated. Be careful to count all the ways that I2SRC and I1SRC can be used.
Fail if we tried to make a new register.
Fail if we couldn't do something and have a CLOBBER.
Fail if this new pattern is a MULT and we didn't have one before at the outer level.
If the actions of the earlier insns must be kept in addition to substituting them into the latest one, we must make a new PARALLEL for the latest insn to hold additional the SETs.
Note which hard regs this insn has as inputs.
If recog_for_combine fails, it strips existing clobbers. If we'll consider splitting this pattern, we might need these clobbers.
Is the result of combination a valid instruction?
If the result isn't valid, see if it is a PARALLEL of two SETs where the second SET's destination is a register that is unused and isn't marked as an instruction that might trap in an EH region. In that case, we just need the first SET. This can occur when simplifying a divmod insn. We *must* test for this case here because the code below that splits two independent SETs doesn't handle this case correctly when it updates the register status. It's pointless doing this if we originally had two sets, one from i3, and one from i2. Combining then splitting the parallel results in the original i2 again plus an invalid insn (which we delete). The net effect is only to move instructions around, which makes debug info less accurate. Also check the case where the first SET's destination is unused. That would not cause incorrect code, but does cause an unneeded insn to remain.
If we were combining three insns and the result is a simple SET with no ASM_OPERANDS that wasn't recognized, try to split it into two insns. There are two ways to do this. It can be split using a machinespecific method (like when you have an addition of a large constant) or by combine in the function find_split_point.
See if the MD file can split NEWPAT. If it can't, see if letting it use I2DEST as a scratch register will help. In the latter case, convert I2DEST to the mode of the source of NEWPAT if we can.
We can only use I2DEST as a scratch reg if it doesn't overlap any inputs of NEWPAT.
??? If I2DEST is not safe, and I1DEST exists, then it would be possible to try that as a scratch reg. This would require adding more code to make it work though.
First try to split using the original register as a scratch register.
If that didn't work, try changing the mode of I2DEST if we can.
If recog_for_combine has discarded clobbers, try to use them again for the split.
If I2 or I3 has multiple SETs, we won't know how to track register status, so don't use these insns. If I2's destination is used between I2 and I3, we also can't use these insns.
It is possible that both insns now set the destination of I3. If so, we must show an extra use of it.
If we can split it and use I2DEST, go ahead and see if that helps things be recognized. Verify that none of the registers are set between I2 and I3.
We need I2DEST in the proper mode. If it is a hard register or the only use of a pseudo, we can change its mode. Make sure we don't change a hard register to have a mode that isn't valid for it, or change the number of registers.
We can't overwrite I2DEST if its value is still used by NEWPAT.
*SPLIT may be part of I2SRC, so make sure we have the original expression around for later debug processing. We should not need I2SRC any more in other cases.
Get NEWDEST as a register in the proper mode. We have already validated that we can do this.
If *SPLIT is a (mult FOO (const_int pow2)), convert it to an ASHIFT. This can occur if it was inside a PLUS and hence appeared to be a memory address. This is a kludge.
Update split_code because we may not have a multiply anymore.
If *SPLIT is a paradoxical SUBREG, when we split it, it should be written as a ZERO_EXTEND.
Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's what it really is.
Attempt to split binary operators using arithmetic identities.
Split "X = Y op Y" as "Z = Y; X = Z op Z".
Split "((P op Q) op R) op S" where op is PLUS or MULT.
Split both "((X op Y) op X) op Y" and "((X op Y) op Y) op X" as "T op T" where T is "X op Y".
Split "((X op X) op Y) op Y)" as "T op T" where T is "X op Y".
recog_for_combine might have added CLOBBERs to newi2pat. Make sure NEWPAT does not depend on the clobbered regs.
If the split point was a MULT and we didn't have one before, don't use one now.
Check for a case where we loaded from memory in a narrow mode and then sign extended it, but we need both registers. In that case, we have a PARALLEL with both loads from the same memory location. We can split this into a load from memory followed by a registerregister copy. This saves at least one insn, more if register allocation can eliminate the copy. We cannot do this if the destination of the first assignment is a condition code register or cc0. We eliminate this case by making sure the SET_DEST and SET_SRC have the same mode. We cannot do this if the destination of the second assignment is a register that we have already assumed is zeroextended. Similarly for a SUBREG of such a register.
Similarly, check for a case where we have a PARALLEL of two independent SETs but we started with three insns. In this case, we can do the sets as two separate insns. This case occurs when some SET allows two other insns to combine, but the destination of that SET is still live.
Normally, it doesn't matter which of the two is done first, but the one that references cc0 can't be the second, and one which uses any regs/memory set in between i2 and i3 can't be first. The PARALLEL might also have been preexisting in i3, so we need to make sure that we won't wrongly hoist a SET to i2 that would conflict with a death note present in there.
recog_for_combine might have added CLOBBERs to newi2pat. Make sure NEWPAT does not depend on the clobbered regs.
If it still isn't recognized, fail and change things back the way they were.
Is the result a reasonable ASM_OPERANDS?
If we had to change another insn, make sure it is valid also.
If I2 is the CC0 setter and I3 is the CC0 user then check whether they are adjacent to each other or not.
Only allow this combination if insn_rtx_costs reports that the replacement instructions are cheaper than the originals.
Temporarily revert mode back.
If we used i2dest as a scratch register with a different mode, substitute it for the original i2src while its original mode is temporarily restored, and then clear i2scratch so that we don't do it again later.
Put back the new mode.
We're dealing with a reg that changed mode but not meaning, so we want to turn it into a subreg for the new mode. However, because of REG sharing and because its mode had already changed, we have to do it in two steps. First, replace any debug uses of reg, with its original mode temporarily restored, with this copy we have created; then, replace the copy with the SUBREG of the original shared reg, once again changed to the new mode.
If we will be able to accept this, we have made a change to the destination of I3. This requires us to do a few adjustments.
We now know that we can do this combination. Merge the insns and update the status of registers and LOG_LINKS.
If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they are still valid. Then add any nonduplicate notes added by recog_for_combine.
I3 now uses what used to be its destination and which is now I2's destination. This requires us to do a few adjustments.
We need a LOG_LINK from I3 to I2. But we used to have one, so we still will. However, some later insn might be using I2's dest and have a LOG_LINK pointing at I3. We must remove this link. The simplest way to remove the link is to point it at I1, which we know will be a NOTE.
newi2pat is usually a SET here; however, recog_for_combine might have added some clobbers.
Compute which registers we expect to eliminate. newi2pat may be setting either i3dest or i2dest, so we must check it. Also, i1dest may be the same as i3dest, in which case newi2pat may be setting i1dest.
Get the old REG_NOTES and LOG_LINKS from all our insns and clear them.
Ensure that we do not have something that should not be shared but occurs multiple times in the new insns. Check this by first resetting all the `used' flags and then copying anything is shared.
I2SRC must still be meaningful at this point. Some splitting operations can invalidate I2SRC, but those operations do not apply to calls.
We had one special case above where I2 had more than one set and we replaced a destination of one of those sets with the destination of I3. In that case, we have to update LOG_LINKS of insns later in this basic block. Note that this (expensive) case is rare. Also, in this case, we must pretend that all REG_NOTEs for I2 actually came from I3, so that REG_UNUSED notes from I2 will be properly handled.
Get death notes for everything that is now used in either I3 or I2 and used to die in a previous insn. If we built two new patterns, move from I1 to I2 then I2 to I3 so that we get the proper movement on registers that I2 modifies.
Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.
Distribute any notes added to I2 or I3 by recog_for_combine. We know these are REG_UNUSED and want them to go to the desired insn, so we always pass it as i3.
If I3DEST was used in I3SRC, it really died in I3. We may need to put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets I3DEST, the death must be somewhere before I2, not I3. If we passed I3 in that case, it might delete I2. Similarly for I2 and I1. Show an additional death due to the REG_DEAD note we make here. If we discard it in distribute_notes, we will decrement it again.
The insn that used to set this register doesn't exist, and this life of the register may not exist either. See if one of I3's links points to an insn that sets I2DEST. If it does, that is now the last known value for I2DEST. If we don't update this and I2 set the register to a value that depended on its old contents, we will get confused. If this insn is used, thing will be set correctly in combine_instructions.
If the reg formerly set in I2 died only once and that was in I3, zero its use count so it won't make `reload' do any work.
Update reg_stat[].nonzero_bits et al for any changes that may have been made to this insn. The order is important, because newi2pat can affect nonzero_bits of newpat.
Set new_direct_jump_p if a new return or simple jump instruction has been created. Adjust the CFG accordingly.
A noop might also need cleaning up of CFG, if it comes from the simplification of a jump.
References combine_merges, dead_or_set_p(), subst_insn, and subst_low_luid.

static 
A helper to simplify_shift_const_1 to determine the mode we can perform the shift in. The original shift operation CODE is performed on OP in ORIG_MODE. Return the wider mode MODE if we can perform the operation in that mode. Return ORIG_MODE otherwise. We can also assume that the result of the shift is subject to operation OUTER_CODE with operand OUTER_CONST.
In general we can't perform in wider mode for right shift and rotate.
We can still widen if the bits brought in from the left are identical to the sign bit of ORIG_MODE.
Similarly here but with zero bits.
We can also widen if the bits brought in will be masked off. This operation is performed in ORIG_MODE.
fall through

static 
Undo all the modifications recorded in undobuf.

static 
We've committed to accepting the changes we made. Move all of the undos to the free list.
References find_split_point(), gen_int_mode(), and HOST_WIDE_INT.

static 
Check for any register or memory mentioned in EQUIV that is not mentioned in EXPR. This is used to restrict EQUIV to "specializations" of EXPR where some registers may have been replaced by constants.

static 

static 
Subroutine of unmentioned_reg_p and callback from for_each_rtx. Check whether the expression pointer to by LOC is a register or memory, and if so return 1 if it isn't mentioned in the rtx EXPR. Otherwise return zero.

static 
Delete the unconditional jump INSN and adjust the CFG correspondingly. Note that the INSN should be deleted *after* removing dead edges, so that the kept edge is the fallthrough edge for a (set (pc) (pc)) but not for a (set (pc) (label_ref FOO)).
Remove barriers from the footer if there are any.
References reg_overlap_mentioned_p(), and SET.

static 

static 
Utility function for following routine. Called when X is part of a value being stored into last_set_value. Sets last_set_table_tick for each register mentioned. Similar to mention_regs in cse.c
Check for identical subexpressions. If x contains identical subexpression we only have to traverse one of them.
Note that at this point x1 has already been processed.
If x0 and x1 are identical then there is no need to process x0.
If x0 is identical to a subexpression of x1 then while processing x1, x0 has already been processed. Thus we are done with x.
If x1 is identical to a subexpression of x0 then we still have to process the rest of x0.
References find_regno_note(), and remove_note().

static 

static 
Return nonzero if expression X refers to a REG or to memory that is set in an instruction more recent than FROM_LUID.
Don't allow uses of the stack pointer to be moved, because we don't know whether the move crosses a push insn.
References alloc_reg_note(), dead_or_set_p(), dead_or_set_regno_p(), distribute_notes(), find_regno_fusage(), refers_to_regno_p(), reg_bitfield_target_p(), regno_reg_rtx, and this_basic_block.

static 
This is an insn to which a LOG_LINKS entry has been added. If this insn is the earlier than I2 or I3, combine should rescan starting at that location.

static 
@verbatim
Optimize by combining instructions for GNU compiler. Copyright (C) 19872013 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see http://www.gnu.org/licenses/.
This module is essentially the "combiner" phase of the U. of Arizona Portable Optimizer, but redone to work on our liststructured representation for RTL instead of their string representation. The LOG_LINKS of each insn identify the most recent assignment to each REG used in the insn. It is a list of previous insns, each of which contains a SET for a REG that is used in this insn and not used or set in between. LOG_LINKs never cross basic blocks. They were set up by the preceding pass (lifetime analysis). We try to combine each pair of insns joined by a logical link. We also try to combine triplets of insns A, B and C when C has a link back to B and B has a link back to A. Likewise for a small number of quadruplets of insns A, B, C and D for which there's high likelihood of of success. LOG_LINKS does not have links for use of the CC0. They don't need to, because the insn that sets the CC0 is always immediately before the insn that tests it. So we always regard a branch insn as having a logical link to the preceding insn. The same is true for an insn explicitly using CC0. We check (with use_crosses_set_p) to avoid combining in such a way as to move a computation to a place where its value would be different. Combination is done by mathematically substituting the previous insn(s) values for the regs they set into the expressions in the later insns that refer to these regs. If the result is a valid insn for our target machine, according to the machine description, we install it, delete the earlier insns, and update the data flow information (LOG_LINKS and REG_NOTES) for what we did. There are a few exceptions where the dataflow information isn't completely updated (however this is only a local issue since it is regenerated before the next pass that uses it):  reg_live_length is not updated  reg_n_refs is not adjusted in the rare case when a register is no longer required in a computation  there are extremely rare cases (see distribute_notes) when a REG_DEAD note is lost  a LOG_LINKS entry that refers to an insn with multiple SETs may be removed because there is no way to know which register it was linking To simplify substitution, we combine only when the earlier insn(s) consist of only a single assignment. To simplify updating afterward, we never combine when a subroutine call appears in the middle. Since we do not represent assignments to CC0 explicitly except when that is all an insn does, there is no LOG_LINKS entry in an insn that uses the condition code for the insn that set the condition code. Fortunately, these two insns must be consecutive. Therefore, every JUMP_INSN is taken to have an implicit logical link to the preceding insn. This is not quite right, since nonjumps can also use the condition code; but in practice such insns would not combine anyway.
Include expr.h after insnconfig.h so we get HAVE_conditional_move.
Number of attempts to combine instructions in this function.

static 
Number of instructions combined with added SETs in this function.

static 
Number of attempts that got as far as substitution in this function.
Referenced by try_combine().

static 

static 
Number of instructions combined in this function.

static 
combine_instructions may try to replace the right hand side of the second instruction with the value of an associated REG_EQUAL note before throwing it at try_combine. That is problematic when there is a REG_DEAD note for a register used in the old right hand side and can cause distribute_notes to do wrong things. This is the second instruction if it has been so modified, null otherwise.

static 
When I2MOD is nonnull, this is a copy of the new right hand side.

static 
When I2MOD is nonnull, this is a copy of the old right hand side.

static 
Links for LOG_LINKS are allocated from this obstack.

static 
Incremented for each basic block.

static 
Reset to label_tick for each extended basic block in scanning order.

static 
Record the luid of the last CALL_INSN so we can tell whether a potential combination crosses any calls.

static 
Length of the currently allocated uid_insn_cost array.

static 
Record the luid of the last insn that invalidated memory (anything that writes memory, and subroutine calls, but not pushes).

static 
Number of times the pseudo being substituted for was found and replaced.

static 
This contains any hard registers that are used in newpat; reg_dead_at_p must consider all these registers to be always live.

static 
Mode used to compute significance in reg_stat[].nonzero_bits. It is the largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.

static 
Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can be safely used. It is zero while computing them and after combine has completed. This former test prevents propagating values based on previously set values, which can be incorrect if a variable is modified in a loop.

static 
Referenced by simplify_set().

static 

static 

static 
Define three variables used for communication between the following routines.

static 
Referenced by init_reg_last().

static 
When `subst' is called, this is the insn that is being modified (by combining in a previous insn). The PATTERN of this insn is still the old pattern partially modified and it should not be looked at, but this may be used to examine the successors of the insn to judge whether a simplification is valid.
Referenced by try_combine().

static 
This is the lowest LUID that `subst' is currently dealing with. get_last_value will not return a value if the register was set at or after this LUID. If not for this mechanism, we could get confused if I2 or I1 in try_combine were an insn that used the old value of a register to obtain a new value. In that case, we might erroneously get the new value of the register when we wanted the old one.
Referenced by try_combine().

static 
Basic block in which we are performing combines.
Referenced by use_crosses_set_p().

static 
Totals over entire compilation.

static 

static 

static 

static 
The following array records the insn_rtx_cost for every insn in the instruction stream.

static 