GCC Middle and Back End API Reference
lower-subreg.c File Reference

Data Structures

struct  cost_rtxes




static int shift_cost (bool speed_p, struct cost_rtxes *rtxes, enum rtx_code code, enum machine_mode mode, int op1)
static void compute_splitting_shift (bool speed_p, struct cost_rtxes *rtxes, bool *splitting, enum rtx_code code, int word_move_zero_cost, int word_move_cost)
static void compute_costs ()
void init_lower_subreg ()
static bool simple_move_operand ()
static rtx simple_move ()
static bool find_pseudo_copy ()
static void propagate_pseudo_copies ()
static int find_decomposable_subregs ()
static void decompose_register ()
static rtx simplify_subreg_concatn (enum machine_mode outermode, rtx op, unsigned int byte)
static rtx simplify_gen_subreg_concatn (enum machine_mode outermode, rtx op, enum machine_mode innermode, unsigned int byte)
static bool resolve_reg_p ()
static bool resolve_subreg_p ()
static int resolve_subreg_use ()
static int adjust_decomposed_uses ()
static void resolve_reg_notes ()
static bool can_decompose_p ()
static rtx resolve_simple_move ()
static bool resolve_clobber ()
static bool resolve_use ()
static void resolve_debug ()
static bool find_decomposable_shift_zext ()
static rtx resolve_shift_zext ()
static void dump_shift_choices ()
static void dump_choices ()
static void decompose_multiword_subregs ()
static bool gate_handle_lower_subreg ()
static unsigned int rest_of_handle_lower_subreg ()
static unsigned int rest_of_handle_lower_subreg2 ()
rtl_opt_passmake_pass_lower_subreg ()
rtl_opt_passmake_pass_lower_subreg2 ()


static bitmap decomposable_context
static bitmap non_decomposable_context
static bitmap subreg_context
static vec< bitmapreg_copy_graph
struct target_lower_subreg default_target_lower_subreg
struct target_lower_subregthis_target_lower_subreg = &default_target_lower_subreg

Enumeration Type Documentation

   A pointer to one of these values is passed to
   find_decomposable_subregs via for_each_rtx.  
     Not a simple move from one location to another.  
     A simple move we want to decompose.  
     Any other simple move.  

Function Documentation

static int adjust_decomposed_uses ( )
   This is called via for_each_rtx.  Look for SUBREGs which can be
   decomposed and decomposed REGs that need copying.  

References resolve_reg_p().

Referenced by resolve_clobber().

static bool can_decompose_p ( )
   Return whether X can be decomposed into subwords.  

References gen_reg_rtx().

static void compute_costs ( )
   Compute what we should do when optimizing for speed or size; SPEED_P
   selects which.  Use RTXES for computing costs.  
     For the moves and shifts, the only case that is checked is one
     where the mode of the target is an integer mode twice the width
     of the word_mode.

     If it is not profitable to split a double word move then do not
     even consider the shifts or the zero extension.  
         The only case here to check to see if moving the upper part with a
         zero is cheaper than doing the zext itself.  
static void compute_splitting_shift ( bool  speed_p,
struct cost_rtxes rtxes,
bool *  splitting,
enum rtx_code  code,
int  word_move_zero_cost,
int  word_move_cost 
   For each X in the range [0, BITS_PER_WORD), set SPLITTING[X]
   to true if it is profitable to split a double-word CODE shift
   of X + BITS_PER_WORD bits.  SPEED_P says whether we are testing
   for speed or size profitability.

   Use the rtxes in RTXES to calculate costs.  WORD_MOVE_ZERO_COST is
   the cost of moving zero into a word-mode register.  WORD_MOVE_COST
   is the cost of moving between word registers.  
static void decompose_multiword_subregs ( )
   Look for registers which are always accessed via word-sized SUBREGs
   or -if DECOMPOSE_COPIES is true- via copies.  Decompose these
   registers into several word-sized pseudo-registers.  
     Check if this target even has any modes to consider lowering.   
     First see if there are any multi-word pseudo-registers.  If there
     aren't, there is nothing we can do.  This should speed up this
     pass in the normal case, since it should be faster than scanning
     all the insns.  
     FIXME: It may be possible to change this code to look for each
     multi-word pseudo-register and to find each insn which sets or
     uses that register.  That should be faster than scanning all the
                 We mark pseudo-to-pseudo copies as decomposable during the
                 second pass only.  The first pass is so early that there is
                 good chance such moves will be optimized away completely by
                 subsequent optimizations anyway.

                 However, we call find_pseudo_copy even during the first pass
                 so as to properly set up the reg_copy_graph.  
                 We handle ASM_OPERANDS as a special case to support
                 things like x86 rdtsc which returns a DImode value.
                 We can decompose the output, which will certainly be
                 operand 0, but not the inputs.  
                         We can end up splitting loads to multi-word pseudos
                         into separate loads to machine word size pseudos.
                         When this happens, we first had one load that can
                         throw, and after resolve_simple_move we'll have a
                         bunch of loads (at least two).  All those loads may
                         trap if we can have non-call exceptions, so they
                         all will end the current basic block.  We split the
                         block after the outer loop over all insns, but we
                         make sure here that we will be able to split the
                         basic block and still produce the correct control
                         flow graph for it.  
         If we had insns to split that caused control flow insns in the middle
         of a basic block, split those blocks now.  Note that we only handle
         the case where splitting a load has caused multiple possibly trapping
         loads to appear.  
                     Split the block after insn.  There will be a fallthru
                     edge, which is OK so we keep it.  We have to create the
                     exception edges ourselves.  
static void decompose_register ( )
   Decompose REGNO into word-sized components.  We smash the REG node
   in place.  This ensures that (1) something goes wrong quickly if we
   fail to make some replacement, and (2) the debug information inside
   the symbol table is automatically kept up to date.  

References mode_for_size().

static void dump_choices ( )
   Print to dump_file a description of what we're doing when optimizing
   for speed or size; SPEED_P says which.  DESCRIPTION is a description
   of the SPEED_P choice.  
static void dump_shift_choices ( )
   Print to dump_file a description of what we're doing with shift code CODE.
   SPLITTING[X] is true if we are splitting shifts by X + BITS_PER_WORD.  

References dump_file.

static bool find_decomposable_shift_zext ( )
   Check if INSN is a decomposable multiword-shift or zero-extend and
   set the decomposable_context bitmap accordingly.  SPEED_P is true
   if we are optimizing INSN for speed rather than size.  Return true
   if INSN is decomposable.  
static int find_decomposable_subregs ( )
   This is called via for_each_rtx.  If we find a SUBREG which we
   could use to decompose a pseudo-register, set a bit in
   DECOMPOSABLE_CONTEXT.  If we find an unadorned register which is
   not a simple pseudo-register copy, DATA will point at the type of
   move, and we set a bit in DECOMPOSABLE_CONTEXT or
   NON_DECOMPOSABLE_CONTEXT as appropriate.  
         We only try to decompose single word subregs of multi-word
         registers.  When we find one, we return -1 to avoid iterating
         over the inner register.

         ??? This doesn't allow, e.g., DImode subregs of TImode values
         on 32-bit targets.  We would need to record the way the
         pseudo-register was used, and only decompose if all the uses
         were the same number and size of pieces.  Hopefully this
         doesn't happen much.  
         If this is a cast from one mode to another, where the modes
         have the same size, and they are not tieable, then mark this
         register as non-decomposable.  If we decompose it we are
         likely to mess up whatever the backend is trying to do.  
         We will see an outer SUBREG before we see the inner REG, so
         when we see a plain REG here it means a direct reference to
         the register.

         If this is not a simple copy from one location to another,
         then we can not decompose this register.  If this is a simple
         copy we want to decompose, and the mode is right,
         then we mark the register as decomposable.
         Otherwise we don't say anything about this register --
         it could be decomposed, but whether that would be
         profitable depends upon how it is used elsewhere.

         We only set bits in the bitmap for multi-word
         pseudo-registers, since those are the only ones we care about
         and it keeps the size of the bitmaps down.  
         Any registers used in a MEM do not participate in a
         SIMPLE_MOVE or DECOMPOSABLE_SIMPLE_MOVE.  Do our own recursion
         here, and return -1 to block the parent's recursion.  

References bitmap_set_bit().

static bool find_pseudo_copy ( )
   If SET is a copy from one multi-word pseudo-register to another,
   record that in reg_copy_graph.  Return whether it is such a
static bool gate_handle_lower_subreg ( )
   Gate function for lower subreg pass.  
void init_lower_subreg ( void  )
   Do one-per-target initialisation.  This involves determining
   which operations on the machine are profitable.  If none are found,
   then the pass just returns when called.  
rtl_opt_pass* make_pass_lower_subreg ( )
rtl_opt_pass* make_pass_lower_subreg2 ( )
static void propagate_pseudo_copies ( )
   Look through the registers in DECOMPOSABLE_CONTEXT.  For each case
   where they are copied to another register, add the register to
   which they are copied to DECOMPOSABLE_CONTEXT.  Use
   NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track
   copies of registers which are in NON_DECOMPOSABLE_CONTEXT.  
static bool resolve_clobber ( )
   Change a CLOBBER of a decomposed register into a CLOBBER of the
   component registers.  Return whether we changed something.  

References adjust_decomposed_uses(), df_insn_rescan(), for_each_rtx(), and resolve_reg_notes().

static void resolve_debug ( )
   A VAR_LOCATION can be simplified.  
static void resolve_reg_notes ( )
   Resolve any decomposed registers which appear in register notes on

References bitmap_bit_p(), simplify_subreg_regno(), and word_mode.

Referenced by resolve_clobber().

static bool resolve_reg_p ( )
   Return whether we should resolve X into the registers into which it
   was decomposed.  

Referenced by adjust_decomposed_uses(), and resolve_subreg_use().

static rtx resolve_shift_zext ( )
   Decompose a more than word wide shift (in INSN) of a multiword
   pseudo or a multiword zero-extend of a wordmode pseudo into a move
   and 'set to zero' insn.  Return a pointer to the new insn when a
   replacement was done.  
     We can tear this operation apart only if the regs were already
     torn apart.  
     src_reg_num is the number of the word mode register which we
     are operating on.  For a left shift and a zero_extend on little
     endian machines this is register 0.  
static rtx resolve_simple_move ( )
   Decompose the registers used in a simple move SET within INSN.  If
   we don't change anything, return INSN, otherwise return the start
   of the sequence of moves.  
     We have to handle copying from a SUBREG of a decomposed reg where
     the SUBREG is larger than word size.  Rather than assume that we
     can take a word_mode SUBREG of the destination, we copy to a new
     register and then copy that to the destination.  
     Similarly if we are copying to a SUBREG of a decomposed reg where
     the SUBREG is larger than word size.  
     If we didn't have any big SUBREGS of decomposed registers, and
     neither side of the move is a register we are decomposing, then
     we don't have to do anything here.  
     It's possible for the code to use a subreg of a decomposed
     register while forming an address.  We need to handle that before
     passing the address to emit_move_insn.  We pass NULL_RTX as the
     insn parameter to resolve_subreg_use because we can not validate
     the insn yet.  
     If SRC is a register which we can't decompose, or has side
     effects, we need to move via a temporary register.  
     If DEST is a register which we can't decompose, or has side
     effects, we need to first move to a temporary register.  We
     handle the common case of pushing an operand directly.  We also
     go through a temporary register if it holds a floating point
     value.  This gives us better code on systems which can't move
     data easily between integer and floating point registers.  
     If we get here via self-recursion, then INSN is not yet in the insns
     chain and delete_insn will fail.  We only want to remove INSN from the
     current sequence.  See PR56738.  
static bool resolve_subreg_p ( )
   Return whether X is a SUBREG of a register which we need to

Referenced by resolve_subreg_use().

static int resolve_subreg_use ( )
   This is called via for_each_rtx.  Look for SUBREGs which need to be
         It is possible for a note to contain a reference which we can
         decompose.  In this case, return 1 to the caller to indicate
         that the note must be removed.  
         Return 1 to the caller to indicate that we found a direct
         reference to a register which is being decomposed.  This can
         happen inside notes, multiword shift or zero-extend

References copy_rtx(), resolve_reg_p(), resolve_subreg_p(), and simplify_subreg_concatn().

static bool resolve_use ( )
   A USE of a decomposed register is no longer meaningful.  Return
   whether we changed something.  
static unsigned int rest_of_handle_lower_subreg ( )
   Implement first lower subreg pass.  
static unsigned int rest_of_handle_lower_subreg2 ( )
   Implement second lower subreg pass.  
static int shift_cost ( bool  speed_p,
struct cost_rtxes rtxes,
enum rtx_code  code,
enum machine_mode  mode,
int  op1 
   Return the cost of a CODE shift in mode MODE by OP1 bits, using the
   rtxes in RTXES.  SPEED_P selects between the speed and size cost.  
static rtx simple_move ( )
   If INSN is a single set between two objects that we want to split,
   return the single set.  SPEED_P says whether we are optimizing
   INSN for speed or size.

   INSN should have been passed to recog and extract_insn before this
   is called.  
     For the src we can handle ASM_OPERANDS, and it is beneficial for
     things like x86 rdtsc which returns a DImode value.  
     We try to decompose in integer modes, to avoid generating
     inefficient code copying between integer and floating point
     registers.  That means that we can't decompose if this is a
     non-integer mode for which there is no integer mode of the same
     Reject PARTIAL_INT modes.  They are used for processor specific
     purposes and it's probably best not to tamper with them.  
static bool simple_move_operand ( )
static rtx simplify_gen_subreg_concatn ( enum machine_mode  outermode,
rtx  op,
enum machine_mode  innermode,
unsigned int  byte 
   Wrapper around simplify_gen_subreg which handles CONCATN.  
     We have to handle generating a SUBREG of a SUBREG of a CONCATN.
     If OP is a SUBREG of a CONCATN, then it must be a simple mode
     change with the same size and offset 0, or it must extract a
     part.  We shouldn't see anything else here.  
             We don't handle paradoxical subregs here.  
     If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then
     resolve_simple_move will ask for the high part of the paradoxical
     subreg, which does not have a value.  Just return a zero.  
static rtx simplify_subreg_concatn ( enum machine_mode  outermode,
rtx  op,
unsigned int  byte 
   Get a SUBREG of a CONCATN.  
     VECTOR_CSTs in debug expressions are expanded into CONCATN instead of
     regular CONST_VECTORs.  They have vector or integer modes, depending
     on the capabilities of the target.  Cope with them.  

Referenced by resolve_subreg_use().

Variable Documentation

bitmap decomposable_context
   Bit N in this bitmap is set if regno N is used in a context in
   which we can decompose it.  
struct target_lower_subreg default_target_lower_subreg
bitmap non_decomposable_context
   Bit N in this bitmap is set if regno N is used in a context in
   which it can not be decomposed.  
vec<bitmap> reg_copy_graph
   Bit N in the bitmap in element M of this array is set if there is a
   copy from reg M to reg N.  
bitmap subreg_context
   Bit N in this bitmap is set if regno N is used in a subreg
   which changes the mode but not the size.  This typically happens
   when the register accessed as a floating-point value; we want to
   avoid generating accesses to its subwords in integer modes.  
struct target_lower_subreg* this_target_lower_subreg = &default_target_lower_subreg