- Generated by
1.8.1.1
|
GCC Middle and Back End API Reference
|
Data Structures | |
| struct | sloc |
Typedefs | |
| typedef struct sloc * | sloc_t |
|
static |
Process recursively X of INSN and add REG_INC notes if necessary.
Scan all X sub-expressions.
Referenced by check_rtl().
|
static |
This page contains code dealing with info about registers in insns.
Process X of insn UID recursively and add info (operand type is given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) about registers in X to the insn DATA.
The info can not be integrated into the found
structure. We treat clobber of non-operand hard registers as early
clobber (the behavior is expected from asm). Some targets place small structures in registers for return
values of functions, and those registers are wrapped in
PARALLEL that we may see as the destination of a SET. Here
is an example:
(call_insn 13 12 14 2 (set (parallel:BLK [
(expr_list:REG_DEP_TRUE (reg:DI 0 ax)
(const_int 0 [0]))
(expr_list:REG_DEP_TRUE (reg:DI 1 dx)
(const_int 8 [0x8]))
])
(call (mem:QI (symbol_ref:DI (...
|
static |
Expand, if necessary, LRA data about insns.
|
static |
Function checks RTL for correctness. If FINAL_P is true, it is done at the end of LRA and the check is more rigorous.
LRA code is based on assumption that all addresses can be
correctly decomposed. LRA can generate reloads for
decomposable addresses. The decomposition code checks the
correctness of the addresses. So we don't need to check
the addresses here.
References add_auto_inc_notes().
|
staticread |
Recursively process X and collect info about registers, which are not the insn operands, in X with TYPE (in/out/inout) and flag that it is early clobbered in the insn (EARLY_CLOBBER) and add the info to LIST. X is a part of insn given by DATA. Return the result list.
It is an operand loc. Stop here.
It is a dup loc. Stop here.
This is a new hard regno or the info can not be
integrated into the found structure. This clobber is to inform popping floating
point stack only. We treat clobber of non-operand hard registers as early
clobber (the behavior is expected from asm).
References new_insn_reg().
|
static |
Emit insn x = x + y. Return the insn. We use gen_add2_insn as the last resort.
References emit_add3_insn(), last, and max_reg_num().
|
static |
Emit insn x = y + z. Return NULL if we failed to do it. Otherwise, return the insn. We don't use gen_add3_insn as it might clobber CC.
Referenced by emit_add2_insn().
|
static |
Expand all regno related info needed for LRA.
|
static |
Expand common reg info if it is necessary.
|
static |
Called once per compiler work to finalize some LRA data related to insns.
|
static |
Finish LRA data about all insns.
References operand_alternative::anything_ok.
|
static |
Finish pool for insn reg info.
References debug_operand_data.
|
static |
Finish common reg info and copies.
|
static |
Finish LRA DATA about insn.
References lra_static_insn_data::operand_alternative.
|
static |
Free insn reg info IR.
Referenced by new_insn_reg().
|
static |
Free insn reg info list IR.
References OP_IN.
|
static |
|
static |
Return execution frequency of INSN.
|
static |
Return info about insn give by UID. The info should be already set up.
|
static |
Return new register value.
|
staticread |
Return static insn data, allocate and setup if necessary. Although dup_num is static data (it depends only on icode), to set it up we need to extract insn first. So recog_data should be valid for normal insn (ICODE >= 0) before the call.
|
static |
Determine if the current function has an exception receiver block that reaches the exit block via non-exceptional edges
If we're not optimizing, then just err on the safe side.
First determine which blocks can reach exit via normal paths.
Place the exit block on our worklist.
Iterate: find everything reachable from what we've already seen.
No exceptional block reached exit unexceptionally.
References targetm.
|
static |
Called once per compiler work to initialize some LRA data related to insns.
|
static |
Initialize LRA data about insns.
|
static |
Initiate pool for insn reg info.
References pool_free().
|
static |
Initialize LRA info about operands in insn alternatives.
References lra_operand_data::constraint, insn_operand_data::constraint, insn_data, lra_operand_data::is_address, lra_operand_data::is_operator, insn_operand_data::is_operator, OP_IN, OP_INOUT, OP_OUT, lra_static_insn_data::operand, insn_data_d::operand, lra_operand_data::strict_low, and insn_operand_data::strict_low.
|
static |
Initialize common reg info and copies.
|
inlinestatic |
Initialize I-th element of lra_reg_info.
References lra_reg::copies, lra_copy::freq, lra_reg::freq, pool_alloc(), lra_copy::regno1, lra_copy::regno1_dest_p, lra_copy::regno1_next, lra_copy::regno2, and lra_copy::regno2_next.
|
static |
Invalidate all reg info of INSN with DATA and execution frequency FREQ. Update common info about the invalidated registers.
References bitmap_bit_p(), bitmap_set_bit(), lra_update_insn_regno_info(), and sbitmap_resize().
|
static |
Referenced by lra_set_regno_unique_value().
|
static |
Invalidate all info about insn given by its UID.
| void lra | ( | ) |
Major LRA entry function. F is a file should be used to dump LRA debug info.
Make sure that the last insn is a note. Some subsequent passes
need it. We can not set up reload_in_progress because it prevents new
pseudo creation. Function remove_scratches can creates new pseudos for clobbers --
so set up lra_constraint_new_regno_start before its call to
permit changing reg classes for pseudos created by this
simplification. A function that has a non-local label that can reach the exit
block via non-exceptional paths must save all call-saved
registers. We don't DF from now and avoid its using because it is to
expensive when a lot of RTL changes are made. It is needed for the 1st coalescing.
If we have a stack frame, we must align it now. The stack size
may be a part of the offset computation for register
elimination. We should try to assign hard registers to scratches even
if there were no RTL transformations in
lra_constraints. Constraint transformations may result in that eliminable
hard regs become uneliminable and pseudos which use them
should be spilled. It is better to do it before pseudo
assignments.
For example, rs6000 can make
RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
to use a constant pool. Do inheritance only for regular algorithms.
We need live ranges for lra_assign -- so build them.
If we don't spill non-reload and non-inheritance pseudos,
there is no sense to run memory-memory move coalescing.
If inheritance pseudos were spilled, the memory-memory
moves involving them will be removed by pass undoing
inheritance. Don't clear optional reloads bitmap until all constraints are
satisfied as we need to differ them from regular reloads. We need full live info for spilling pseudos into
registers instead of memory. Assignment of stack slots changes elimination offsets for
some eliminations. So update the offsets here. We've possibly turned single trapping insn into multiple ones.
Replacing pseudos with their memory equivalents might have
created shared rtx. Subsequent passes would get confused
by this, so unshare everything here.
| void lra_create_copy | ( | ) |
Create copy of two pseudos REGNO1 and REGNO2. The copy execution frequency is FREQ.
References lra_insn_reg::early_clobber, lra_insn_recog_data::insn, new_insn_reg(), lra_insn_reg::next, OP_INOUT, lra_insn_reg::regno, lra_insn_recog_data::regs, and lra_insn_reg::subreg_p.
| rtx lra_create_new_reg | ( | enum machine_mode | md_mode, |
| rtx | original, | ||
| enum reg_class | rclass, | ||
| const char * | title | ||
| ) |
Analogous to the previous function but also inherits value of ORIGINAL.
Referenced by push_insns().
| rtx lra_create_new_reg_with_unique_value | ( | enum machine_mode | md_mode, |
| rtx | original, | ||
| enum reg_class | rclass, | ||
| const char * | title | ||
| ) |
Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL or of VOIDmode, use MD_MODE for the new reg. Initialize its register class to RCLASS. Print message about assigning class RCLASS containing new register name TITLE unless it is NULL. Use attributes of ORIGINAL if it is a register. The created register will have unique held value.
Referenced by change_class().
| void lra_delete_dead_insn | ( | ) |
Delete an unneeded INSN and any previous insns who sole purpose is loading data that is dead in INSN.
If the previous insn sets a register that dies in our insn,
delete it too.
| void lra_emit_add | ( | ) |
Target checks operands through operand predicates to recognize an insn. We should have a special precaution to generate add insns which are frequent results of elimination. Emit insns for x = y + z. X can be used to store intermediate values and should be not in Y and Z when we use X to store an intermediate value. Y + Z should form [base] [+ index[ * scale]] [ + disp] where base and index are registers, disp and scale are constants. Y should contain base if it is present, Z should contain disp if any. index[*scale] can be part of Y or Z.
Probably we have no 3 op add. Last chance is to use 2-op
add insn. To succeed, don't move Z to X as an address
segment always comes in Y. Otherwise, we might fail when
adding the address segment to register. Generate x = index_scale; x = x + base.
Try x = base + disp.
Generate x = disp; x = x + base.
Generate x = x + index.
Try x = index_scale; x = x + disp; x = x + base.
Generate x = disp; x = x + base; x = x + index_scale.
Functions emit_... can create pseudos -- so expand the pseudo
data.
| void lra_emit_move | ( | ) |
Emit x := y, processing special case when y = u + v or y = u + v * scale + w through emit_add (Y can be an address which is base + index reg * scale + displacement in general case). X may be used as intermediate result therefore it should be not in Y.
Function emit_move can create pseudos -- so expand the pseudo
data.
References lra_static_insn_data::dup_num, and lra_static_insn_data::n_dups.
| void lra_finish_once | ( | void | ) |
Called once per compiler to finish LRA data which are initialize once.
| bool lra_former_scratch_operand_p | ( | ) |
Return true if the operand NOP of INSN is a former scratch.
References constrain_operands(), and extract_insn().
| bool lra_former_scratch_p | ( | ) |
Return true if pseudo REGNO is made of SCRATCH.
| void lra_free_copies | ( | void | ) |
Free all copies.
| lra_copy_t lra_get_copy | ( | ) |
Return N-th (0, 1, ...) copy. If there is no copy, return NULL.
|
read |
Return reg info of insn given by it UID.
References dump_rtl_slim(), and lra_dump_file.
| void lra_init | ( | void | ) |
Initialize LRA whenever register-related information is changed.
| void lra_init_once | ( | void | ) |
Called once per compiler to initialize LRA data once.
| unsigned int lra_insn_stack_length | ( | void | ) |
Return the current size of the insn stack.
| void lra_invalidate_insn_data | ( | ) |
Invalidate INSN related info used by LRA.
References lra_invalidate_insn_data().
| void lra_invalidate_insn_regno_info | ( | ) |
Invalidate all reg info of INSN. Update common info about the invalidated registers.
References lra_push_insn_1().
| rtx lra_pop_insn | ( | void | ) |
Take the last-inserted insns off the stack and return it.
References sloc::insn.
| void lra_process_new_insns | ( | ) |
Emit insns BEFORE before INSN and insns AFTER after INSN. Put the insns onto the stack. Print about emitting the insns with TITLE.
| void lra_push_insn | ( | ) |
Put INSN on the stack.
|
inlinestatic |
Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg info for INSN, otherwise only update it if INSN is not already on the stack.
References sloc::insn, and sloc::nop.
Referenced by lra_invalidate_insn_regno_info().
| void lra_push_insn_and_update_insn_regno_info | ( | ) |
Put INSN on the stack and update its reg info.
References bitmap_bit_p().
| void lra_push_insn_by_uid | ( | ) |
Put insn with UID on the stack.
References bitmap_bit_p().
| void lra_set_insn_deleted | ( | ) |
Mark INSN deleted and invalidate the insn related info used by LRA.
References prev_real_insn(), reg_mentioned_p(), and SET.
| lra_insn_recog_data_t lra_set_insn_recog_data | ( | ) |
Set up and return info about INSN. Set up the info if it is not set up yet.
It might be a new simple insn which is not recognized yet.
Its is a special insn like USE or CLOBBER.
expand_asm_operands makes sure there aren't too many
operands. Now get the operand values and constraints out of the
insn. Cache the insn because we don't want to call extract_insn
from get_attr_enabled as extract_insn modifies
which_alternative. The attribute enabled should not depend
on insn operands, operand modes, operand types, and operand
constraints. It should depend on the architecture. If it
is not true, we should rewrite this file code to use
extract_insn instead of less expensive insn_extract. Finding implicit hard register usage. We believe it will be
not changed whatever transformations are used. Call insns
are such example. It is an argument register.
Some output operand can be recognized only from the context not
from the constraints which are empty in this case. Call insn may
contain a hard register in set destination with empty constraint
and extract_insn treats them as an input. ??? Should we treat 'X' the same way. It looks to me that
'X' means anything and empty constraint means we do not
care.
References recog_data_d::constraints, and recog_data.
| void lra_set_regno_unique_value | ( | ) |
Set up for REGNO unique hold value.
References invalidate_insn_recog_data(), and lra_invalidate_insn_regno_info().
| void lra_set_used_insn_alternative | ( | ) |
Set up that INSN is using alternative ALT now.
| void lra_set_used_insn_alternative_by_uid | ( | ) |
Set up that insn with UID is using alternative ALT now. The insn info should be already set up.
References bitmap_clear(), free(), free_alloc_pool(), lra_reg::insn_bitmap, and reg_info_size.
| void lra_update_dups | ( | ) |
Update insn operands which are duplication of operands whose numbers are in array of NOPS (with end marker -1). The insn is represented by its LRA internal representation ID.
References lra_reg_info, pool_alloc(), lra_insn_reg::subreg_p, and type().
| lra_insn_recog_data_t lra_update_insn_recog_data | ( | ) |
Update all the insn info about INSN. It is usually called when something in the insn was changed. Return the updated info.
Now get the operand values and constraints out of the
insn. Cache the insn to prevent extract_insn call from
get_attr_enabled.
References lra_insn_recog_data::alternative_enabled_p, recog_data_d::insn, lra_static_insn_data::n_alternatives, recog_data, and which_alternative.
| void lra_update_insn_regno_info | ( | ) |
Set up insn reg info of INSN. Update common reg info from reg info of INSN.
|
staticread |
Create LRA insn related info about a reference to REGNO in INSN with TYPE (in/out/inout), biggest reference mode MODE, flag that it is reference through subreg (SUBREG_P), flag that is early clobbered in the insn (EARLY_CLOBBER), and reference to the next insn reg info (NEXT).
References free_insn_reg(), and lra_insn_reg::next.
Referenced by collect_non_operand_hard_regs(), and lra_create_copy().
|
static |
Push insns FROM to TO (excluding it) going in reverse order.
References add_reg_note(), lra_create_new_reg(), lra_get_insn_recog_data(), lra_update_dup(), lra_static_insn_data::n_operands, lra_static_insn_data::operand, and lra_insn_recog_data::operand_loc.
|
static |
Change scratches onto pseudos and save their location.
Because we might use DF right after caller-saves sub-pass
we need to keep DF info up to date.
|
static |
Changes pseudos created by function remove_scratches onto scratches.
It should be only case when scratch register with chosen
constraint 'X' did not get memory or hard register.
|
static |
Update common reg info from reg info of insn given by its DATA and execution frequency FREQ.
References lra_push_insn().
|
static |
Setup info about operands in alternatives of LRA DATA of insn.
These don't say anything we care about.
We currently only support one commutative pair of
operands. The last operand should not be marked
commutative.
|
static |
Set up value LRA_REG_SPILL_P.
References lra_create_live_ranges().
|
static |
Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC. We change pseudos by hard registers without notification of DF and that can make the notes obsolete. DF-infrastructure does not deal with REG_INC notes -- so we should regenerate them here.
|
static |
Pools for copies.
|
static |
Vec referring to pseudo copies.
|
static |
The following data are used as static insn data for all debug insns. If structure lra_static_insn_data is changed, the initializer should be changed too.
|
static |
Debug insns are represented as a special insn with one input operand which is RTL expression in var_location.
The following data are used as static insn operand data for all debug insns. If structure lra_operand_data is changed, the initializer should be changed too.
Referenced by finish_insn_regs().
| struct target_lra_int default_target_lra_int |
This page contains code dealing LRA insn info (or in other words LRA internal insn representation).
| struct lra_static_insn_data* insn_code_data[LAST_INSN_CODE] |
Map INSN_CODE -> the static insn data. This info is valid during all translation unit.
|
static |
This page contains code dealing with info about registers in the insns.
Pools for insn reg info.
|
static |
Last register value.
|
static |
This page contains code dealing with stack of the insns which should be processed by the next constraint pass.
Bitmap used to put an insn on the stack only in one exemplar.
| int lra_constraint_new_insn_uid_start |
First UID of insns generated before a new spill pass.
| int lra_constraint_new_regno_start |
Start of reload pseudo regnos before the new spill pass.
Referenced by bb_has_abnormal_call_pred(), spill_for(), and update_lives().
| int lra_curr_reload_num |
The number of emitted reload insns so far.
| FILE* lra_dump_file |
File used for output of LRA debug information.
Referenced by coalescable_pseudo_p(), lra_get_insn_regs(), lra_inheritance(), lra_init_elimination(), process_alt_operands(), reg_in_class_p(), remove_pseudos(), spill_pseudos(), swap_operands(), update_hard_regno_preference(), and valid_address_p().
| int lra_in_progress |
Set to 1 while in lra.
Referenced by address_operand(), and gen_tmp_stack_mem().
| bitmap_head lra_inheritance_pseudos |
Inheritance pseudo regnos before the new spill pass.
Map INSN_UID -> the insn recog data (NULL if unknown).
| int lra_insn_recog_data_len |
The current length of the following array.
| int lra_new_regno_start |
Start of pseudo regnos before the LRA.
Referenced by match_reload().
| HARD_REG_SET lra_no_alloc_regs |
@verbatim
LRA (local register allocator) driver and LRA utilities. Copyright (C) 2010-2013 Free Software Foundation, Inc. Contributed by Vladimir Makarov vmakarov@redhat.com.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see http://www.gnu.org/licenses/.
The Local Register Allocator (LRA) is a replacement of former
reload pass. It is focused to simplify code solving the reload
pass tasks, to make the code maintenance easier, and to implement new
perspective optimizations.
The major LRA design solutions are:
o division small manageable, separated sub-tasks
o reflection of all transformations and decisions in RTL as more
as possible
o insn constraints as a primary source of the info (minimizing
number of target-depended macros/hooks)
In brief LRA works by iterative insn process with the final goal is
to satisfy all insn and address constraints:
o New reload insns (in brief reloads) and reload pseudos might be
generated;
o Some pseudos might be spilled to assign hard registers to
new reload pseudos;
o Changing spilled pseudos to stack memory or their equivalences;
o Allocation stack memory changes the address displacement and
new iteration is needed.
Here is block diagram of LRA passes:
------------------------
--------------- | Undo inheritance for | ---------------
| Memory-memory | | spilled pseudos, | | New (and old) |
| move coalesce |<---| splits for pseudos got |<-- | pseudos |
--------------- | the same hard regs, | | assignment |
Start | | and optional reloads | ---------------
| | ------------------------ ^
V | ---------------- |
----------- V | Update virtual | |
| Remove |----> ------------>| register | |
| scratches | ^ | displacements | |
----------- | ---------------- |
| | |
| V New |
---------------- No ------------ pseudos -------------------
| Spilled pseudo | change |Constraints:| or insns | Inheritance/split |
| to memory |<-------| RTL |--------->| transformations |
| substitution | | transfor- | | in EBB scope |
---------------- | mations | -------------------
| ------------
V
-------------------------
| Hard regs substitution, |
| devirtalization, and |------> Finish
| restoring scratches got |
| memory |
-------------------------
To speed up the process:
o We process only insns affected by changes on previous
iterations;
o We don't use DFA-infrastructure because it results in much slower
compiler speed than a special IR described below does;
o We use a special insn representation for quick access to insn
info which is always *synchronized* with the current RTL;
o Insn IR is minimized by memory. It is divided on three parts:
o one specific for each insn in RTL (only operand locations);
o one common for all insns in RTL with the same insn code
(different operand attributes from machine descriptions);
o one oriented for maintenance of live info (list of pseudos).
o Pseudo data:
o all insns where the pseudo is referenced;
o live info (conflicting hard regs, live ranges, # of
references etc);
o data used for assigning (preferred hard regs, costs etc).
This file contains LRA driver, LRA utility functions and data, and
code for dealing with scratches. Hard registers currently not available for allocation. It can changed after some hard registers become not eliminable.
Referenced by lra_intersected_live_ranges_p(), process_alt_operands(), and substitute_pseudo().
| bitmap_head lra_optional_reload_pseudos |
Reload pseudo regnos before the new assignmnet pass which still can be spilled after the assinment pass as memory is also accepted in insns for the reload pseudos.
| struct lra_reg* lra_reg_info |
Common info about each register.
Referenced by add_pseudo_to_slot(), bb_has_abnormal_call_pred(), create_live_range_start_chains(), init_lives(), lra_debug_live_ranges(), lra_intersected_live_ranges_p(), lra_update_dups(), next_program_point(), process_alt_operands(), regno_freq_compare(), remove_pseudos(), remove_some_program_points_and_update_live_ranges(), setup_try_hard_regno_pseudos(), spill_pseudos(), update_hard_regno_preference(), and update_lives().
| bool lra_reg_spill_p |
True if we should try spill into registers of different classes instead of memory.
Referenced by remove_pseudos().
| bool lra_simple_p |
True if the current function is too big to use regular algorithms in LRA. In other words, we should use simpler and faster algorithms in LRA. It also means we should not worry about generation code for caller saves. The value is set up in IRA.
Referenced by split_live_ranges_for_shrink_wrap().
| bitmap_head lra_split_regs |
Split regnos before the new spill pass.
| bitmap_head lra_subreg_reload_pseudos |
Pseudo regnos used for subreg reloads before the new assignment pass. Such pseudos still can be spilled after the assinment pass.
Referenced by insert_move_for_subreg().
|
static |
This page contains code dealing with common register info and pseudo copies.
The size of the following array.
Referenced by lra_set_used_insn_alternative_by_uid().
|
static |
Bitmap of scratch regnos.
|
static |
Bitmap of scratch operands.
| struct target_lra_int* this_target_lra_int = &default_target_lra_int |
1.8.1.1