- Generated by
1.8.1.1
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GCC Middle and Back End API Reference
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Data Structures | |
| struct | move_by_pieces_d |
| struct | store_by_pieces_d |
Variables | |
| int | cse_not_expected |
| static tree | block_move_fn |
| tree | block_clear_fn |
| bool addr_expr_of_non_mem_decl_p | ( | ) |
Return TRUE iff OP is an ADDR_EXPR of a DECL that's not addressable. This is very much like mem_ref_refers_to_non_mem_p, but instead of the MEM_REF, it takes its base, and it doesn't assume a DECL is in memory just because its RTL is not set yet.
References emit_group_load(), emit_group_move(), and int_size_in_bytes().
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Returns true if ADDR is an ADDR_EXPR of a DECL that does not reside in memory and has non-BLKmode. DECL_RTL must not be a MEM; if DECL_RTL was not set yet, return NORTL.
References convert_memory_address_addr_space(), and emit_move_insn().
Referenced by get_subtarget().
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Return the largest alignment we can use for doing a move (or store) of MAX_PIECES. ALIGN is the largest alignment we could use.
References move_by_pieces_d::from_addr, get_address_mode(), move_by_pieces_d::offset, and move_by_pieces_d::to_addr.
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Return 1 if EXP contains all zeros.
References copy_rtx(), get_alias_set(), store_constructor_field(), and tree_low_cst().
| bool array_at_struct_end_p | ( | ) |
Returns true if REF is an array reference to an array at the end of a structure. If this is the case, the array may be allocated larger than its upper bound implies.
If the reference chain contains a component reference to a
non-union type and there follows another field the reference
is not at the end of a structure. If the reference is based on a declared entity, the size of the array
is constrained by its given domain.
| tree array_ref_element_size | ( | ) |
Return a tree of sizetype representing the size, in bytes, of the element of EXP, an ARRAY_REF or an ARRAY_RANGE_REF.
If a size was specified in the ARRAY_REF, it's the size measured
in alignment units of the element type. So multiply by that value. ??? tree_ssa_useless_type_conversion will eliminate casts to
sizetype from another type of the same width and signedness. Otherwise, take the size from that of the element type. Substitute
any PLACEHOLDER_EXPR that we have.
References alias_sets_conflict_p(), get_alias_set(), safe_from_p(), and staticp().
Referenced by get_addr_base_and_unit_offset_1(), and outermost_invariant_loop_for_expr().
| tree array_ref_low_bound | ( | ) |
Return a tree representing the lower bound of the array mentioned in EXP, an ARRAY_REF or an ARRAY_RANGE_REF.
If a lower bound is specified in EXP, use it.
Otherwise, if there is a domain type and it has a lower bound, use it,
substituting for a PLACEHOLDER_EXPR as needed. Otherwise, return a zero of the appropriate type.
Referenced by expand_expr_real_1(), get_addr_base_and_unit_offset_1(), outermost_invariant_loop_for_expr(), and pdr_add_alias_set().
| tree array_ref_up_bound | ( | ) |
Return a tree representing the upper bound of the array mentioned in EXP, an ARRAY_REF or an ARRAY_RANGE_REF.
If there is a domain type and it has an upper bound, use it, substituting
for a PLACEHOLDER_EXPR as needed. Otherwise fail.
Referenced by pdr_add_alias_set().
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A subroutine of emit_block_move. Returns true if calling the block move libcall will not clobber any parameters which may have already been placed on the stack.
If arguments are pushed on the stack, then they're safe.
If registers go on the stack anyway, any argument is sure to clobber
an outgoing argument. Avoid set but not used warning if *REG_PARM_STACK_SPACE doesn't
depend on its argument. If any argument goes in memory, then it might clobber an outgoing
argument.
References create_convert_operand_to(), create_fixed_operand(), create_integer_operand(), insn_data, maybe_expand_insn(), and volatile_ok.
Referenced by move_by_pieces_1().
| tree build_personality_function | ( | ) |
Build a decl for a personality function given a language prefix.
Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
are the flags assigned by targetm.encode_section_info.
| int can_move_by_pieces | ( | unsigned HOST_WIDE_INT | len, |
| unsigned int | align | ||
| ) |
Determine whether the LEN bytes can be moved by using several move instructions. Return nonzero if a call to move_by_pieces should succeed.
References move_by_pieces_d::autinc_from, move_by_pieces_d::reverse, and widest_int_mode_for_size().
Referenced by gimplify_init_ctor_eval().
| int can_store_by_pieces | ( | unsigned HOST_WIDE_INT | len, |
| rtx(*)(void *, HOST_WIDE_INT, enum machine_mode) | constfun, | ||
| void * | constfundata, | ||
| unsigned int | align, | ||
| bool | memsetp | ||
| ) |
Determine whether the LEN bytes generated by CONSTFUN can be stored to memory using several move instructions. CONSTFUNDATA is a pointer which will be passed as argument in every CONSTFUN call. ALIGN is maximum alignment we can assume. MEMSETP is true if this is a memset operation and false if it's a copy of a constant string. Return nonzero if a call to store_by_pieces should succeed.
cst is set but not used if LEGITIMATE_CONSTANT doesn't use it.
We would first store what we can in the largest integer mode, then go to
successively smaller modes. The code above should have handled everything.
| bool categorize_ctor_elements | ( | const_tree | ctor, |
| HOST_WIDE_INT * | p_nz_elts, | ||
| HOST_WIDE_INT * | p_init_elts, | ||
| bool * | p_complete | ||
| ) |
Examine CTOR to discover:
* how many scalar fields are set to nonzero values,
and place it in *P_NZ_ELTS;
* how many scalar fields in total are in CTOR,
and place it in *P_ELT_COUNT.
* whether the constructor is complete -- in the sense that every
meaningful byte is explicitly given a value --
and place it in *P_COMPLETE.
Return whether or not CTOR is a valid static constant initializer, the same
as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0".
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Helper for categorize_ctor_elements. Identical interface.
Whether CTOR is a valid constant initializer, in accordance with what
initializer_constant_valid_p does. If inferred from the constructor
elements, true until proven otherwise.
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Generate several move instructions to clear LEN bytes of block TO. (A MEM rtx with BLKmode). ALIGN is maximum alignment we can assume.
References emit_move_insn(), and write_complex_part().
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Callback routine for clear_by_pieces. Return const0_rtx unconditionally.
| rtx clear_storage | ( | ) |
References emit_move_insn().
Referenced by count_type_elements().
| rtx clear_storage_hints | ( | rtx | object, |
| rtx | size, | ||
| enum block_op_methods | method, | ||
| unsigned int | expected_align, | ||
| HOST_WIDE_INT | expected_size | ||
| ) |
Write zeros through the storage of OBJECT. If OBJECT has BLKmode, SIZE is its length in bytes.
If OBJECT is not BLKmode and SIZE is the same size as its mode,
just move a zero. Otherwise, do this a piece at a time.
References byte_mode, create_convert_operand_from(), create_convert_operand_to(), create_fixed_operand(), create_integer_operand(), insn_data, and maybe_expand_insn().
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References simplify_gen_subreg().
| bool complete_ctor_at_level_p | ( | const_tree | type, |
| HOST_WIDE_INT | num_elts, | ||
| const_tree | last_type | ||
| ) |
TYPE is initialized by a constructor with NUM_ELTS elements, the last of which had type LAST_TYPE. Each element was itself a complete initializer, in the sense that every meaningful byte was explicitly given a value. Return true if the same is true for the constructor as a whole.
??? We could look at each element of the union, and find the
largest element. Which would avoid comparing the size of the
initialized element against any tail padding in the union.
Doesn't seem worth the effort...
| tree component_ref_field_offset | ( | ) |
Return a tree representing the offset, in bytes, of the field referenced by EXP. This does not include any offset in DECL_FIELD_BIT_OFFSET.
If an offset was specified in the COMPONENT_REF, it's the offset measured
in units of DECL_OFFSET_ALIGN / BITS_PER_UNIT. So multiply by that
value. ??? tree_ssa_useless_type_conversion will eliminate casts to
sizetype from another type of the same width and signedness. Otherwise, take the offset from that of the field. Substitute
any PLACEHOLDER_EXPR that we have.
Referenced by dr_analyze_indices(), and get_addr_base_and_unit_offset_1().
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If Y is representable exactly in a narrower mode, and the target can perform the extension directly from constant or memory, then emit the move as an extension.
Skip if the target can't extend this way.
Skip if the narrowed value isn't exact.
Skip if the target needs extra instructions to perform
the extension. This is valid, but may not be cheaper than the original.
This is valid, but may not be cheaper than the original.
For CSE's benefit, force the compressed constant pool entry
into a new pseudo. This constant may be used in different modes,
and if not, combine will put things back together for us.
References HOST_WIDE_INT_MIN, and rtx_equal_p().
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Return a CONST_VECTOR rtx for a VECTOR_CST tree.
| rtx convert_modes | ( | ) |
Return an rtx for a value that would result from converting X from mode OLDMODE to mode MODE. Both modes may be floating, or both integer. UNSIGNEDP is nonzero if X is an unsigned value. This can be done by referring to a part of X in place or by copying to a new temporary with conversion. You can give VOIDmode for OLDMODE, if you are sure X has a nonvoid mode.
If FROM is a SUBREG that indicates that we have already done at least
the required extension, strip it. There is one case that we must handle specially: If we are converting
a CONST_INT into a mode whose size is twice HOST_BITS_PER_WIDE_INT and
we are to interpret the constant as unsigned, gen_lowpart will do
the wrong if the constant appears negative. What we want to do is
make the high-order word of the constant zero, not all ones. We need to zero extend VAL.
We can do this with a gen_lowpart if both desired and current modes
are integer, and this is either a constant integer, a register, or a
non-volatile MEM. Except for the constant case where MODE is no
wider than HOST_BITS_PER_WIDE_INT, we must be narrowing the operand. ?? If we don't know OLDMODE, we have to assume here that
X does not need sign- or zero-extension. This may not be
the case, but it's the best we can do. We must sign or zero-extend in this case. Start by
zero-extending, then sign extend if we need to. Converting from integer constant into mode is always equivalent to an
subreg operation.
References gen_int_mode(), HOST_WIDE_INT, and val_signbit_known_set_p().
Referenced by avoid_expensive_constant(), compute_argument_block_size(), expand_mult(), node_has_low_bound(), resolve_operand_name_1(), and swap_commutative_operands_with_target().
| void convert_move | ( | ) |
Copy data from FROM to TO, where the machine modes are not the same. Both modes may be integer, or both may be floating, or both may be fixed-point. UNSIGNEDP should be nonzero if FROM is an unsigned type. This causes zero-extension instead of sign-extension.
rtx code for making an equivalent value.
If the source and destination are already the same, then there's
nothing to do. If FROM is a SUBREG that indicates that we have already done at least
the required extension, strip it. We don't handle such SUBREGs as
TO here. Conversion between decimal float and binary float, same size.
Try converting directly if the insn is supported.
Otherwise use a libcall.
Is this conversion implemented yet?
Handle pointer conversion.
Targets are expected to provide conversion insns between PxImode and
xImode for all MODE_PARTIAL_INT modes they use, but no others. else proceed to integer conversions below.
Make sure both are fixed-point modes or both are not.
If we widen from_mode to to_mode and they are in the same class,
we won't saturate the result.
Otherwise, always saturate the result to play safe. Now both modes are integers.
Handle expanding beyond a word.
Try converting directly if the insn is supported.
If FROM is a SUBREG, put it into a register. Do this
so that we always generate the same set of insns for
better cse'ing; if an intermediate assignment occurred,
we won't be doing the operation directly on the SUBREG. Next, try converting via full word.
No special multiword conversion insn; do it by hand.
Since we will turn this into a no conflict block, we must ensure the
the source does not overlap the target so force it into an isolated
register when maybe so. Likewise for any MEM input, since the
conversion sequence might require several references to it and we
must ensure we're getting the same value every time. Get a copy of FROM widened to a word, if necessary.
Compute the value to put in each remaining word.
Fill the remaining words.
Truncating multi-word to a word or less.
Now follow all the conversions between integers
no more than a word long. For truncation, usually we can just refer to FROM in a narrower mode.
Handle extension.
Convert directly if that works.
Search for a mode to convert via.
No suitable intermediate mode.
Generate what we need with shifts. Support special truncate insns for certain modes.
Handle truncation of volatile memrefs, and so on;
the things that couldn't be truncated directly,
and for which there was no special instruction.
??? Code above formerly short-circuited this, for most integer
mode pairs, with a force_reg in from_mode followed by a recursive
call to this routine. Appears always to have been wrong. Mode combination is not recognized.
Referenced by expand_builtin_memset(), expand_builtin_memset_args(), and supportable_convert_operation().
| rtx convert_to_mode | ( | ) |
Return an rtx for a value that would result from converting X to mode MODE. Both X and MODE may be floating, or both integer. UNSIGNEDP is nonzero if X is an unsigned value. This can be done by referring to a part of X in place or by copying to a new temporary with conversion.
Referenced by assign_parm_adjust_entry_rtl(), dump_case_nodes(), expand_binop(), expand_builtin_memset_args(), expand_float(), expand_mult(), have_add2_insn(), stabilize_va_list_loc(), and supportable_convert_operation().
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Convert the tree comparison code TCODE to the rtl one where the signedness is UNSIGNEDP.
References assign_temp(), can_conditionally_move_p(), EXPAND_NORMAL, expand_normal(), expand_operands(), get_def_for_expr_class(), gimple_assign_rhs1(), gimple_assign_rhs2(), gimple_assign_rhs_code(), promote_mode(), start_sequence(), and tcc_comparison.
| void copy_blkmode_from_reg | ( | ) |
Copy a BLKmode object of TYPE out of a register SRCREG into TARGET. This is used on targets that return BLKmode values in registers.
BLKmode registers created in the back-end shouldn't have survived.
If the structure doesn't take up a whole number of words, see whether
SRCREG is padded on the left or on the right. If it's on the left,
set PADDING_CORRECTION to the number of bits to skip.
In most ABIs, the structure will be returned at the least end of
the register, which translates to right padding on little-endian
targets and left padding on big-endian targets. The opposite
holds if the structure is returned at the most significant
end of the register. We can use a single move if we have an exact mode for the size.
And if we additionally have the same mode for a register.
This code assumes srcreg is at least a full word. If it isn't, copy it
into a new pseudo which is a full word. Copy the structure BITSIZE bits at a time. If the target lives in
memory, take care of not reading/writing past its end by selecting
a copy mode suited to BITSIZE. This should always be possible given
how it is computed.
If the target lives in register, make sure not to select a copy mode
larger than the mode of the register.
We could probably emit more efficient code for machines which do not use
strict alignment, but it doesn't seem worth the effort at the current
time. We need a new source operand each time xbitpos is on a
word boundary and when xbitpos == padding_correction
(the first time through). We need a new destination operand each time bitpos is on
a word boundary. Use xbitpos for the source extraction (right justified) and
bitpos for the destination store (left justified).
References targetm.
| rtx copy_blkmode_to_reg | ( | ) |
Copy BLKmode value SRC into a register of mode MODE. Return the register if it contains any data, otherwise return null. This is used on targets that return BLKmode values in registers.
If the structure doesn't take up a whole number of words, see
whether the register value should be padded on the left or on
the right. Set PADDING_CORRECTION to the number of padding
bits needed on the left side.
In most ABIs, the structure will be returned at the least end of
the register, which translates to right padding on little-endian
targets and left padding on big-endian targets. The opposite
holds if the structure is returned at the most significant
end of the register. Copy the structure BITSIZE bits at a time.
We need a new destination pseudo each time xbitpos is
on a word boundary and when xbitpos == padding_correction
(the first time through). Generate an appropriate register.
Clear the destination before we move anything into it.
We need a new source operand each time bitpos is on a word
boundary. Use bitpos for the source extraction (left justified) and
xbitpos for the destination store (right justified). Find the smallest integer mode large enough to hold the
entire structure. Have we found a large enough mode?
A suitable mode should have been found.
Referenced by expand_naked_return().
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If FOR_CTOR_P, return the number of top-level elements that a constructor must have in order for it to completely initialize a value of type TYPE. Return -1 if the number isn't known. If !FOR_CTOR_P, return an estimate of the number of scalars in TYPE.
Don't count flexible arrays, which are not supposed
to be initialized. Estimate the number of scalars in each field and pick the
maximum. Other estimates would do instead; the idea is simply
to make sure that the estimate is not sensitive to the ordering
of the fields. If the field doesn't span the whole union, add an extra
scalar for the rest.
References bit_position(), BLOCK_OP_NORMAL, clear_storage(), emit_clobber(), emit_move_insn(), expand_normal(), expr_size(), fields_length(), get_address_mode(), host_integerp(), initializer_zerop(), int_bit_position(), make_tree(), mostly_zeros_p(), offset, tree_low_cst(), expand_operand::value, and vec_safe_length().
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Generate code to calculate OPS, and exploded expression using a store-flag instruction and return an rtx for the result. OPS reflects a comparison. If TARGET is nonzero, store the result there if convenient. Return zero if there is no suitable set-flag instruction available on this machine. Once expand_expr has been called on the arguments of the comparison, we are committed to doing the store flag, since it is not safe to re-evaluate the expression. We emit the store-flag insn by calling emit_store_flag, but only expand the arguments if we have a reason to believe that emit_store_flag will be successful. If we think that it will, but it isn't, we have to simulate the store-flag with a set/jump/set sequence.
Don't crash if the comparison was erroneous.
We won't bother with BLKmode store-flag operations because it would mean
passing a lot of information to emit_store_flag. We won't bother with store-flag operations involving function pointers
when function pointers must be canonicalized before comparisons. For vector typed comparisons emit code to generate the desired
all-ones or all-zeros mask. Conveniently use the VEC_COND_EXPR
expander for this. Get the rtx comparison code to use. We know that EXP is a comparison
operation of some type. Some comparisons against 1 and -1 can be
converted to comparisons with zero. Do so here so that the tests
below will be aware that we have a comparison with zero. These
tests will not catch constants in the first operand, but constants
are rarely passed as the first operand. Put a constant second.
If this is an equality or inequality test of a single bit, we can
do this by shifting the bit being tested to the low-order bit and
masking the result with the constant 1. If the condition was EQ,
we xor it with 1. This does not require an scc insn and is faster
than an scc insn even if we have it.
The code to make this transformation was moved into fold_single_bit_test,
so we just call into the folder and expand its result. Try a cstore if possible.
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Subroutine of the next function. INDEX is the value being switched on, with the lowest value in the table already subtracted. MODE is its expected mode (needed if INDEX is constant). RANGE is the length of the jump table. TABLE_LABEL is a CODE_LABEL rtx for the table itself. DEFAULT_LABEL is a CODE_LABEL rtx to jump to if the index value is out of range. DEFAULT_PROBABILITY is the probability of jumping to the default label.
Do an unsigned comparison (in the proper mode) between the index
expression and the value which represents the length of the range.
Since we just finished subtracting the lower bound of the range
from the index expression, this comparison allows us to simultaneously
check that the original index expression value is both greater than
or equal to the minimum value of the range and less than or equal to
the maximum value of the range. If index is in range, it must fit in Pmode.
Convert to Pmode so we can index with it. Don't let a MEM slip through, because then INDEX that comes
out of PIC_CASE_VECTOR_ADDRESS won't be a valid address,
and break_out_memory_refs will go to work on it and mess it up. ??? The only correct use of CASE_VECTOR_MODE is the one inside the
GET_MODE_SIZE, because this indicates how large insns are. The other
uses should all be Pmode, because they are addresses. This code
could fail if addresses and insns are not the same size. If we are generating PIC code or if the table is PC-relative, the
table and JUMP_INSN must be adjacent, so don't output a BARRIER.
| rtx emit_block_move | ( | ) |
References direct_optab_handler().
Referenced by emit_move_change_mode(), and save_fixed_argument_area().
| rtx emit_block_move_hints | ( | rtx | x, |
| rtx | y, | ||
| rtx | size, | ||
| enum block_op_methods | method, | ||
| unsigned int | expected_align, | ||
| HOST_WIDE_INT | expected_size | ||
| ) |
Emit code to move a block Y to a block X. This may be done with string-move instructions, with multiple scalar move instructions, or with a library call. Both X and Y must be MEM rtx's (perhaps inside VOLATILE) with mode BLKmode. SIZE is an rtx that says how long they are. ALIGN is the maximum alignment we can assume they have. METHOD describes what kind of copy this is, and what mechanisms may be used. Return the address of the new block, if memcpy is called and returns it, 0 otherwise.
Make inhibit_defer_pop nonzero around the library call
to force it to pop the arguments right away. Make sure we've got BLKmode addresses; store_one_arg can decide that
block copy is more efficient for other large modes, e.g. DCmode. Set MEM_SIZE as appropriate for this block copy. The main place this
can be incorrect is coming from __builtin_memcpy. Since x and y are passed to a libcall, mark the corresponding
tree EXPR as addressable.
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References delete_insns_since(), emit_insn(), gen_rtx_REG(), get_last_insn(), and word_mode.
| rtx emit_block_move_via_libcall | ( | ) |
A subroutine of emit_block_move. Expand a call to memcpy. Return the return value from memcpy, 0 otherwise.
Emit code to copy the addresses of DST and SRC and SIZE into new
pseudos. We can then place those new pseudos into a VAR_DECL and
use them later. It is incorrect to use the libcall calling conventions to call
memcpy in this context. This could be a user call to memcpy and
the user may wish to examine the return value from memcpy. For
targets where libcalls and normal calls have different conventions
for returning pointers, we could end up generating incorrect code.
A subroutine of emit_block_move. Copy the data via an explicit loop. This is used only when libcalls are forbidden.
??? It'd be nice to copy in hunks larger than QImode.
References delete_insns_since(), emit_insn(), emit_move_insn(), gen_rtx_REG(), get_last_insn(), operand_subword(), and word_mode.
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Referenced by move_by_pieces_1().
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A subroutine of emit_block_move. Expand a movmem pattern; return true if successful.
Since this is a move insn, we don't care about volatility.
Try the most limited insn first, because there's no point
including more than one in the machine description unless
the more limited one has some advantage. We don't need MODE to be narrower than BITS_PER_HOST_WIDE_INT
here because if SIZE is less than the mode mask, as it is
returned by the macro, it will definitely be less than the
actual mode mask. ??? When called via emit_block_move_for_call, it'd be
nice if there were some way to inform the backend, so
that it doesn't fail the expansion because it thinks
emitting the libcall would be more efficient. The check above guarantees that this size conversion is valid.
| void emit_group_load | ( | ) |
Emit code to move a block SRC of type TYPE to a block DST, where DST is non-consecutive registers represented by a PARALLEL. SSIZE represents the total size of block ORIG_SRC in bytes, or -1 if not known.
Copy the extracted pieces into the proper (probable) hard regs.
Referenced by addr_expr_of_non_mem_decl_p(), emit_push_insn(), and resolve_operand_name_1().
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A subroutine of emit_group_load. Arguments as for emit_group_load, except that values are placed in TMPS[i], and must later be moved into corresponding XEXP (XVECEXP (DST, 0, i), 0) element.
...and back again.
Check for a NULL entry, used to indicate that the parameter goes
both on the stack and in registers. Process the pieces.
Handle trailing fragments that run over the size of the struct.
Arrange to shift the fragment to where it belongs.
extract_bit_field loads to the lsb of the reg. If we won't be loading directly from memory, protect the real source
from strange tricks we might play; but make sure that the source can
be loaded directly into the destination. Optimize the access just a bit.
Let emit_move_complex do the bulk of the work.
The following assumes that the concatenated objects all
have the same size. In this case, a simple calculation
can be used to determine the object and the bit field
to be extracted. FIXME: A SIMD parallel will eventually lead to a subreg of a
SIMD register, which is currently broken. While we get GCC
to emit proper RTL for these cases, let's dump to memory.
References extract_bit_field().
| rtx emit_group_load_into_temps | ( | ) |
Similar, but load SRC into new pseudos in a format that looks like PARALLEL. This can later be fed to emit_group_move to get things in the right place.
Convert the vector to look just like the original PARALLEL, except
with the computed values.
Referenced by call_expr_flags().
| void emit_group_move | ( | ) |
Emit code to move a block SRC to block DST, where SRC and DST are non-consecutive groups of registers, each represented by a PARALLEL.
Skip first entry if NULL.
Referenced by addr_expr_of_non_mem_decl_p().
| rtx emit_group_move_into_temps | ( | ) |
Move a group of registers represented by a PARALLEL into pseudos.
| void emit_group_store | ( | ) |
Emit code to move a block SRC to a block ORIG_DST of type TYPE, where SRC is non-consecutive registers represented by a PARALLEL. SSIZE represents the total size of block ORIG_DST, or -1 if not known.
Check for a NULL entry, used to indicate that the parameter goes
both on the stack and in registers. Copy the (probable) hard regs into pseudos.
If we won't be storing directly into memory, protect the real destination
from strange tricks we might play. We can get a PARALLEL dst if there is a conditional expression in
a return statement. In that case, the dst and src are the same,
so no action is necessary. It is unclear if we can ever reach here, but we may as well handle
it. Allocate a temporary, and split this into a store/load to/from
the temporary. Make life a bit easier for combine.
If the first element of the vector is the low part
of the destination mode, use a paradoxical subreg to
initialize the destination. If the first element wasn't the low part, try the last.
Otherwise, simply initialize the result to zero.
Process the pieces.
Handle trailing fragments that run over the size of the struct.
store_bit_field always takes its value from the lsb.
Move the fragment to the lsb if it's not already there. Optimize the access just a bit.
Copy from the pseudo into the (probable) hard reg.
|
static |
A subroutine of emit_move_insn_1. Generate a move from Y into X. MODE is known to be MODE_CC. Returns the last instruction emitted.
Assume all MODE_CC modes are equivalent; if we have movcc, use it.
Otherwise, find the MODE_INT mode of the same width.
References force_const_mem(), targetm, and use_anchored_address().
|
static |
A subroutine of emit_move_insn_1. Yet another lowpart generator. NEW_MODE and OLD_MODE are the same size. Return NULL if X cannot be represented in NEW_MODE. If FORCE is true, this will never happen, as we'll force-create a SUBREG if needed.
We don't have to worry about changing the address since the
size in bytes is supposed to be the same. Copy the MEM to change the mode and move any
substitutions from the old MEM to the new one. Note that we do want simplify_subreg's behavior of validating
that the new mode is ok for a hard register. If we were to use
simplify_gen_subreg, we would create the subreg, but would
probably run into the target not being able to implement it. Except, of course, when FORCE is true, when this is exactly what
we want. Which is needed for CCmodes on some targets.
References BLOCK_OP_NO_LIBCALL, emit_block_move(), emit_move_complex_push(), get_last_insn(), get_mode_alignment(), optab_handler(), push_operand(), and register_operand().
|
static |
A subroutine of emit_move_insn_1. Generate a move from Y into X. MODE is known to be complex. Returns the last instruction emitted.
Need to take special care for pushes, to maintain proper ordering
of the data, and possibly extra padding. See if we can coerce the target into moving both values at once, except
for floating point where we favor moving as parts if this is easy. Not possible if the values are inherently not adjacent.
Is possible if both are registers (or subregs of registers).
If one of the operands is a memory, and alignment constraints
are friendly enough, we may be able to do combined memory operations.
We do not attempt this if Y is a constant because that combination is
usually better with the by-parts thing below. For memory to memory moves, optimal behavior can be had with the
existing block move logic.
| rtx emit_move_complex_parts | ( | ) |
A subroutine of emit_move_complex. Perform the move from Y to X via two moves of the parts. Returns the last instruction emitted.
Show the output dies here. This is necessary for SUBREGs
of pseudos since we cannot track their lifetimes correctly;
hard regs shouldn't appear here except as return values.
| rtx emit_move_complex_push | ( | ) |
A subroutine of emit_move_complex. Generate a move from Y into X. X is known to satisfy push_operand, and MODE is known to be complex. Returns the last instruction emitted.
In case we output to the stack, but the size is smaller than the
machine can push exactly, we need to use move instructions. Note that the real part always precedes the imag part in memory
regardless of machine's endianness.
Referenced by emit_move_change_mode().
| rtx emit_move_insn | ( | ) |
Generate code to copy Y into X. Both Y and X must have the same mode, except that Y can be a constant with VOIDmode. This mode cannot be BLKmode; use emit_block_move for that. Return the last instruction emitted.
If the target's cannot_force_const_mem prevented the spill,
assume that the target's move expanders will also take care
of the non-legitimate constant. If X or Y are memory references, verify that their addresses are valid
for the machine.
References mem_autoinc_base(), and SET.
Referenced by addr_expr_of_non_mem_decl_p_1(), allocate_struct_function(), assign_parm_adjust_entry_rtl(), clear_by_pieces(), clear_storage(), copy_rtx_if_shared_1(), count_type_elements(), emit_block_move_via_loop(), expand_ffs(), expand_float(), expand_vector_broadcast(), gen_group_rtx(), get_inner_reference(), init_set_costs(), mathfn_built_in_1(), mem_overlaps_already_clobbered_arg_p(), noce_emit_store_flag(), push_block(), push_cfun(), resolve_operand_name_1(), restore_fixed_argument_area(), save_fixed_argument_area(), set_storage_via_libcall(), sjlj_assign_call_site_values(), split_edge_and_insert(), and split_iv().
| rtx emit_move_insn_1 | ( | ) |
Low level part of emit_move_insn. Called just like emit_move_insn, but assumes X and Y are basically valid.
Expand complex moves by moving real part and imag part.
If we can't find an integer mode, use multi words.
Try using a move pattern for the corresponding integer mode. This is
only safe when simplify_subreg can convert MODE constants into integer
constants. At present, it can only do this reliably if the value
fits within a HOST_WIDE_INT.
References plus_constant().
|
static |
A subroutine of emit_move_insn_1. Generate a move from Y into X. MODE is any multi-word or full-word mode that lacks a move_insn pattern. Note that you will get better code if you define such patterns, even if they must turn into multiple assembler instructions.
If X is a push on the stack, do the push now and replace
X with a reference to the stack pointer. If we are in reload, see if either operand is a MEM whose address
is scheduled for replacement. Do not generate code for a move if it would come entirely
from the undefined bits of a paradoxical subreg. If we can't get a part of Y, put Y into memory if it is a
constant. Otherwise, force it into a register. Then we must
be able to get a part of Y. Show the output dies here. This is necessary for SUBREGs
of pseudos since we cannot track their lifetimes correctly;
hard regs shouldn't appear here except as return values.
We never want to emit such a clobber after reload.
References targetm.
|
static |
A subroutine of emit_move_insn_1. X is a push_operand in MODE. Return an equivalent MEM that does not use an auto-increment.
Do not use anti_adjust_stack, since we don't want to update
stack_pointer_delta.
|
static |
A subroutine of emit_move_insn_1. Generate a move from Y into X using an integer mode of the same size as MODE. Returns the instruction emitted, or NULL if such a move could not be generated.
There must exist a mode of the exact size we require.
The target must support moves in this mode.
| void emit_push_insn | ( | rtx | x, |
| enum machine_mode | mode, | ||
| tree | type, | ||
| rtx | size, | ||
| unsigned int | align, | ||
| int | partial, | ||
| rtx | reg, | ||
| int | extra, | ||
| rtx | args_addr, | ||
| rtx | args_so_far, | ||
| int | reg_parm_stack_space, | ||
| rtx | alignment_pad | ||
| ) |
Generate code to push X onto the stack, assuming it has mode MODE and type TYPE. MODE is redundant except when X is a CONST_INT (since they don't carry mode info). SIZE is an rtx for the size of data to be copied (in bytes), needed only if X is BLKmode. ALIGN (in bits) is maximum alignment we can assume. If PARTIAL and REG are both nonzero, then copy that many of the first bytes of X into registers starting with REG, and push the rest of X. The amount of space pushed is decreased by PARTIAL bytes. REG must be a hard register in this case. If REG is zero but PARTIAL is not, take any all others actions for an argument partially in registers, but do not actually load any registers. EXTRA is the amount in bytes of extra space to leave next to this arg. This is ignored if an argument block has already been allocated. On a machine that lacks real push insns, ARGS_ADDR is the address of the bottom of the argument block for this call. We use indexing off there to store the arg. On machines with push insns, ARGS_ADDR is 0 when a argument block has not been preallocated. ARGS_SO_FAR is the size of args previously pushed for this call. REG_PARM_STACK_SPACE is nonzero if functions require stack space for arguments passed in registers. If nonzero, it will be the number of bytes required.
Decide where to pad the argument: `downward' for below,
`upward' for above, or `none' for don't pad it.
Default is below for small data on big-endian machines; else above. Invert direction if stack is post-decrement.
FIXME: why? Copy a block into the stack, entirely or partially.
A value is to be stored in an insufficiently aligned
stack slot; copy via a suitably aligned slot if
necessary. USED is now the # of bytes we need not copy to the stack
because registers will take care of them. If the partial register-part of the arg counts in its stack size,
skip the part of stack space corresponding to the registers.
Otherwise, start copying to the beginning of the stack space,
by setting SKIP to 0. Do it with several push insns if that doesn't take lots of insns
and if there is no difficulty with push insns that skip bytes
on the stack for alignment purposes. Here we avoid the case of a structure whose weak alignment
forces many pushes of a small amount of data,
and such small pushes do rounding that causes trouble. Push padding now if padding above and stack grows down,
or if padding below and stack grows up.
But if space already allocated, this has already been done. Otherwise make space on the stack and copy the data
to the address of that space. Deduct words put into registers from the size we must copy.
Get the address of the stack space.
In this case, we do not deal with EXTRA separately.
A single stack adjust will do. If the source is referenced relative to the stack pointer,
copy it to another register to stabilize it. We do not need
to do this if we know that we won't be changing sp. We do *not* set_mem_attributes here, because incoming arguments
may overlap with sibling call outgoing arguments and we cannot
allow reordering of reads from function arguments with stores
to outgoing arguments of sibling calls. We do, however, want
to record the alignment of the stack slot. ALIGN may well be better aligned than TYPE, e.g. due to
PARM_BOUNDARY. Assume the caller isn't lying. Scalar partly in registers.
# bytes of start of argument
that we must make space for but need not store. Push padding now if padding above and stack grows down,
or if padding below and stack grows up.
But if space already allocated, this has already been done. If we make space by pushing it, we might as well push
the real data. Otherwise, we can leave OFFSET nonzero
and leave the space uninitialized. Now NOT_STACK gets the number of words that we don't need to
allocate on the stack. Convert OFFSET to words too. If the partial register-part of the arg counts in its stack size,
skip the part of stack space corresponding to the registers.
Otherwise, start copying to the beginning of the stack space,
by setting SKIP to 0. If X is a hard register in a non-integer mode, copy it into a pseudo;
SUBREGs of such registers are not allowed. Loop over all the words allocated on the stack for this arg.
We can do it by words, because any scalar bigger than a word
has a size a multiple of a word. Push padding now if padding above and stack grows down,
or if padding below and stack grows up.
But if space already allocated, this has already been done. We do *not* set_mem_attributes here, because incoming arguments
may overlap with sibling call outgoing arguments and we cannot
allow reordering of reads from function arguments with stores
to outgoing arguments of sibling calls. We do, however, want
to record the alignment of the stack slot. ALIGN may well be better aligned than TYPE, e.g. due to
PARM_BOUNDARY. Assume the caller isn't lying. If part should go in registers, copy that part
into the appropriate registers. Do this now, at the end,
since mem-to-mem copies above may do function calls. Handle calls that pass values in multiple non-contiguous locations.
The Irix 6 ABI has examples of this.
References emit_group_load(), and move_block_to_reg().
|
static |
Emit and annotate a single push insn.
Notice the common case where we emitted exactly one insn.
|
static |
Emit single push insn.
If there is push pattern, use it. Otherwise try old way of throwing
MEM representing push operation to move expander. If we are to pad downward, adjust the stack pointer first and
then store X into the stack location using an offset. This is
because emit_move_insn does not know how to pad; it does not have
access to type. We have already decremented the stack pointer, so get the
previous value. We have already incremented the stack pointer, so get the
previous value. ??? This seems wrong if STACK_PUSH_CODE == POST_DEC.
??? This seems wrong if STACK_PUSH_CODE == POST_INC.
Function incoming arguments may overlap with sibling call
outgoing arguments and we cannot allow reordering of reads
from function arguments with stores to outgoing arguments
of sibling calls.
| bool emit_storent_insn | ( | ) |
Emits nontemporal store insn that moves FROM to TO. Returns true if this succeeded, false otherwise.
| void expand_assignment | ( | ) |
Expand an assignment that stores the value of FROM into TO. If NONTEMPORAL is true, try generating a nontemporal store.
Don't crash if the lhs of the assignment was erroneous.
Optimize away no-op moves without side-effects.
Handle misaligned stores.
The movmisalign<mode> pattern cannot fail, else the assignment
would silently be omitted. Assignment of a structure component needs special treatment
if the structure component's rtx is not simply a MEM.
Assignment of an array element at a constant index, and assignment of
an array element in an unaligned packed structure field, has the same
problem. Same for (partially) storing into a non-memory object. If the bitfield is volatile, we want to access it in the
field's mode, not the computed mode.
If a MEM has VOIDmode (external with incomplete type),
use BLKmode for it instead. We can get constant negative offsets into arrays with broken
user code. Translate this to a trap instead of ICEing. A constant address in TO_RTX can have VOIDmode, we must not try
to call force_reg for that case. Avoid that case. No action is needed if the target is not a memory and the field
lies completely outside that target. This can occur if the source
code contains an out-of-bounds access to a small array. Handle expand_expr of a complex value returning a CONCAT.
If the field is at offset zero, we could have been given the
DECL_RTX of the parent struct. Don't munge it. If the rhs is a function call and its value is not an aggregate,
call the function before we start to compute the lhs.
This is needed for correct code for cases such as
val = setjmp (buf) on machines where reference to val
requires loading up part of an address in a separate insn.
Don't do this if TO is a VAR_DECL or PARM_DECL whose DECL_RTL is REG
since it might be a promoted variable where the zero- or sign- extension
needs to be done. Handling this in the normal way is safe because no
computation is done before the call. The same is true for SSA names. Handle calls that return values in multiple non-contiguous locations.
The Irix 6 ABI has examples of this. Handle calls that return BLKmode values in registers.
Ordinary treatment. Expand TO to get a REG or MEM rtx.
Don't move directly into a return register.
If the source is itself a return value, it still is in a pseudo at
this point so we can move it back to the return register directly. Handle calls that return values in multiple non-contiguous locations.
The Irix 6 ABI has examples of this. In case we are returning the contents of an object which overlaps
the place the value is being stored, use a safe function when copying
a value through a pointer into a structure value return block. Compute FROM and store the value in the rtx we got.
Referenced by expand_asm_stmt().
Try to expand the conditional expression which is represented by TREEOP0 ? TREEOP1 : TREEOP2 using conditonal moves. If succeseds return the rtl reg which repsents the result. Otherwise return NULL_RTL.
If we cannot do a conditional move on the mode, try doing it
with the promoted mode. Try to emit the conditional move.
If we could do the conditional move, emit the sequence,
and return. Otherwise discard the sequence and fall back to code with
branches.
|
static |
Generate code for computing CONSTRUCTOR EXP. An rtx for the computed value is returned. If AVOID_TEMP_MEM is TRUE, instead of creating a temporary variable in memory NULL is returned and the caller needs to handle it differently.
Try to avoid creating a temporary at all. This is possible
if all of the initializer is zero.
FIXME: try to handle all [0..255] initializers we can handle
with memset. All elts simple constants => refer to a constant in memory. But
if this is a non-BLKmode mode, let it store a field at a time
since that should make a CONST_INT or CONST_DOUBLE when we
fold. Likewise, if we have a target we can use, it is best to
store directly into the target unless the type is large enough
that memcpy will be used. If we are making an initializer and
all operands are constant, put it in memory as well.
FIXME: Avoid trying to fill vector constructors piece-meal.
Output them with output_constant_def below unless we're sure
they're zeros. This should go away when vector initializers
are treated like VECTOR_CST instead of arrays. Handle calls that pass values in multiple non-contiguous
locations. The Irix 6 ABI has examples of this.
Referenced by expand_expr_real_1().
|
static |
A subroutine of expand_expr. Evaluate EXP, which is an ADDR_EXPR. The TARGET, TMODE and MODIFIER arguments are as for expand_expr.
Target mode of VOIDmode says "whatever's natural".
We can get called with some Weird Things if the user does silliness
like "(short) &a". In that case, convert_memory_address won't do
the right thing, so ignore the given target mode. Despite expand_expr claims concerning ignoring TMODE when not
strictly convenient, stuff breaks if we don't honor it. Note
that combined with the above, we only do this for pointer modes.
|
static |
A subroutine of expand_expr_addr_expr. Evaluate the address of EXP. The TARGET, TMODE and MODIFIER arguments are as for expand_expr.
If we are taking the address of a constant and are at the top level,
we have to use output_constant_def since we can't call force_const_mem
at top level. ??? This should be considered a front-end bug. We should not be
generating ADDR_EXPR of something that isn't an LVALUE. The only
exception here is STRING_CST. Everything must be something allowed by is_gimple_addressable.
This case will happen via recursion for &a->b.
Expand the initializer like constants above.
The real part of the complex number is always first, therefore
the address is the same as the address of the parent object. The imaginary part of the complex number is always second.
The expression is therefore always offset by the size of the
scalar type. Allow COMPOUND_LITERAL_EXPR in initializers, if e.g.
rtl_for_decl_init is called on DECL_INITIAL with
COMPOUNT_LITERAL_EXPRs in it, they aren't gimplified. FALLTHRU
If the object is a DECL, then expand it for its rtl. Don't bypass
expand_expr, as that can have various side effects; LABEL_DECLs for
example, may not have their DECL_RTL set yet. Expand the rtl of
CONSTRUCTORs too, which should yield a memory reference for the
constructor's contents. Assume language specific tree nodes can
be expanded in some interesting way. If the DECL isn't in memory, then the DECL wasn't properly
marked TREE_ADDRESSABLE, which will be either a front-end
or a tree optimizer bug. ??? Is this needed anymore?
Pass FALSE as the last argument to get_inner_reference although
we are expanding to RTL. The rationale is that we know how to
handle "aligning nodes" here: we can just bypass them because
they won't change the final object whose address will be returned
(they actually exist only for that purpose). We must have made progress.
For VIEW_CONVERT_EXPR, where the outer alignment is bigger than
inner alignment, force the inner to be sufficiently aligned. Someone beforehand should have rejected taking the address
of such an object.
|
static |
Return a MEM that contains constant EXP. DEFER is as for output_constant_def and MODIFIER is as for expand_expr.
| rtx expand_expr_real | ( | tree | exp, |
| rtx | target, | ||
| enum machine_mode | tmode, | ||
| enum expand_modifier | modifier, | ||
| rtx * | alt_rtl | ||
| ) |
expand_expr: generate code for computing expression EXP. An rtx for the computed value is returned. The value is never null. In the case of a void EXP, const0_rtx is returned. The value may be stored in TARGET if TARGET is nonzero. TARGET is just a suggestion; callers must assume that the rtx returned may not be the same as TARGET. If TARGET is CONST0_RTX, it means that the value will be ignored. If TMODE is not VOIDmode, it suggests generating the result in mode TMODE. But this is done only when convenient. Otherwise, TMODE is ignored and the value generated in its natural mode. TMODE is just a suggestion; callers must assume that the rtx returned may not have mode TMODE. Note that TARGET may have neither TMODE nor MODE. In that case, it probably will not be used. If MODIFIER is EXPAND_SUM then when EXP is an addition we can return an rtx of the form (MULT (REG ...) (CONST_INT ...)) or a nest of (PLUS ...) and (MINUS ...) where the terms are products as above, or REG or MEM, or constant. Ordinarily in such cases we would output mul or add instructions and then return a pseudo reg containing the sum. EXPAND_INITIALIZER is much like EXPAND_SUM except that it also marks a label as absolutely required (it can't be dead). It also makes a ZERO_EXTEND or SIGN_EXTEND instead of emitting extend insns. This is used for outputting expressions used in initializers. EXPAND_CONST_ADDRESS says that it is okay to return a MEM with a constant address even if that address is not normally legitimate. EXPAND_INITIALIZER and EXPAND_SUM also have this effect. EXPAND_STACK_PARM is used when expanding to a TARGET on the stack for a call parameter. Such targets require special care as we haven't yet marked TARGET so that it's safe from being trashed by libcalls. We don't want to use TARGET for anything but the final result; Intermediate values must go elsewhere. Additionally, calls to emit_block_move will be flagged with BLOCK_OP_CALL_PARM. If EXP is a VAR_DECL whose DECL_RTL was a MEM with an invalid address, and ALT_RTL is non-NULL, then *ALT_RTL is set to the DECL_RTL of the VAR_DECL. *ALT_RTL is also set if EXP is a COMPOUND_EXPR whose second argument is such a VAR_DECL, and so on recursively.
Handle ERROR_MARK before anybody tries to access its type.
| rtx expand_expr_real_1 | ( | tree | exp, |
| rtx | target, | ||
| enum machine_mode | tmode, | ||
| enum expand_modifier | modifier, | ||
| rtx * | alt_rtl | ||
| ) |
An operation in what may be a bit-field type needs the
result to be reduced to the precision of the bit-field type,
which is narrower than that of the type's mode. If we are going to ignore this result, we need only do something
if there is a side-effect somewhere in the expression. If there
is, short-circuit the most common cases here. Note that we must
not call expand_expr with anything but const0_rtx in case this
is an initial expansion of a size that contains a PLACEHOLDER_EXPR. Ensure we reference a volatile object even if value is ignored, but
don't do this if all we are doing is taking its address. Use subtarget as the target for operand 0 of a binary operation.
??? ivopts calls expander, without any preparation from
out-of-ssa. So fake instructions as if this was an access to the
base variable. This unnecessarily allocates a pseudo, see how we can
reuse it, if partition base vars have it set already. For EXPAND_INITIALIZER try harder to get something simpler.
If a static var's type was incomplete when the decl was written,
but the type is complete now, lay out the decl now. ... fall through ...
Record writes to register variables.
Ensure variable marked as used even if it doesn't go through
a parser. If it hasn't be used yet, write out an external
definition. Show we haven't gotten RTL for this yet.
Variables inherited from containing functions should have
been lowered by this point. ??? C++ creates functions that are not TREE_STATIC.
This is the case of an array whose size is to be determined
from its initializer, while the initializer is still being parsed.
??? We aren't parsing while expanding anymore. If DECL_RTL is memory, we are in the normal case and the
address is not valid, get the address into a register. If we got something, return it. But first, set the alignment
if the address is a register. If the mode of DECL_RTL does not match that of the decl,
there are two cases: we are dealing with a BLKmode value
that is returned in a register, or we are dealing with
a promoted value. In the latter case, return a SUBREG
of the wanted mode, but mark it so that we know that it
was already extended. Get the signedness to be used for this variable. Ensure we get
the same mode we got when the variable was declared. If optimized, generate immediate CONST_DOUBLE
which will be turned into memory by reload if necessary.
We used to force a register so that loop.c could see it. But
this does not allow gen_* patterns to perform optimizations with
the constants. It also produces two insns in cases like "x = 1.0;".
On most machines, floating-point constants are not permitted in
many insns, so we'd end up copying it to a register in any case.
Now, we do the copying in expand_binop, if appropriate. Handle evaluating a complex constant in a CONCAT target.
Move the real and imaginary parts separately.
... fall through ...
temp contains a constant address.
On RISC machines where a constant address isn't valid,
make some insns to get that address into a register. We can indeed still hit this case, typically via builtin
expanders calling save_expr immediately before expanding
something. Assume this means that we only have to deal
with non-BLKmode values. If we don't need the result, just ensure we evaluate any
subexpressions. If the target does not have special handling for unaligned
loads of mode then it can use regular moves for them. We've already validated the memory, and we're creating a
new pseudo destination. The predicates really can't fail,
nor can the generator. Handle expansion of non-aliased memory with non-BLKmode. That
might end up in a register. We've already validated the memory, and we're creating a
new pseudo destination. The predicates really can't fail,
nor can the generator. Fold an expression like: "foo"[2].
This is not done in fold so it won't happen inside &.
Don't fold if this is for wide characters since it's too
difficult to do correctly and this is a very rare case. If this is a constant index into a constant array,
just get the value from the array. Handle both the cases when
we have an explicit constructor and when our operand is a variable
that was declared const. If VALUE is a CONSTRUCTOR, this
optimization is only useful if
this doesn't store the CONSTRUCTOR
into memory. If it does, it is more
efficient to just load the data from
the array directly. Optimize the special case of a zero lower bound.
We convert the lower bound to sizetype to avoid problems
with constant folding. E.g. suppose the lower bound is
1 and its mode is QI. Without the conversion
(ARRAY + (INDEX - (unsigned char)1))
becomes
(ARRAY + (-(unsigned char)1) + INDEX)
which becomes
(ARRAY + 255 + INDEX). Oops! If the operand is a CONSTRUCTOR, we can just extract the
appropriate field if it is present. We can normally use the value of the field in the
CONSTRUCTOR. However, if this is a bitfield in
an integral mode that we can fit in a HOST_WIDE_INT,
we must mask only the number of bits in the bitfield,
since this is done implicitly by the constructor. If
the bitfield does not meet either of those conditions,
we can't do this optimization. If we got back the original object, something is wrong. Perhaps
we are evaluating an expression too early. In any event, don't
infinitely recurse. If TEM's type is a union of variable size, pass TARGET to the inner
computation, since it will need a temporary and TARGET is known
to have to do. This occurs in unchecked conversion in Ada. If the bitfield is volatile, we want to access it in the
field's mode, not the computed mode.
If a MEM has VOIDmode (external with incomplete type),
use BLKmode for it instead. If we have either an offset, a BLKmode result, or a reference
outside the underlying object, we must force it to memory.
Such a case can occur in Ada if we have unchecked conversion
of an expression from a scalar type to an aggregate type or
for an ARRAY_RANGE_REF whose type is BLKmode, or if we were
passed a partially uninitialized object or a view-conversion
to a larger size. Handle CONCAT first.
Otherwise force into memory.
If this is a constant, put it in a register if it is a legitimate
constant and we don't need a memory reference. Otherwise, if this is a constant, try to force it to the constant
pool. Note that back-ends, e.g. MIPS, may refuse to do so if it
is a legitimate constant. Otherwise, if this is a constant or the object is not in memory
and need be, put it there. A constant address in OP0 can have VOIDmode, we must
not try to call force_reg in that case. If OFFSET is making OP0 more aligned than BIGGEST_ALIGNMENT,
record its alignment as BIGGEST_ALIGNMENT. Don't forget about volatility even if this is a bitfield.
In cases where an aligned union has an unaligned object
as a field, we might be extracting a BLKmode value from
an integer-mode (e.g., SImode) object. Handle this case
by doing the extract into an object as wide as the field
(which we know to be the width of a basic mode), then
storing into memory, and changing the mode to BLKmode. If the field is volatile, we always want an aligned
access. Do this in following two situations:
1. the access is not already naturally
aligned, otherwise "normal" (non-bitfield) volatile fields
become non-addressable.
2. the bitsize is narrower than the access size. Need
to extract bitfields from the access. If the field isn't aligned enough to fetch as a memref,
fetch it as a bit field. If the type and the field are a constant size and the
size of the type isn't the same size as the bitfield,
we must use bitfield operations. In this case, BITPOS must start at a byte boundary and
TARGET, if specified, must be a MEM. If the result is a record type and BITSIZE is narrower than
the mode of OP0, an integral mode, and this is a big endian
machine, we must put the field into the high-order bits. If the result type is BLKmode, store the data into a temporary
of the appropriate type, but with the mode corresponding to the
mode for the data we have (op0's mode). It's tempting to make
this a constant type, since we know it's only being stored once,
but that can cause problems if we are taking the address of this
COMPONENT_REF because the MEM of any reference via that address
will have flags corresponding to the type, which will not
necessarily be constant. If the result is BLKmode, use that to access the object
now as well. Get a reference to just this component.
If op0 is a temporary because of forcing to memory, pass only the
type to set_mem_attributes so that the original expression is never
marked as ADDRESSABLE through MEM_EXPR of the temporary. All valid uses of __builtin_va_arg_pack () are removed during
inlining. Check for a built-in function.
If we are converting to BLKmode, try to avoid an intermediate
temporary by fetching an inner memory reference. ??? We should work harder and deal with non-zero offsets.
See the normal_inner_ref case for the rationale.
Get a reference to just this component.
If the input and output modes are both the same, we are done.
If neither mode is BLKmode, and both modes are the same size
then we can use gen_lowpart. If both types are integral, convert from one mode to the other.
As a last resort, spill op0 to memory, and reload it in a
different mode. If the operand is not a MEM, force it into memory. Since we
are going to be changing the mode of the MEM, don't call
force_const_mem for constants because we don't allow pool
constants to change mode. At this point, OP0 is in the correct mode. If the output type is
such that the operand is known to be aligned, indicate that it is.
Otherwise, we need only be concerned about alignment for non-BLKmode
results. ??? Copying the MEM without substantially changing it might
run afoul of the code handling volatile memory references in
store_expr, which assumes that TARGET is returned unmodified
if it has been used. If the target does have special handling for unaligned
loads of mode then use them. We've already validated the memory, and we're creating a
new pseudo destination. The predicates really can't
fail. Nor can the insn generator.
Check for |= or &= of a bitfield of size one into another bitfield
of size 1. In this case, (unless we need the result of the
assignment) we can do this more efficiently with a
test followed by an assignment, if necessary.
??? At this point, we can't get a BIT_FIELD_REF here. But if
things change so we do, this code should be enhanced to
support it. Expanded in cfgexpand.c.
Lowered by tree-eh.c.
Lowered by gimplify.c.
Function descriptors are not valid except for as
initialization constants, and should not be expanded. WITH_SIZE_EXPR expands to its first argument. The caller should
have pulled out the size to use in whatever context it needed.
References array_ref_low_bound(), compare_tree_int(), expand_constructor(), expand_expr(), fold(), fold_convert_loc(), gen_int_mode(), integer_zerop(), size_diffop_loc(), tree_int_cst_equal(), and expand_operand::value.
| rtx expand_expr_real_2 | ( | sepops | ops, |
| rtx | target, | ||
| enum machine_mode | tmode, | ||
| enum expand_modifier | modifier | ||
| ) |
We should be called only on simple (binary or unary) expressions,
exactly those that are valid in gimple expressions that aren't
GIMPLE_SINGLE_RHS (or invalid). We should be called only if we need the result.
An operation in what may be a bit-field type needs the
result to be reduced to the precision of the bit-field type,
which is narrower than that of the type's mode. Use subtarget as the target for operand 0 of a binary operation.
If both input and output are BLKmode, this conversion isn't doing
anything except possibly changing memory attribute. Store data into beginning of memory target.
Store this field into a union of the proper type.
Return the entire union.
If the signedness of the conversion differs and OP0 is
a promoted SUBREG, clear that indication since we now
have to do the proper extension. If OP0 is a constant, just convert it into the proper mode.
Conversions between pointers to the same address space should
have been implemented via CONVERT_EXPR / NOP_EXPR. Ask target code to handle conversion between pointers
to overlapping address spaces. For disjoint address spaces, converting anything but
a null pointer invokes undefined behaviour. We simply
always return a null pointer here. Even though the sizetype mode and the pointer's mode can be different
expand is able to handle this correctly and get the correct result out
of the PLUS_EXPR code. Make sure to sign-extend the sizetype offset in a POINTER_PLUS_EXPR
if sizetype precision is smaller than pointer precision. If sizetype precision is larger than pointer precision, truncate the
offset to have matching modes. If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and
something else, make sure we add the register to the constant and
then to the other thing. This case can occur during strength
reduction and doing it this way will produce better code if the
frame pointer or argument pointer is eliminated.
fold-const.c will ensure that the constant is always in the inner
PLUS_EXPR, so the only case we need to do anything about is if
sp, ap, or fp is our second argument, in which case we must swap
the innermost first argument and our second argument. If the result is to be ptr_mode and we are adding an integer to
something, we might be forming a constant. So try to use
plus_constant. If it produces a sum and we can't accept it,
use force_operand. This allows P = &ARR[const] to generate
efficient code on machines where a SYMBOL_REF is not a valid
address.
If this is an EXPAND_SUM call, always return the sum. Use immed_double_const to ensure that the constant is
truncated according to the mode of OP1, then sign extended
to a HOST_WIDE_INT. Using the constant directly can result
in non-canonical RTL in a 64x32 cross compile. Return a PLUS if modifier says it's OK.
Use immed_double_const to ensure that the constant is
truncated according to the mode of OP1, then sign extended
to a HOST_WIDE_INT. Using the constant directly can result
in non-canonical RTL in a 64x32 cross compile. Use TER to expand pointer addition of a negated value
as pointer subtraction. No sense saving up arithmetic to be done
if it's all in the wrong mode to form part of an address.
And force_operand won't know whether to sign-extend or
zero-extend. For initializers, we are allowed to return a MINUS of two
symbolic constants. Here we handle all cases when both operands
are constant. Handle difference of two symbolic constants,
for the sake of an initializer. If the last operand is a CONST_INT, use plus_constant of
the negated constant. Else make the MINUS. No sense saving up arithmetic to be done
if it's all in the wrong mode to form part of an address.
And force_operand won't know whether to sign-extend or
zero-extend. Convert A - const to A + (-const).
If first operand is constant, swap them.
Thus the following special case checks need only
check the second operand. First, check if we have a multiplication of one signed and one
unsigned operand. op0 and op1 might still be constant, despite the above
!= INTEGER_CST check. Handle it. Check for a multiplication with matching signedness.
op0 and op1 might still be constant, despite the above
!= INTEGER_CST check. Handle it. op0 and op1 might still be constant, despite the above
!= INTEGER_CST check. Handle it. If there is no insn for FMA, emit it as __builtin_fma{,f,l}
call. If this is a fixed-point operation, then we cannot use the code
below because "expand_mult" doesn't support sat/no-sat fixed-point
multiplications. If first operand is constant, swap them.
Thus the following special case checks need only
check the second operand. Attempt to return something suitable for generating an
indexed address, for machines that support that. If this is a fixed-point operation, then we cannot use the code
below because "expand_divmod" doesn't support sat/no-sat fixed-point
divisions. Possible optimization: compute the dividend with EXPAND_SUM
then if the divisor is constant can optimize the case
where some terms of the dividend have coeffs divisible by it. expand_float can't figure out what to do if FROM has VOIDmode.
So give it the correct mode. With -O, cse will optimize this. ABS_EXPR is not valid for complex arguments.
Unsigned abs is simply the operand. Testing here means we don't
risk generating incorrect code below. First try to do it with a special MIN or MAX instruction.
If that does not win, use a conditional jump to select the proper
value. At this point, a MEM target is no longer useful; we will get better
code without it. If op1 was placed in target, swap op0 and op1.
We generate better code and avoid problems with op1 mentioning
target by forcing op1 into a pseudo if it isn't a constant. Canonicalize to comparisons against 0.
Converting (a >= 1 ? a : 1) into (a > 0 ? a : 1)
or (a != 0 ? a : 1) for unsigned.
For MIN we are safe converting (a <= 1 ? a : 1)
into (a <= 0 ? a : 1) Converting (a >= -1 ? a : -1) into (a >= 0 ? a : -1)
and (a <= -1 ? a : -1) into (a < 0 ? a : -1) Use a conditional move if possible.
??? Same problem as in expmed.c: emit_conditional_move
forces a stack adjustment via compare_from_rtx, and we
lose the stack adjustment if the sequence we are about
to create is discarded. Try to emit the conditional move.
If we could do the conditional move, emit the sequence,
and return. Otherwise discard the sequence and fall back to code with
branches. In case we have to reduce the result to bitfield precision
for unsigned bitfield expand this as XOR with a proper constant
instead. ??? Can optimize bitwise operations with one arg constant.
Can optimize (a bitwise1 n) bitwise2 (a bitwise3 b)
and (a bitwise1 b) bitwise2 b (etc)
but that is probably not worth while. fall through
If this is a fixed-point operation, then we cannot use the code
below because "expand_shift" doesn't support sat/no-sat fixed-point
shifts. Could determine the answer when only additive constants differ. Also,
the addition of one can be handled by changing the condition. Use a compare and a jump for BLKmode comparisons, or for function
type comparisons is HAVE_canonicalize_funcptr_for_compare. Make sure we don't have a hard reg (such as function's return
value) live across basic blocks, if not optimizing. Get the rtx code of the operands.
If target overlaps with op1, then either we need to force
op1 into a pseudo (if target also overlaps with op0),
or write the complex parts in reverse order. Move the imaginary (op1) and real (op0) parts to their
location. Move the real (op0) and imaginary (op1) parts to their location.
The signedness is determined from input operand.
Careful here: if the target doesn't support integral vector modes,
a constant selection vector could wind up smooshed into a normal
integral constant. A COND_EXPR with its type being VOID_TYPE represents a
conditional jump and is handled in
expand_gimple_cond_expr. Note that COND_EXPRs whose type is a structure or union
are required to be constructed to contain assignments of
a temporary variable, so that we can evaluate them here
for side effect only. If type is void, we must do likewise. If we are not to produce a result, we have no target. Otherwise,
if a target was specified use it; it will not be used as an
intermediate target unless it is safe. If no target, use a
temporary. Here to do an ordinary binary operator.
Bitwise operations do not need bitfield reduction as we expect their
operands being properly truncated.
|
static |
Subroutine of expand_expr. Expand the two operands of a binary expression EXP0 and EXP1 placing the results in OP0 and OP1. The value may be stored in TARGET if TARGET is nonzero. The MODIFIER argument is as documented by expand_expr.
If we need to preserve evaluation order, copy exp0 into its own
temporary variable so that it can't be clobbered by exp1.
Referenced by convert_tree_comp_to_rtx().
| HOST_WIDE_INT find_args_size_adjust | ( | ) |
A utility routine used here, in reload, and in try_split. The insns
after PREV up to and including LAST are known to adjust the stack,
with a final value of END_ARGS_SIZE. Iterate backward from LAST
placing notes as appropriate. PREV may be NULL, indicating the
entire insn sequence prior to LAST should be scanned.
The set of allowed stack pointer modifications is small:
(1) One or more auto-inc style memory references (aka pushes),
(2) One or more addition/subtraction with the SP as destination,
(3) A single move insn with the SP as destination,
(4) A call_pop insn,
(5) Noreturn call insns if !ACCUMULATE_OUTGOING_ARGS.
Insns in the sequence that do not modify the SP are ignored,
except for noreturn calls.
The return value is the amount of adjustment that can be trivially
verified, via immediate operand or auto-inc. If the adjustment
cannot be trivially extracted, the return value is INT_MIN. Look for a call_pop pattern.
We have to allow non-call_pop patterns for the case
of emit_single_push_insn of a TLS address. All call_pop have a stack pointer adjust in the parallel.
The call itself is always first, and the stack adjust is
usually last, so search from the end. We'd better have found the stack pointer adjust.
Fall through to process the extracted SET and DEST
as if it was a standalone insn. ??? Some older ports use a parallel with a stack adjust
and a store for a PUSH_ROUNDING pattern, rather than a
PRE/POST_MODIFY rtx. Don't force them to update yet... ??? See h8300 and m68k, pushqi1.
We do not expect an auto-inc of the sp in the parallel.
Look for direct modifications of the stack pointer.
Look for a trivial adjustment, otherwise assume nothing.
Note that the SPU restore_stack_block pattern refers to
the stack pointer in V4SImode. Consider that non-trivial. ??? Reload can generate no-op moves, which will be cleaned
up later. Recognize it and continue searching. Otherwise only think about autoinc patterns.
| int fixup_args_size_notes | ( | ) |
References anti_adjust_stack(), move_by_pieces(), and none.
Referenced by expand_null_return_1().
|
static |
Return true if field F of structure TYPE is a flexible array.
| rtx force_operand | ( | ) |
Given an rtx VALUE that may contain additions and multiplications, return an equivalent value that just refers to a register, memory, or constant. This is done by generating instructions to perform the arithmetic and returning a pseudo-register containing the value. The returned value may be a REG, SUBREG, MEM or constant.
Use subtarget as the target for operand 0 of a binary operation.
Check for subreg applied to an expression produced by loop optimizer.
Check for a PIC address load.
Check for an addition with OP2 a constant integer and our first
operand a PLUS of a virtual register and something else. In that
case, we want to emit the sum of the virtual register and the
constant first and then add the other value. This allows virtual
register instantiation to simply modify the constant rather than
creating another one around this addition. On machines that have insn scheduling, we want all memory reference to be
explicit, so we need to deal with such paradoxical SUBREGs.
Referenced by split_edge_and_insert().
| rtx gen_group_rtx | ( | ) |
Generate a PARALLEL rtx for a new non-consecutive group of registers from ORIG, where ORIG is a non-consecutive group of registers represented by a PARALLEL. The clone is identical to the original except in that the original set of registers is replaced by a new set of pseudo registers. The new set has the same modes as the original set.
Skip a NULL entry in first slot.
References emit_move_insn(), and gen_reg_rtx().
|
static |
In the C++ memory model, consecutive bit fields in a structure are considered one memory location. Given a COMPONENT_REF EXP at position (BITPOS, OFFSET), this function returns the bit range of consecutive bits in which this COMPONENT_REF belongs. The values are returned in *BITSTART and *BITEND. *BITPOS and *OFFSET may be adjusted in the process. If the access does not need to be restricted, 0 is returned in both *BITSTART and *BITEND.
If we do not have a DECL_BIT_FIELD_REPRESENTATIVE there is no
need to limit the range we can access. If we have a DECL_BIT_FIELD_REPRESENTATIVE but the enclosing record is
part of a larger bit field, then the representative does not serve any
useful purpose. This can occur in Ada. Compute the adjustment to bitpos from the offset of the field
relative to the representative. DECL_FIELD_OFFSET of field and
repr are the same by construction if they are not constants,
see finish_bitfield_layout. If the adjustment is larger than bitpos, we would have a negative bit
position for the lower bound and this may wreak havoc later. This can
occur only if we have a non-null offset, so adjust offset and bitpos
to make the lower bound non-negative.
|
static |
Return the defining gimple statement for SSA_NAME NAME if it is an assigment and the code of the expresion on the RHS is CODE. Return NULL otherwise.
References copy_to_mode_reg(), emit_insn(), store_by_pieces_d::explicit_inc_to, gen_add2_insn(), plus_constant(), and store_by_pieces_d::to_addr.
|
static |
Return the defining gimple statement for SSA_NAME NAME if it is an assigment and the class of the expresion on the RHS is CLASS. Return NULL otherwise.
Referenced by convert_tree_comp_to_rtx().
| tree get_inner_reference | ( | tree | exp, |
| HOST_WIDE_INT * | pbitsize, | ||
| HOST_WIDE_INT * | pbitpos, | ||
| tree * | poffset, | ||
| enum machine_mode * | pmode, | ||
| int * | punsignedp, | ||
| int * | pvolatilep, | ||
| bool | keep_aligning | ||
| ) |
Given an expression EXP that may be a COMPONENT_REF, a BIT_FIELD_REF, an ARRAY_REF, or an ARRAY_RANGE_REF, look for nested operations of these codes and find the ultimate containing object, which we return. We set *PBITSIZE to the size in bits that we want, *PBITPOS to the bit position, and *PUNSIGNEDP to the signedness of the field. If the position of the field is variable, we store a tree giving the variable offset (in units) in *POFFSET. This offset is in addition to the bit position. If the position is not variable, we store 0 in *POFFSET. If any of the extraction expressions is volatile, we store 1 in *PVOLATILEP. Otherwise we don't change that. If the field is a non-BLKmode bit-field, *PMODE is set to VOIDmode. Otherwise, it is a mode that can be used to access the field. If the field describes a variable-sized object, *PMODE is set to BLKmode and *PBITSIZE is set to -1. An access cannot be made in this case, but the address of the object can be found. If KEEP_ALIGNING is true and the target is STRICT_ALIGNMENT, we don't look through nodes that serve as markers of a greater alignment than the one that can be deduced from the expression. These nodes make it possible for front-ends to prevent temporaries from being created by the middle-end on alignment considerations. For that purpose, the normal operating mode at high-level is to always pass FALSE so that the ultimate containing object is really returned; moreover, the associated predicate handled_component_p will always return TRUE on these nodes, thus indicating that they are essentially handled by get_inner_reference. TRUE should only be passed when the caller is scanning the expression in order to build another representation and specifically knows how to handle these nodes; as such, this is the normal operating mode in the RTL expanders.
First get the mode, signedness, and size. We do this from just the
outermost expression. Volatile bitfields should be accessed in the mode of the
field's type, not the mode computed based on the bit
size. For vector types, with the correct size of access, use the mode of
inner type. Compute cumulative bit-offset for nested component-refs and array-refs,
and find the ultimate containing object. If this field hasn't been filled in yet, don't go past it.
This should only happen when folding expressions made during
type construction. ??? Right now we don't do anything with DECL_OFFSET_ALIGN.
We assume all arrays have sizes that are a multiple of a byte.
First subtract the lower bound, if any, in the type of the
index, then convert to sizetype and multiply by the size of
the array element. Hand back the decl for MEM[&decl, off].
If any reference in the chain is volatile, the effect is volatile.
If OFFSET is constant, see if we can return the whole thing as a
constant bit position. Make sure to handle overflow during
this conversion. Otherwise, split it up.
Avoid returning a negative bitpos as this may wreak havoc later.
TEM is the bitpos rounded to BITS_PER_UNIT towards -Inf.
Subtract it to BIT_OFFSET and add it (scaled) to OFFSET. We can use BLKmode for a byte-aligned BLKmode bitfield.
References emit_move_insn(), and gen_reg_rtx().
Referenced by delegitimize_mem_from_attrs(), fold_unary_ignore_overflow_loc(), invert_truthvalue_loc(), native_interpret_real(), and tree_to_aff_combination().
| rtx get_personality_function | ( | ) |
Extracts the personality function of DECL and returns the corresponding libfunc.
|
static |
Return X if X can be used as a subtarget in a sequence of arithmetic operations.
Only registers can be subtargets.
Don't use hard regs to avoid extending their life.
References addr_expr_of_non_mem_decl_p_1().
| unsigned HOST_WIDE_INT highest_pow2_factor | ( | ) |
Return the highest power of two that EXP is known to be a multiple of. This is used in updating alignment of MEMs in array references.
We can find the lowest bit that's a one. If the low
HOST_BITS_PER_WIDE_INT bits are zero, return BIGGEST_ALIGNMENT.
We need to handle this case since we can find it in a COND_EXPR,
a MIN_EXPR, or a MAX_EXPR. If the constant overflows, we have an
erroneous program, so return BIGGEST_ALIGNMENT to avoid any
later ICE. Note: tree_low_cst is intentionally not used here,
we don't care about the upper bits. The highest power of two of a bit-and expression is the maximum of
that of its operands. We typically get here for a complex LHS and
a constant negative power of two on the RHS to force an explicit
alignment, so don't bother looking at the LHS.
|
static |
|
static |
Similar, except that the alignment requirements of TARGET are taken into account. Assume it is at least as aligned as its type, unless it is a COMPONENT_REF in which case the layout of the structure gives the alignment.
| void init_block_clear_fn | ( | ) |
References expand_expr(), and EXPAND_NORMAL.
| void init_block_move_fn | ( | ) |
| void init_expr | ( | void | ) |
This is run at the start of compiling a function.
Referenced by blocks_nreverse(), and vect_can_advance_ivs_p().
| void init_expr_target | ( | void | ) |
This is run to set up which modes can be used directly in memory and to initialize the block move optab. It is run at the beginning of compilation and when the target is reinitialized.
Try indexing by frame ptr and try by stack ptr.
It is known that on the Convex the stack ptr isn't a valid index.
With luck, one or the other is valid on any machine. A scratch register we can modify in-place below to avoid
useless RTL allocations. See if there is some register that can be used in this mode and
directly loaded or stored from memory.
|
static |
|
static |
Subroutine of above: returns 1 if OFFSET corresponds to an offset that when applied to the address of EXP produces an address known to be aligned more than BIGGEST_ALIGNMENT.
Strip off any conversions.
We must now have a BIT_AND_EXPR with a constant that is one less than
power of 2 and which is larger than BIGGEST_ALIGNMENT. Look at the first operand of BIT_AND_EXPR and strip any conversion.
It must be NEGATE_EXPR. Then strip any more conversions. This must now be the address of EXP.
| rtx maybe_emit_group_store | ( | ) |
Return a form of X that does not use a PARALLEL. TYPE is the type of the value stored in X.
|
static |
A utility routine that returns the base of an auto-inc memory, or NULL.
Referenced by emit_move_insn().
|
inlinestatic |
Returns true if the MEM_REF REF refers to an object that does not reside in memory and has non-BLKmode.
|
static |
Return 1 if EXP contains mostly (3/4) zeros.
Referenced by count_type_elements().
| void move_block_from_reg | ( | ) |
Copy all or part of a BLKmode value X out of registers starting at REGNO. The number of registers to be filled is NREGS.
See if the machine can do this with a store multiple insn.
| void move_block_to_reg | ( | ) |
Copy all or part of a value X into registers starting at REGNO. The number of registers to be filled is NREGS.
See if the machine can do this with a load multiple insn.
References gen_reg_rtx(), and offset.
Referenced by emit_push_insn(), and mem_overlaps_already_clobbered_arg_p().
| rtx move_by_pieces | ( | rtx | to, |
| rtx | from, | ||
| unsigned HOST_WIDE_INT | len, | ||
| unsigned int | align, | ||
| int | endp | ||
| ) |
Generate several move instructions to copy LEN bytes from block FROM to block TO. (These are MEM rtx's with BLKmode). If PUSH_ROUNDING is defined and TO is NULL, emit_single_push_insn is used to push FROM to the stack. ALIGN is maximum stack alignment we can assume. If ENDP is 0 return to, if ENDP is 1 return memory at the end ala mempcpy, and if ENDP is 2 return memory the end minus one byte ala stpcpy.
If copying requires more than two move insns,
copy addresses to registers (to make displacements shorter)
and use post-increment if available. Find the mode of the largest move...
MODE might not be used depending on the definitions of the
USE_* macros below. First move what we can in the largest integer mode, then go to
successively smaller modes. The code above should have handled everything.
References move_by_pieces_d::autinc_from, copy_to_mode_reg(), move_by_pieces_d::explicit_inc_from, move_by_pieces_d::from_addr, and plus_constant().
Referenced by fixup_args_size_notes(), and move_by_pieces_1().
|
static |
Subroutine of move_by_pieces. Move as many bytes as appropriate with move instructions for mode MODE. GENFUN is the gen_... function to make a move insn for that mode. DATA has all the other info.
References block_move_libcall_safe_for_call_parm(), BLOCK_OP_CALL_PARM, BLOCK_OP_NO_LIBCALL, BLOCK_OP_NORMAL, BLOCK_OP_TAILCALL, emit_block_move_via_movmem(), mark_addressable(), move_by_pieces(), and set_mem_size().
| unsigned HOST_WIDE_INT move_by_pieces_ninsns | ( | unsigned HOST_WIDE_INT | l, |
| unsigned int | align, | ||
| unsigned int | max_size | ||
| ) |
Return number of insns required to move L bytes by pieces. ALIGN (in bits) is maximum alignment we can assume.
|
static |
A subroutine of expand_assignment. Optimize FIELD op= VAL, where FIELD is a bitfield. Returns true if the optimization was successful, and there's nothing else to do.
If OP0 is an SSA_NAME, then we want to walk the use-def chain
to find its initialization. Hopefully the initialization will
be from a bitfield load. We want to eventually have OP0 be the same as TO, which
should be a bitfield. If the bit field covers the whole REG/MEM, store_field
will likely generate better code. We can't handle fields split across multiple entities.
For now, just optimize the case of the topmost bitfield
where we don't need to do any masking and also
1 bit bitfields where xor can be used.
We might win by one instruction for the other bitfields
too if insv/extv instructions aren't used, so that
can be added later. We may be accessing data outside the field, which means
we can alias adjacent data. We may be accessing data outside the field, which means
we can alias adjacent data.
| rtx push_block | ( | ) |
Pushing data onto the stack.
Push a block of length SIZE (perhaps variable) and return an rtx to address the beginning of the block. The value may be virtual_outgoing_args_rtx. EXTRA is the number of bytes of padding to push in addition to SIZE. BELOW nonzero means this padding comes at low addresses; otherwise, the padding comes at high addresses.
References create_input_operand(), downward, emit_move_insn(), expand_binop(), gen_int_mode(), HOST_WIDE_INT, maybe_expand_insn(), offset, optab_handler(), and OPTAB_LIB_WIDEN.
|
static |
Extract one of the components of the complex value CPLX. Extract the real part if IMAG_P is false, and the imaginary part if it's true.
Special case reads from complex constants that got spilled to memory.
For MEMs simplify_gen_subreg may generate an invalid new address
because, e.g., the original address is considered mode-dependent
by the target, which restricts simplify_subreg from invoking
adjust_address_nv. Instead of preparing fallback support for an
invalid address, we call adjust_address_nv directly. If the sub-object is at least word sized, then we know that subregging
will work. This special case is important, since extract_bit_field
wants to operate on integer modes, and there's rarely an OImode to
correspond to TCmode. For hard regs we have exact predicates. Assume we can split
the original object if it spans an even number of hard regs.
This special case is important for SCmode on 64-bit platforms
where the natural size of floating-point regs is 32-bit. simplify_gen_subreg may fail for sub-word MEMs.
|
static |
Subroutine of above: reduce EXP to the precision of TYPE (in the signedness of TYPE), possibly returning the result in TARGET.
For constant values, reduce using build_int_cst_type.
| int safe_from_p | ( | ) |
Subroutine of expand_expr: return nonzero iff there is no way that EXP can reference X, which is being modified. TOP_P is nonzero if this call is going to be used to determine whether we need a temporary for EXP, as opposed to a recursive call to this function. It is always safe for this routine to return zero since it merely searches for optimization opportunities.
If EXP has varying size, we MUST use a target since we currently
have no way of allocating temporaries of variable size
(except for arrays that have TYPE_ARRAY_MAX_SIZE set).
So we assume here that something at a higher level has prevented a
clash. This is somewhat bogus, but the best we can do. Only
do this when X is BLKmode and when we are at the top level. If X is in the outgoing argument area, it is always safe.
If this is a subreg of a hard register, declare it unsafe, otherwise,
find the underlying pseudo. Now look at our tree code and possibly recurse.
The only case we look at here is the DECL_INITIAL inside a
DECL_EXPR. Fall through.
Now do code-specific tests. EXP_RTL is set to any rtx we find in
the expression. If it is set, we conflict iff we are that rtx or
both are in memory. Otherwise, we check all operands of the
expression recursively. If the operand is static or we are static, we can't conflict.
Likewise if we don't conflict with the operand at all. Otherwise, the only way this can conflict is if we are taking
the address of a DECL a that address if part of X, which is
very rare. Assume that the call will clobber all hard registers and
all of memory. Lowered by gimplify.c.
If we have an rtx, we do not need to scan our operands.
Should never get a type here.
If we have an rtl, find any enclosed object. Then see if we conflict
with it. If the rtl is X, then it is not safe. Otherwise, it is unless both
are memory and they conflict. If we reach here, it is safe.
References targetm.
Referenced by array_ref_element_size(), and expand_builtin_va_start().
| rtx set_storage_via_libcall | ( | ) |
A subroutine of clear_storage. Expand a call to memset. Return the return value of memset, 0 otherwise.
Emit code to copy OBJECT and SIZE into new pseudos. We can then
place those into new pseudos into a VAR_DECL and use them later. It is incorrect to use the libcall calling conventions to call
memset in this context. This could be a user call to memset and
the user may wish to examine the return value from memset. For
targets where libcalls and normal calls have different conventions
for returning pointers, we could end up generating incorrect code.
References emit_move_insn(), and simplify_gen_subreg().
| bool set_storage_via_setmem | ( | rtx | object, |
| rtx | size, | ||
| rtx | val, | ||
| unsigned int | align, | ||
| unsigned int | expected_align, | ||
| HOST_WIDE_INT | expected_size | ||
| ) |
Expand a setmem pattern; return true if successful.
Try the most limited insn first, because there's no point
including more than one in the machine description unless
the more limited one has some advantage. We don't need MODE to be narrower than
BITS_PER_HOST_WIDE_INT here because if SIZE is less than
the mode mask, as it is returned by the macro, it will
definitely be less than the actual mode mask. The check above guarantees that this size conversion is valid.
References copy_replacements(), gen_rtx_MEM(), push_operand(), reload_in_progress, simplify_gen_subreg(), and simplify_subreg().
|
static |
Return TRUE if expression STMT is suitable for replacement. Never consider memory loads as replaceable, because those don't ever lead into constant expressions.
Don't move around loads.
| rtx store_by_pieces | ( | rtx | to, |
| unsigned HOST_WIDE_INT | len, | ||
| rtx(*)(void *, HOST_WIDE_INT, enum machine_mode) | constfun, | ||
| void * | constfundata, | ||
| unsigned int | align, | ||
| bool | memsetp, | ||
| int | endp | ||
| ) |
Generate several move instructions to store LEN bytes generated by CONSTFUN to block TO. (A MEM rtx with BLKmode). CONSTFUNDATA is a pointer which will be passed as argument in every CONSTFUN call. ALIGN is maximum alignment we can assume. MEMSETP is true if this is a memset operation and false if it's a copy of a constant string. If ENDP is 0 return to, if ENDP is 1 return memory at the end ala mempcpy, and if ENDP is 2 return memory the end minus one byte ala stpcpy.
|
static |
Subroutine of clear_by_pieces and store_by_pieces. Generate several move instructions to store LEN bytes of block TO. (A MEM rtx with BLKmode). ALIGN is maximum alignment we can assume.
If storing requires more than two move insns,
copy addresses to registers (to make displacements shorter)
and use post-increment if available. Determine the main mode we'll be using.
MODE might not be used depending on the definitions of the
USE_* macros below. First store what we can in the largest integer mode, then go to
successively smaller modes. The code above should have handled everything.
|
static |
Subroutine of store_by_pieces_1. Store as many bytes as appropriate with move instructions for mode MODE. GENFUN is the gen_... function to make a move insn for that mode. DATA has all the other info.
|
static |
|
static |
Store the value of constructor EXP into the rtx TARGET. TARGET is either a REG or a MEM; we know it cannot conflict, since safe_from_p has been called. CLEARED is true if TARGET is known to have been zero'd. SIZE is the number of bytes of TARGET we are allowed to modify: this may not be the same as the size of EXP if we are assigning to a field which has been packed to exclude padding bits.
If size is zero or the target is already cleared, do nothing.
We either clear the aggregate or indicate the value is dead.
If the constructor is empty, clear the union.
If we are building a static constructor into a register,
set the initial value as zero so we can fold the value into
a constant. But if more than one register is involved,
this probably loses. If the constructor has fewer fields than the structure or
if we are initializing the structure to mostly zeros, clear
the whole structure first. Don't do this if TARGET is a
register whose mode size isn't equal to SIZE since
clear_storage can't handle this case. Store each element of the constructor into the
corresponding field of TARGET. Just ignore missing fields. We cleared the whole
structure, above, if any fields are missing. If this initializes a field that is smaller than a
word, at the start of a word, try to widen it to a full
word. This special case allows us to output C++ member
function initializations in a form that the optimizers
can understand. If we have constant bounds for the range of the type, get them.
If the constructor has fewer elements than the array, clear
the whole array first. Similarly if this is static
constructor of a non-BLKmode object. This loop is a more accurate version of the loop in
mostly_zeros_p (it handles RANGE_EXPR in an index). It
is also needed to check for missing elements. Clear the entire array first if there are any missing
elements, or if the incidence of zero elements is >=
75%. Inform later passes that the old value is dead.
Store each element of the constructor into the
corresponding element of TARGET, determined by counting the
elements. If the range is constant and "small", unroll the loop.
Build the head of the loop.
Assign value to element index.
Generate a conditional jump to exit the loop.
Update the loop counter, and jump to the head of
the loop. Build the end of the loop.
If the constructor has fewer elements than the vector,
clear the whole array first. Similarly if this is static
constructor of a non-BLKmode object. Clear the entire vector first if there are any missing elements,
or if the incidence of zero elements is >= 75%. Inform later passes that the old value is dead.
Store each element of the constructor into the corresponding
element of TARGET, determined by counting the elements. Vector CONSTRUCTORs should only be built from smaller
vectors in the case of BLKmode vectors.
|
static |
Helper function for store_constructor. TARGET, BITSIZE, BITPOS, MODE, EXP are as for store_field. CLEARED is as for store_constructor. ALIAS_SET is the alias set to use for any stores. This provides a recursive shortcut back to store_constructor when it isn't necessary to go through store_field. This is so that we can pass through the cleared field to let store_constructor know that we may not have to clear a substructure if the outer structure has already been cleared.
We can only call store_constructor recursively if the size and
bit position are on a byte boundary. If we have a nonzero bitpos for a register target, then we just
let store_field do the bitfield handling. This is unlikely to
generate unnecessary clear instructions anyways. Update the alias set, if required.
Referenced by all_zeros_p().
| rtx store_expr | ( | ) |
Generate code for computing expression EXP, and storing the value into TARGET. If the mode is BLKmode then we may return TARGET itself. It turns out that in BLKmode it doesn't cause a problem. because C has no operators that could combine two different assignments into the same BLKmode object with different values with no sequence point. Will other languages need this to be more thorough? If CALL_PARAM_P is nonzero, this is a store into a call param on the stack, and block moves may need to be treated specially. If NONTEMPORAL is true, try using a nontemporal store instruction.
C++ can generate ?: expressions with a throw expression in one
branch and an rvalue in the other. Here, we resolve attempts to
store the throw expression's nonexistent result. Perform first part of compound expression, then assign from second
part. For conditional expression, get safe form of the target. Then
test the condition, doing the appropriate assignment on either
side. This avoids the creation of unnecessary temporaries.
For non-BLKmode, it is more efficient not to do this. If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
expression. We can do the conversion inside EXP, which will often result
in some optimizations. Do the conversion in two steps: first
change the signedness, if needed, then the extend. But don't
do this if the type of EXP is a subtype of something else
since then the conversion might involve more than just
converting modes. Some types, e.g. Fortran's logical*4, won't have a signed
version, so use the mode instead. If TEMP is a VOIDmode constant, use convert_modes to make
sure that we properly convert it. Optimize initialization of an array with a STRING_CST.
If we want to use a nontemporal store, force the value to
register first. If TEMP is a VOIDmode constant and the mode of the type of EXP is not
the same as that of TARGET, adjust the constant. This is needed, for
example, in case it is a CONST_DOUBLE and we want only a word-sized
value. If value was not generated in the target, store it there.
Convert the value to TARGET's type first if necessary and emit the
pending incrementations that have been queued when expanding EXP.
Note that we cannot emit the whole queue blindly because this will
effectively disable the POST_INC optimization later.
If TEMP and TARGET compare equal according to rtx_equal_p, but
one or both of them are volatile memory refs, we have to distinguish
two cases:
- expand_expr has used TARGET. In this case, we must not generate
another copy. This can be detected by TARGET being equal according
to == .
- expand_expr has not used TARGET - that means that the source just
happens to have the same RTX form. Since temp will have been created
by expand_expr, it will compare unequal according to == .
We must generate a copy in this case, to reach the correct number
of volatile memory references. If store_expr stores a DECL whose DECL_RTL(exp) == TARGET,
but TARGET is not valid memory reference, TEMP will differ
from TARGET although it is really the same location. If there's nothing to copy, don't bother. Don't call
expr_size unless necessary, because some front-ends (C++)
expr_size-hook must not be given objects that are not
supposed to be bit-copied or bit-initialized. Handle calls that return BLKmode values in registers.
Handle copying a string constant into an array. The string
constant may be shorter than the array. So copy just the string's
actual length, and clear the rest. First get the size of the data
type of the string, which is actually the size of the target. Compute the size of the data to copy from the string.
Copy that much.
Figure out how much is left in TARGET that we have to clear.
Do all calculations in pointer_mode. Handle calls that return values in multiple non-contiguous locations.
The Irix 6 ABI has examples of this. If we emit a nontemporal store, there is nothing else to do.
Referenced by initialize_argument_information().
|
static |
Store the value of EXP (an expression tree) into a subfield of TARGET which has mode MODE and occupies BITSIZE bits, starting BITPOS bits from the start of TARGET. If MODE is VOIDmode, it means that we are storing into a bit-field. BITREGION_START is bitpos of the first bitfield in this region. BITREGION_END is the bitpos of the ending bitfield in this region. These two fields are 0, if the C++ memory model does not apply, or we are not interested in keeping track of bitfield regions. Always return const0_rtx unless we have something particular to return. ALIAS_SET is the alias set for the destination. This value will (in general) be different from that for TARGET, since TARGET is a reference to the containing structure. If NONTEMPORAL is true, try generating a nontemporal store.
If we have nothing to store, do nothing unless the expression has
side-effects. We're storing into a struct containing a single __complex.
If the structure is in a register or if the component
is a bit field, we cannot use addressing to access it.
Use bit-field techniques or SUBREG to store in it. If the field isn't aligned enough to store as an ordinary memref,
store it as a bit field. If the RHS and field are a constant size and the size of the
RHS isn't the same size as the bitfield, we must use bitfield
operations. If we are expanding a MEM_REF of a non-BLKmode non-addressable
decl we must use bitfield operations. If EXP is a NOP_EXPR of precision less than its mode, then that
implies a mask operation. If the precision is the same size as
the field we're storing into, that mask is redundant. This is
particularly common with bit field assignments generated by the
C front end. If BITSIZE is narrower than the size of the type of EXP
we will be narrowing TEMP. Normally, what's wanted are the
low-order bits. However, if EXP's type is a record and this is
big-endian machine, we want the upper BITSIZE bits. Unless MODE is VOIDmode or BLKmode, convert TEMP to MODE.
If the modes of TEMP and TARGET are both BLKmode, both
must be in memory and BITPOS must be aligned on a byte
boundary. If so, we simply do a block copy. Likewise
for a BLKmode-like TARGET. Handle calls that return values in multiple non-contiguous locations.
The Irix 6 ABI has examples of this. Handle calls that return BLKmode values in registers.
Store the value in the bitfield.
Now build a reference to just the desired component.
| tree string_constant | ( | ) |
Return the tree node if an ARG corresponds to a string constant or zero if it doesn't. If we return nonzero, set *PTR_OFFSET to the offset in bytes within the string that ARG is accessing. The type of the offset will be `sizetype'.
Check if the array has a nonzero lower bound.
If the offset and base aren't both constants, return 0.
Adjust offset by the lower bound.
Variables initialized to string literals can be handled too.
Avoid const char foo[4] = "abcde";
If variable is bigger than the string literal, OFFSET must be constant
and inside of the bounds of the string literal.
Referenced by constant_pointer_difference(), get_pointer_alignment(), and maybe_emit_chk_warning().
|
static |
Alignment in bits the TARGET of an assignment may be assumed to have.
We might have a chain of nested references with intermediate misaligning
bitfields components, so need to recurse to find out.
| int try_casesi | ( | tree | index_type, |
| tree | index_expr, | ||
| tree | minval, | ||
| tree | range, | ||
| rtx | table_label, | ||
| rtx | default_label, | ||
| rtx | fallback_label, | ||
| int | default_probability | ||
| ) |
Attempt to generate a casesi instruction. Returns 1 if successful, 0 otherwise (i.e. if there is no casesi instruction). DEFAULT_PROBABILITY is the probability of jumping to the default label.
Convert the index to SImode.
We must handle the endpoints in the original mode.
Now we can safely truncate.
| int try_tablejump | ( | tree | index_type, |
| tree | index_expr, | ||
| tree | minval, | ||
| tree | range, | ||
| rtx | table_label, | ||
| rtx | default_label, | ||
| int | default_probability | ||
| ) |
|
static |
Return true if word I of OP lies entirely in the undefined bits of a paradoxical subreg.
The SUBREG_BYTE represents offset, as if the value were stored in
memory, except for a paradoxical subreg where we define
SUBREG_BYTE to be 0; undo this exception as in
simplify_subreg.
| void use_group_regs | ( | ) |
Add USE expressions to *CALL_FUSAGE for each REG contained in the PARALLEL REGS. This is for calls that pass values in multiple non-contiguous locations. The Irix 6 ABI has examples of this.
A NULL entry means the parameter goes both on the stack and in
registers. This can also be a MEM for targets that pass values
partially on the stack and partially in registers.
References store_by_pieces_d::to.
| void use_reg_mode | ( | ) |
Add a USE expression for REG to the (possibly empty) list pointed to by CALL_FUSAGE. REG must denote a hard register.
| void use_regs | ( | ) |
Add USE expressions to *CALL_FUSAGE for each of NREGS consecutive regs, starting at REGNO. All of these registers must be hard registers.
References get_address_mode().
|
static |
Return the widest integer mode no wider than SIZE. If no such mode can be found, return VOIDmode.
Referenced by can_move_by_pieces().
Referenced by clear_by_pieces().
|
static |
Write to one of the components of the complex value CPLX. Write VAL to the real part if IMAG_P is false, and the imaginary part if its true.
For MEMs simplify_gen_subreg may generate an invalid new address
because, e.g., the original address is considered mode-dependent
by the target, which restricts simplify_subreg from invoking
adjust_address_nv. Instead of preparing fallback support for an
invalid address, we call adjust_address_nv directly. If the sub-object is at least word sized, then we know that subregging
will work. This special case is important, since store_bit_field
wants to operate on integer modes, and there's rarely an OImode to
correspond to TCmode. For hard regs we have exact predicates. Assume we can split
the original object if it spans an even number of hard regs.
This special case is important for SCmode on 64-bit platforms
where the natural size of floating-point regs is 32-bit. simplify_gen_subreg may fail for sub-word MEMs.
| tree block_clear_fn |
A subroutine of set_storage_via_libcall. Create the tree node for the function we use for block clears.
|
static |
A subroutine of emit_block_move_via_libcall. Create the tree node for the function we use for block copies.
| int cse_not_expected |
If this is nonzero, we do not bother generating VOLATILE around volatile memory references, and we are willing to output indirect addresses. If cse is to follow, we reject indirect addresses so a useful potential cse is generated; if it is used only once, instruction combination will produce the same indirect address eventually.
1.8.1.1